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2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
The newer update-copyright.py fixes file encoding too, removing cr/lf on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
2022-05-11opcodes cgen: remove use of PTRAlan Modra1-1/+1
Note that opcodes is regenerated with cgen commit d1dd5fcc38e reverted, due to failure of bpf to compile with that patch applied. .../opcodes/bpf-opc.c:57:11: error: conversion from ‘long unsigned int’ to ‘unsigned int’ changes value from ‘18446744073709486335’ to ‘4294902015’ [-Werror=overflow] 57 | 64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } plus other similar errors. cpu/ * mep.opc (print_tpreg, print_spreg): Delete unnecessary forward declarations. Replace PTR with void *. * mt.opc (print_dollarhex, print_pcrel): Delete forward decls. opcodes/ * bpf-desc.c, * bpf-dis.c, * cris-desc.c, * epiphany-desc.c, * epiphany-dis.c, * fr30-desc.c, * fr30-dis.c, * frv-desc.c, * frv-dis.c, * ip2k-desc.c, * ip2k-dis.c, * iq2000-desc.c, * iq2000-dis.c, * lm32-desc.c, * lm32-dis.c, * m32c-desc.c, * m32c-dis.c, * m32r-desc.c, * m32r-dis.c, * mep-desc.c, * mep-dis.c, * mt-desc.c, * mt-dis.c, * or1k-desc.c, * or1k-dis.c, * xc16x-desc.c, * xc16x-dis.c, * xstormy16-desc.c, * xstormy16-dis.c: Regenerate.
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out */po/*.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-06-04opcodes: discriminate endianness and insn-endianness in CGEN portsJose E. Marchesi1-1/+1
The CGEN support code in opcodes accesses instruction contents using a couple of functions defined in cgen-opc.c: cgen_get_insn_value and cgen_put_insn_value. These functions use the "instruction endianness" in the CPU description to order the read/written bytes. The process of writing an instruction to the object file is: a) cgen_put_insn_value ;; Writes out the opcodes. b) ARCH_cgen_insert_operand insert_normal insert_1 cgen_put_insn_value ;; Writes out the bytes of the ;; operand. Likewise, the process of reading an instruction from the object file is: a) cgen_get_insn_value ;; Reads the opcodes. b) ARCH_cgen_extract_operand extract_normal extract_1 cgen_get_insn_value ;; Reads in the bytes of the ;; operand. As can be seen above, cgen_{get,put}_insn_value are used to both process the instruction opcodes (the constant fields conforming the base instruction) and also the values of the instruction operands, such as immediates. This is problematic for architectures in which the endianness of instructions is different to the endianness of data. An example is BPF, where instructions are always encoded big-endian but the data may be either big or little. This patch changes the cgen_{get,put}_insn_value functions in order to get an extra argument with the endianness to use, and adapts the existin callers to these functions in order to provide cd->endian or cd->insn_endian, whatever appropriate. Callers like extract_1 and insert_1 pass cd->endian (since they are reading/writing operand values) while callers reading/writing the base instruction pass cd->insn_endian instead. A few little adjustments have been needed in some existing CGEN based ports: * The BPF assembler uses cgen_put_insn_value. It has been adapted to pass the new endian argument. * The mep port has code in mep.opc that uses cgen_{get,put}_insn_value. It has been adapted to pass the new endianargument. Ditto for a call in the assembler. Tested with --enable-targets=all. Regested in all supported targets. No regressions. include/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/cgen.h: Get an `endian' argument in both cgen_get_insn_value and cgen_put_insn_value. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument. (cgen_put_insn_value): Likewise. (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value. * cgen-dis.in (print_insn): Likewise. * cgen-ibld.in (insert_1): Likewise. (insert_1): Likewise. (insert_insn_normal): Likewise. (extract_1): Likewise. * bpf-dis.c: Regenerate. * bpf-ibld.c: Likewise. * bpf-ibld.c: Likewise. * cgen-dis.in: Likewise. * cgen-ibld.in: Likewise. * cgen-opc.c: Likewise. * epiphany-dis.c: Likewise. * epiphany-ibld.c: Likewise. * fr30-dis.c: Likewise. * fr30-ibld.c: Likewise. * frv-dis.c: Likewise. * frv-ibld.c: Likewise. * ip2k-dis.c: Likewise. * ip2k-ibld.c: Likewise. * iq2000-dis.c: Likewise. * iq2000-ibld.c: Likewise. * lm32-dis.c: Likewise. * lm32-ibld.c: Likewise. * m32c-dis.c: Likewise. * m32c-ibld.c: Likewise. * m32r-dis.c: Likewise. * m32r-ibld.c: Likewise. * mep-dis.c: Likewise. * mep-ibld.c: Likewise. * mt-dis.c: Likewise. * mt-ibld.c: Likewise. * or1k-dis.c: Likewise. * or1k-ibld.c: Likewise. * xc16x-dis.c: Likewise. * xc16x-ibld.c: Likewise. * xstormy16-dis.c: Likewise. * xstormy16-ibld.c: Likewise. gas/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen.c (gas_cgen_finish_insn): Pass the endianness to cgen_put_insn_value. (gas_cgen_md_apply_fix): Likewise. (gas_cgen_md_apply_fix): Likewise. * config/tc-bpf.c (md_apply_fix): Pass data endianness to cgen_put_insn_value. * config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to cgen_put_insn_value. cpu/ChangeLog: 2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com> * mep.opc (print_slot_insn): Pass the insn endianness to cgen_get_insn_value.
2020-06-04opcodes: support insn endianness in cgen_cpu_openJose E. Marchesi1-0/+7
This patch adds support for a new CGEN_OPEN_INSN_ENDIAN argument for @arch@_cgen_cpu_open. This is useful for architectures in which the endianness of the instruction words is not the same than the endianness used for data. An accompanying patch has been sent to the CGEN mailing list that adds support for this argument on the CGEN side [1]. Its been already pre-approved [2], and will be applied simultaneously with this binutils series. [1] https://sourceware.org/pipermail/cgen/2020q2/002733.html [2] https://sourceware.org/pipermail/cgen/2020q2/002737.html include/ChangeLog: 2020-06-04 Jose E. Marchesi <jemarch@gnu.org> * opcode/cgen.h (enum cgen_cpu_open_arg): New value CGEN_CPU_OPEN_INSN_ENDIAN. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi <jemarch@gnu.org> * cgen-dis.in (cpu_desc_list): New field `insn_endian'. (print_insn_): Handle instruction endian. * bpf-dis.c: Regenerate. * bpf-desc.c: Regenerate. * epiphany-dis.c: Likewise. * epiphany-desc.c: Likewise. * fr30-dis.c: Likewise. * fr30-desc.c: Likewise. * frv-dis.c: Likewise. * frv-desc.c: Likewise. * ip2k-dis.c: Likewise. * ip2k-desc.c: Likewise. * iq2000-dis.c: Likewise. * iq2000-desc.c: Likewise. * lm32-dis.c: Likewise. * lm32-desc.c: Likewise. * m32c-dis.c: Likewise. * m32c-desc.c: Likewise. * m32r-dis.c: Likewise. * m32r-desc.c: Likewise. * mep-dis.c: Likewise. * mep-desc.c: Likewise. * mt-dis.c: Likewise. * mt-desc.c: Likewise. * or1k-dis.c: Likewise. * or1k-desc.c: Likewise. * xc16x-dis.c: Likewise. * xc16x-desc.c: Likewise. * xstormy16-dis.c: Likewise. * xstormy16-desc.c: Likewise. binutils/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * objdump.c (disassemble_data): Set disasm_info.endian_code to disasm_info.endian after the latter is initialized to the endianness reported by BFD.
2020-05-19or1k: Regenerate opcodes after removing 32-bit supportStafford Horne1-9/+0
opcodes/ChangeLog: yyyy-mm-dd Stafford Horne <shorne@gmail.com> PR 25184 * or1k-asm.c: Regenerate. * or1k-desc.c: Regenerate. * or1k-desc.h: Regenerate. * or1k-dis.c: Regenerate. * or1k-ibld.c: Regenerate. * or1k-opc.c: Regenerate. * or1k-opc.h: Regenerate. * or1k-opinst.c: Regenerate.
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-12-10Use disassemble_info.private_data in place of insn_setsAlan Modra1-1/+1
No cgen target uses private_data. This patch removes a disassemble_info field that is only used by cgen, and instead uses private_data. It also removes a macro that is no longer used. include/ * dis-asm.h (struct disassemble_info): Delete insn_sets. (INIT_DISASSEMBLE_INFO_NO_ARCH): Don't define. opcodes/ * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data. * disassemble.c (disassemble_init_for_target): Likewise. * bpf-dis.c: Regenerate. * epiphany-dis.c: Regenerate. * fr30-dis.c: Regenerate. * frv-dis.c: Regenerate. * ip2k-dis.c: Regenerate. * iq2000-dis.c: Regenerate. * lm32-dis.c: Regenerate. * m32c-dis.c: Regenerate. * m32r-dis.c: Regenerate. * mep-dis.c: Regenerate. * mt-dis.c: Regenerate. * or1k-dis.c: Regenerate. * xc16x-dis.c: Regenerate. * xstormy16-dis.c: Regenerate.
2019-06-13opcodes/or1k: Regenerate opcodesStafford Horne1-2/+41
This picks up changes for: - new orfpx64a32 spec additions - new unordered instructions - symbol and documentation updates opcodes/ChangeLog: * or1k-asm.c: Regenerated. * or1k-desc.c: Regenerated. * or1k-desc.h: Regenerated. * or1k-dis.c: Regenerated. * or1k-ibld.c: Regenerated. * or1k-opc.c: Regenerated. * or1k-opc.h: Regenerated. * or1k-opinst.c: Regenerated.
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-10-05or1k: Add the l.adrp insn and supporting relocationsStafford Horne1-0/+3
This patch adds the new instruction and relocation as per proposal: https://openrisc.io/proposals/ladrp This is to be added to the spec in an upcoming revision. The new instruction l.adrp loads the page offset of the current instruction offset by a 21-bit immediate shifted left 13-bits. This is meant to be used with a 13-bit lower bit page offset. This allows us to free up the got register r16. l.adrp r3, foo l.ori r4, r3, po(foo) l.lbz r5, po(foo)(r3) l.sb po(foo)(r3), r6 The relocations we add are: - BFD_RELOC_OR1K_PLTA26 For PLT jump relocation with PLT entry asm: plta() implemented using l.ardp, meaning no need for r16 (the GOT reg) - BFD_RELOC_OR1K_GOT_PG21 Upper 21-bit Page offset got address asm: got() - BFD_RELOC_OR1K_TLS_GD_PG21 Upper 21-bit Page offset with TLS General asm: tlsgd() Dynamic calculation - BFD_RELOC_OR1K_TLS_LDM_PG21 Upper 21-bit Page offset with TLS local asm: tlsldm() dynamic calculation - BFD_RELOC_OR1K_TLS_IE_PG21 Upper 21-bit Page offset with TLS Initial asm: gottp() Executable calculation - BFD_RELOC_OR1K_PCREL_PG21 Default relocation for disp21 (l.adrp instructions) - BFD_RELOC_OR1K_LO13 low 13-bit page offset relocation asm: po() i.e. mem loads, addi etc - BFD_RELOC_OR1K_SLO13 low 13-bit page offset relocation asm: po() i.e. mem stores, with split immediate - BFD_RELOC_OR1K_GOT_LO13, low 13-bit page offset with GOT calcs asm: gotpo() - BFD_RELOC_OR1K_TLS_GD_LO13 Lower 13-bit offset with TLS GD calcs asm: tlsgdpo() - BFD_RELOC_OR1K_TLS_LDM_LO13 Lower 13-bit offset with TLS LD calcs asm: tlsldmpo() - BFD_RELOC_OR1K_TLS_IE_LO13 Lower 13-bit offset with TLS IE calcs asm: gottppo() bfd/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * bfd-in2.h: Regenerated. * elf32-or1k.c: (or1k_elf_howto_table): Fix formatting for R_OR1K_PLT26, Add R_OR1K_PCREL_PG21, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_SLO13, R_OR1K_PLTA26. (or1k_reloc_map): Add BFD_RELOC_OR1K_PCREL_PG21, BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_TLS_GD_PG21, BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_IE_PG21, BFD_RELOC_OR1K_LO13, BFD_RELOC_OR1K_GOT_LO13, BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_LO13, BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_PLTA26. (elf_or1k_link_hash_table): Add field saw_plta. (or1k_final_link_relocate): Add value calculations for new relocations. (or1k_elf_relocate_section): Add section relocations for new relocations. (or1k_write_plt_entry): New function. (or1k_elf_finish_dynamic_sections): Add support for PLTA relocations using new l.adrp instruction. Cleanup PLT relocation code generation. * libbfd.h: Regenerated. * reloc.c: Add BFD_RELOC_OR1K_PCREL_PG21, BFD_RELOC_OR1K_LO13, BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_GOT_LO13, BFD_RELOC_OR1K_PLTA26, BFD_RELOC_OR1K_TLS_GD_PG21, BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21, BFD_RELOC_OR1K_TLS_IE_LO13. cpu/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * or1k.opc (parse_disp26): Add support for plta() relocations. (parse_disp21): New function. (or1k_rclass): New enum. (or1k_rtype): New enum. (or1k_imm16_relocs): Define new PO and SPO relocation mappings. (parse_reloc): Add new po(), gotpo() and gottppo() for LO13 relocations. (parse_imm16): Add support for the new 21bit and 13bit relocations. * or1korbis.cpu (f-disp26): Don't assume SI. (f-disp21): New pc-relative 21-bit 13 shifted to right. (insn-opcode): Add ADRP. (l-adrp): New instruction. gas/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * config/tc-or1k.c (or1k_apply_fix): Add BFD_RELOC_OR1K_TLS_GD_PG21, BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21, BFD_RELOC_OR1K_TLS_IE_LO13. * testsuite/gas/or1k/allinsn.s: Add test for l.adrp. * testsuite/gas/or1k/allinsn.d: Add test results for new instructions. * testsuite/gas/or1k/reloc-1.s: Add tests to generate R_OR1K_PLTA26, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLD_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_LO13, R_OR1K_SLO13 relocations. * testsuite/gas/or1k/reloc-1.d: Add relocation results for tests. * testsuite/gas/or1k/reloc-2.s: Add negative tests for store to gotpo(). * testsuite/gas/or1k/reloc-2.l: Add expected error test results. ld/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * testsuite/ld-or1k/or1k.exp: Add test cases for plt generation. * testsuite/ld-or1k/plt1.dd: New file. * testsuite/ld-or1k/plt1.s: New file. * testsuite/ld-or1k/plt1.x.dd: New file. * testsuite/ld-or1k/plta1.dd: New file. * testsuite/ld-or1k/plta1.s: New file. * testsuite/ld-or1k/pltlib.s: New file. include/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_PCREL_PG21, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_SLO13, R_OR1K_PLTA26. opcodes/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * or1k-asm.c: Regenerated. * or1k-desc.c: Regenerated. * or1k-desc.h: Regenerated. * or1k-dis.c: Regenerated. * or1k-ibld.c: Regenerated. * or1k-opc.c: Regenerated. * or1k-opc.h: Regenerated. * or1k-opinst.c: Regenerated.
2018-03-03opcodes error messagesAlan Modra1-3/+4
Another patch aimed at making binutils comply with the GNU coding standard. The generated files require https://sourceware.org/ml/cgen/2018-q1/msg00004.html cpu/ * frv.opc: Include opintl.h. (add_next_to_vliw): Use opcodes_error_handler to print error. Standardize error message. (fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise. opcodes/ * sysdep.h (opcodes_error_handler): Define. (_bfd_error_handler): Declare. * Makefile.am: Remove stray #. * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT EDIT" comment. * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c, * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c, * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use opcodes_error_handler to print errors. Standardize error messages. * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise, and include opintl.h. * nds32-asm.c: Likewise, and include sysdep.h and opintl.h. * i386-gen.c: Standardize error messages. * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate. * Makefile.in: Regenerate. * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c, * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c, * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c, * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c, * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c, * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c, * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c, * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c, * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c, * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c, * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c, * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-07-11Mark generated cgen files read-onlyAlan Modra1-0/+1
* cgen.sh: Mark generated files read-only. * epiphany-asm.c: Regenerate. * epiphany-desc.c: Regenerate. * epiphany-desc.h: Regenerate. * epiphany-dis.c: Regenerate. * epiphany-ibld.c: Regenerate. * epiphany-opc.c: Regenerate. * epiphany-opc.h: Regenerate. * fr30-asm.c: Regenerate. * fr30-desc.c: Regenerate. * fr30-desc.h: Regenerate. * fr30-dis.c: Regenerate. * fr30-ibld.c: Regenerate. * fr30-opc.c: Regenerate. * fr30-opc.h: Regenerate. * frv-asm.c: Regenerate. * frv-desc.c: Regenerate. * frv-desc.h: Regenerate. * frv-dis.c: Regenerate. * frv-ibld.c: Regenerate. * frv-opc.c: Regenerate. * frv-opc.h: Regenerate. * ip2k-asm.c: Regenerate. * ip2k-desc.c: Regenerate. * ip2k-desc.h: Regenerate. * ip2k-dis.c: Regenerate. * ip2k-ibld.c: Regenerate. * ip2k-opc.c: Regenerate. * ip2k-opc.h: Regenerate. * iq2000-asm.c: Regenerate. * iq2000-desc.c: Regenerate. * iq2000-desc.h: Regenerate. * iq2000-dis.c: Regenerate. * iq2000-ibld.c: Regenerate. * iq2000-opc.c: Regenerate. * iq2000-opc.h: Regenerate. * lm32-asm.c: Regenerate. * lm32-desc.c: Regenerate. * lm32-desc.h: Regenerate. * lm32-dis.c: Regenerate. * lm32-ibld.c: Regenerate. * lm32-opc.c: Regenerate. * lm32-opc.h: Regenerate. * lm32-opinst.c: Regenerate. * m32c-asm.c: Regenerate. * m32c-desc.c: Regenerate. * m32c-desc.h: Regenerate. * m32c-dis.c: Regenerate. * m32c-ibld.c: Regenerate. * m32c-opc.c: Regenerate. * m32c-opc.h: Regenerate. * m32r-asm.c: Regenerate. * m32r-desc.c: Regenerate. * m32r-desc.h: Regenerate. * m32r-dis.c: Regenerate. * m32r-ibld.c: Regenerate. * m32r-opc.c: Regenerate. * m32r-opc.h: Regenerate. * m32r-opinst.c: Regenerate. * mep-asm.c: Regenerate. * mep-desc.c: Regenerate. * mep-desc.h: Regenerate. * mep-dis.c: Regenerate. * mep-ibld.c: Regenerate. * mep-opc.c: Regenerate. * mep-opc.h: Regenerate. * mt-asm.c: Regenerate. * mt-desc.c: Regenerate. * mt-desc.h: Regenerate. * mt-dis.c: Regenerate. * mt-ibld.c: Regenerate. * mt-opc.c: Regenerate. * mt-opc.h: Regenerate. * or1k-asm.c: Regenerate. * or1k-desc.c: Regenerate. * or1k-desc.h: Regenerate. * or1k-dis.c: Regenerate. * or1k-ibld.c: Regenerate. * or1k-opc.c: Regenerate. * or1k-opc.h: Regenerate. * or1k-opinst.c: Regenerate. * xc16x-asm.c: Regenerate. * xc16x-desc.c: Regenerate. * xc16x-desc.h: Regenerate. * xc16x-dis.c: Regenerate. * xc16x-ibld.c: Regenerate. * xc16x-opc.c: Regenerate. * xc16x-opc.h: Regenerate. * xstormy16-asm.c: Regenerate. * xstormy16-desc.c: Regenerate. * xstormy16-desc.h: Regenerate. * xstormy16-dis.c: Regenerate. * xstormy16-ibld.c: Regenerate. * xstormy16-opc.c: Regenerate. * xstormy16-opc.h: Regenerate.
2017-05-24Move print_insn_XXX to an opcodes internal headerYao Qi1-1/+1
With the changes done in previous patches, print_insn_XXX functions don't have to be external visible out of opcodes, because both gdb and objdump select disassemblers through a single interface. This patch moves these print_insn_XXX declarations from include/dis-asm.h to opcodes/disassemble.h, which is a new header added by this patch. include: 2017-05-24 Yao Qi <yao.qi@linaro.org> * dis-asm.h: Move some function declarations to opcodes/disassemble.h. opcodes: 2017-05-24 Yao Qi <yao.qi@linaro.org> * alpha-dis.c: Include disassemble.h, don't include dis-asm.h. * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise. * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise. * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise. * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise. * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise. * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise. * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise. * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise. * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise. * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise. * moxie-dis.c, msp430-dis.c, mt-dis.c: * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise. * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise. * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise. * rl78-dis.c, s390-dis.c, score-dis.c: Likewise. * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise. * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise. * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise. * v850-dis.c, vax-dis.c, visium-dis.c: Likewise. * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise. * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise. * z80-dis.c, z8k-dis.c: Likewise. * disassemble.h: New file.
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-08-12Remove trailing spaces in opcodesH.J. Lu1-5/+5
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-06-12Whitespace fixes for cpu/or1k.opcAlan Modra1-2/+1
* or1k.opc: Whitespace fixes.
2014-04-22Remove support for the (deprecated) openrisc and or32 configurations and replaceChristian Svensson1-0/+562
with support for the new or1k configuration.
generated by cgit v1.1 at 2024-08-13 00:23:47 +0000