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1997-03-07update copyrights.Jeff Law1-1/+1
1997-03-06 * mn10300-opc.c (IMM16_PCREL, SD8N_PCREL, D16_SHIFT): Mark theseJeff Law1-3/+3
as relaxable. For the relaxing assembler.
1996-12-16 * mn10300-opc.c (mn10300_opcodes): Add "break" instruction.Jeff Law1-0/+8
For gdb.
1996-12-06 * mn10300-opc.c: Add some comments explaining the variousJeff Law1-1/+42
operands and such. * mn10300-dis.c (disassemble): Fix minor gcc -Wall warnings.
1996-11-26 * mn10300-opc.c (mn10300_opcodes): Fix mask field forJeff Law1-1/+1
mov am,(imm32,sp). Found during initial simulator work.
1996-11-25 * mn10300-opc.c (mn10300_opcodes): Remove redundant "lcc"Jeff Law1-1/+0
opcode.
1996-11-20 * mn10300-opc.c: Fix handling of register list operand forJeff Law1-9/+9
"call", "ret", and "rets" instructions. Stuff noticed while working on disasembler.
1996-11-20 * mn10300-dis.c (disassemble): Print PC-relative and memoryJeff Law1-41/+56
addresses symbolically if possible. * mn10300-opc.c: Distinguish between absolute memory addresses, pc-relative offsets & random immediates. More disassembler work.
1996-11-19 * mn10300-dis.c: Start working on disassembler support.Jeff Law1-6/+6
* mn10300-opc.c (mn10300_opcodes): Fix masks on several insns. Selects opcodes & consumes bytes. Breaks badly if given data instead of code. No operands yet.
1996-11-19 * mn10300-opc.c (mn10300_operands): Add "REGS" for a registerJeff Law1-2/+5
list. (mn10300_opcodes): Use REGS for register list in "movm" instructions.
1996-11-15 * mn10300-opc.c (mn10300_opcodes): Demand parens aroundJeff Law1-2/+2
register argument is calls and jmp instructions. Found trying to build libgcc2 for the mn10300 :-)
1996-11-07 * mn10300-opc.c (mn10300_opcodes): Use DN01 for putx andJeff Law1-5/+5
getx operand. Fix opcode for mulqu imm,dn. Fix bugs exposed by gas testsuite (extended instructions).
1996-11-06 * mn10300-opc.c (mn10300_operands): Hijack "bits" fieldJeff Law1-8/+35
in MN10300_OPERAND_SPLIT operands for how many bits appear in the basic insn word. Add IMM32_HIGH24, IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8. (mn10300_opcodes): Use new operands as needed. Support for everything in the basic instruction manual (yippie!)
1996-11-06 * mn10300-opc.c (mn10300_operands): Add IMM32_LOWSHIFT8Jeff Law1-5/+16
for bset, bclr, btst instructions. (mn10300_opcodes): Use new IMM32_LOWSHIFT8 as needed. For btst, bclr & bset.
1996-11-06 * mn10300-opc.c (mn10300_operands): Remove many redundantJeff Law1-77/+62
operands. Update opcode table as appropriate. (IMM32): Add MN10300_OPERAND_SPLIT flag. (mn10300_opcodes): Fix single bit error in mov imm32,dn insn. Cleaning up a little. Attempting to insert most 32bit operands. And a bug found by assembler testsuite.
1996-11-05 * mn10300-opc.c (mn10300_operands): Add DN2, DM2, AN2, AM2Jeff Law1-20/+47
operands (for indexed load/stores). Fix bitpos for DI operand. Add SN8N_SHIFT8, IMM8_SHIFT8, and D16_SHIFT for the few instructions that insert immediates/displacements in the middle of the instruction. Add IMM8E for 8 bit immediate in the extended part of an instruction. (mn10300_operands): Use new opcodes as appropriate. Opcode table changes so we can correctly insert everything except 32bit operands.
1996-11-04 * mn10300-opc.c (mn10300_operands): Add DN01 and AN01 forJeff Law1-4/+11
a data/address register that appears in register field 0 and register field 1. (mn10300_opcodes): Use DN01 and AN01 for mov/cmp imm8,DN/AN Hacking Matsushita again. Yippie!
1996-10-11 * mn10300-opc.c (mn10300_opcodes): Fix typo in opcodeJeff Law1-1/+1
field for movhu instruction. Bug found by gas testsuite. * v850-dis.c (disassemble): For V850_OPERAND_SIGNED operands, cast value to "long" not "signed long" to keep hpux10 compiler quiet. Found in an attempt to build the v850 on hpux10 with the HP compiler.
1996-10-10 * mn10300-opc.c (FMT*): Remove definitions.Jeff Law1-15/+0
Moved into opcode/mn10300.h
1996-10-10 * mn10300-opc.c (mn10300_opcodes): Fix destination registerJeff Law1-3/+3
for shift-by-register opcodes. Bug found by testsuite.
1996-10-10 * mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AMJeff Law1-200/+212
into [AD][MN][01] for encoding the position of the register in the opcode. Matsushita.
1996-10-09 * mn10300-opc.c (mn10300_opcodes): Add "extended" instructions,Jeff Law1-0/+14
"putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch". Matsushita.
1996-10-08 * mn10300-opc.c (mn10300_operands): Remove "REGS" operand.Jeff Law1-245/+247
Fix various typos. Add "PAREN" operand. (MEM, MEM2): Define. (mn10300_opcodes): Surround all memory addresses with "PAREN" operands. Fix several typos. Should parse all opcodes in the instruction specification, except the "user extension instructions".
1996-10-08 * mn10300-opc.c (mn10300_opcodes): Fix typos in yesterday'sJeff Law1-2/+2
changes. Matsushita.
1996-10-07 * mn10300-opc.c (FMT_XX): Renumber starting at one.Jeff Law1-268/+318
(mn10300_operands): Rough cut. Enough to parse "mov" instructions at this time. (mn10300_opcodes): Break opcode format out into its own field. Update many operand fields to deal with signed vs unsigned issues. Fix one or two typos in the "mov" instruction opcode, mask and/or operand fields. Checkpointing today's work. Matsushita.
1996-10-04 * mn10300-opc.c (mn10300_opcodes): Add opcode & masks forJeff Law1-248/+272
all opcodes. Very rough cut at operands for all opcodes. Matsushita.
1996-10-04 * mn10300-opc.c (mn10300_opcodes): Start fleshing out theJeff Law1-1/+250
opcode table. Checkpointint 10300 work.
1996-10-03Grrr. The mn10200 and mn10300 are _not_ similar enough to easily supportJeff Law1-0/+51
with a single generic configuration. So break them up into two different configurations. See the individual ChangeLogs for additional detail.