aboutsummaryrefslogtreecommitdiff
path: root/opcodes/mips-opc.c
AgeCommit message (Expand)AuthorFilesLines
1998-06-01 * mips-opc.c (rsqrt.s): Update based on r5900 ISA manual version 2.1Jeff Law1-9/+13
1998-05-18* Followup for SCEI PR 15853: 2-operand R5900 "mult1" instruction.Frank Ch. Eigler1-0/+1
1998-05-18* Fix sanitizationFrank Ch. Eigler1-0/+3
1998-05-07* Converted conditional-trap MIPS opcodes to extra-operand variety also.Frank Ch. Eigler1-6/+12
1998-05-07* First batch of fixes for sky PR 15853 (20-bit break/sdbbp)Frank Ch. Eigler1-3/+5
1998-04-21* Bit mask pattern fix for R5900 madd.s instruction; PR 15371.Frank Ch. Eigler1-3/+9
1998-03-10 * mips-opc.c ("clz","dclz"): Added the 4320 versions.Gavin Romig-Koch1-0/+6
1998-03-09 * mips-opc.c ("macc*","mul*"): Added the 4320 versionsGavin Romig-Koch1-13/+52
1998-03-03 * mips-dis.c (_print_insn_mips) : Handle bfd_mach_mips4320.Gavin Romig-Koch1-0/+7
1998-02-27 * mips-opc.c (r5900/madd.s): Takes three operands, not four. FixJeff Law1-3/+3
1998-02-20Fix it right this time.Jeff Law1-1/+1
1998-02-20 * mips-opc.c (mula.s): Renamed from multa.s.Jeff Law1-3/+7
1998-01-13 * mips-opc.c (c.lt.s): Add r5900 variant.Jeff Law1-0/+6
1997-12-22 * mips-opc.c: Add FP_D to s.d instruction flags.Ian Lance Taylor1-1/+24
1997-12-15 * mips-opc.c (mtpc, mfpc, mtps, mfps): Add r5900 variants.Jeff Law1-191/+209
1997-11-12mips-opc.c (sync,cache): These are 3900 insns.Gavin Romig-Koch1-2/+2
1997-11-03make vr5400 disassembly work; fix bugs in some vr5400 insnsKen Raeburn1-10/+11
1997-11-02Correct tx49 sanitation.Gavin Romig-Koch1-1/+10
1997-10-29 * mips-opc.c (deret,dmult,dmultu,madd,maddu,pref,sdbbp):Gavin Romig-Koch1-14/+24
1997-10-28* mips-opc.c (ffc, ffs): Fix mask.Ken Raeburn1-2/+2
1997-10-28Duh. Check in the vr5400 stuff from the directory that doesn't haveKen Raeburn1-0/+130
1997-10-28added vr5400 stuff, fixed "not" maskKen Raeburn1-2/+2
1997-10-17opcodes/mips-opc.c (bnezl,beqzl): Mark these as also tx39.Gavin Romig-Koch1-2/+2
1997-10-16opcodes/mips-opc.c: Note that 'jalx' is (probably incorrectly) marked I1.Gavin Romig-Koch1-1/+3
1997-10-08opcodes/mips-opc.c: Three op mult is not an ISA insn.Gavin Romig-Koch1-2/+7
1997-10-08opcodes/mips-opc.c: Fix formatting.Gavin Romig-Koch1-8/+11
1997-07-28Fix MTSA opcode encoding.Andrew Cagney1-1/+1
1997-07-11 * mips-opc.c (mips_builtin_opcodes): If an insn uses singleJeff Law1-393/+311
1997-06-30 * mips-opc.c (mips_builtin_opcodes): Add "pinteh", "pexeh" andJeff Law1-450/+479
1997-03-27 * mips-opc.c: Add cast when setting mips_opcodes.Ian Lance Taylor1-7/+13
1997-02-23 * mips-opc.c: Add macros for cop0, cop1 cop2 and cop3.Dawn Perchik1-40/+117
1997-02-11Add r5900Gavin Romig-Koch1-21/+214
1996-11-26 Add support for mips16 (16 bit MIPS implementation):Ian Lance Taylor1-13/+107
1995-02-16 * mips-opc.c: Add r4650 mul instruction.Ian Lance Taylor1-0/+1
1995-02-15 * mips-opc.c: Add uld and usd macros for unaligned double load andIan Lance Taylor1-0/+7
1994-12-20 * mips-opc.c: Add dli as a synonym for li.Ian Lance Taylor1-6/+10
1994-09-14 * mips-opc.c (mips_opcodes): Set WR_t for sc and scd.Ian Lance Taylor1-2/+2
1994-09-06 * mips-opc.c: Set INSN_STORE_MEMORY flag for all instructionsIan Lance Taylor1-34/+49
1993-10-05 * mips-opc.c: Correct lwu opcode value (book had it wrong).Ian Lance Taylor1-33/+34
1993-09-02 * mips-opc.c: Change div machine instruction to be z,s,t ratherIan Lance Taylor1-7/+9
1993-09-02 * mips-opc.c: Move div machine instruction after macro forms.Ian Lance Taylor1-8/+17
1993-08-27 * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): SetIan Lance Taylor1-4/+4
1993-08-20 * mips-opc.c: Added r6000 and r4000 instructions and macros.Ian Lance Taylor1-26/+212
1993-08-18 * mips-opc.c: li.d uses "T,L", not "S,F". Added li.s.Ian Lance Taylor1-0/+380