| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 1998-03-10 | * mips-opc.c ("clz","dclz"): Added the 4320 versions. | Gavin Romig-Koch | 1 | -0/+6 |
| 1998-03-09 | * mips-opc.c ("macc*","mul*"): Added the 4320 versions | Gavin Romig-Koch | 1 | -13/+52 |
| 1998-03-03 | * mips-dis.c (_print_insn_mips) : Handle bfd_mach_mips4320. | Gavin Romig-Koch | 1 | -0/+7 |
| 1998-02-27 | * mips-opc.c (r5900/madd.s): Takes three operands, not four. Fix | Jeff Law | 1 | -3/+3 |
| 1998-02-20 | Fix it right this time. | Jeff Law | 1 | -1/+1 |
| 1998-02-20 | * mips-opc.c (mula.s): Renamed from multa.s. | Jeff Law | 1 | -3/+7 |
| 1998-01-13 | * mips-opc.c (c.lt.s): Add r5900 variant. | Jeff Law | 1 | -0/+6 |
| 1997-12-22 | * mips-opc.c: Add FP_D to s.d instruction flags. | Ian Lance Taylor | 1 | -1/+24 |
| 1997-12-15 | * mips-opc.c (mtpc, mfpc, mtps, mfps): Add r5900 variants. | Jeff Law | 1 | -191/+209 |
| 1997-11-12 | mips-opc.c (sync,cache): These are 3900 insns. | Gavin Romig-Koch | 1 | -2/+2 |
| 1997-11-03 | make vr5400 disassembly work; fix bugs in some vr5400 insns | Ken Raeburn | 1 | -10/+11 |
| 1997-11-02 | Correct tx49 sanitation. | Gavin Romig-Koch | 1 | -1/+10 |
| 1997-10-29 | * mips-opc.c (deret,dmult,dmultu,madd,maddu,pref,sdbbp): | Gavin Romig-Koch | 1 | -14/+24 |
| 1997-10-28 | * mips-opc.c (ffc, ffs): Fix mask. | Ken Raeburn | 1 | -2/+2 |
| 1997-10-28 | Duh. Check in the vr5400 stuff from the directory that doesn't have | Ken Raeburn | 1 | -0/+130 |
| 1997-10-28 | added vr5400 stuff, fixed "not" mask | Ken Raeburn | 1 | -2/+2 |
| 1997-10-17 | opcodes/mips-opc.c (bnezl,beqzl): Mark these as also tx39. | Gavin Romig-Koch | 1 | -2/+2 |
| 1997-10-16 | opcodes/mips-opc.c: Note that 'jalx' is (probably incorrectly) marked I1. | Gavin Romig-Koch | 1 | -1/+3 |
| 1997-10-08 | opcodes/mips-opc.c: Three op mult is not an ISA insn. | Gavin Romig-Koch | 1 | -2/+7 |
| 1997-10-08 | opcodes/mips-opc.c: Fix formatting. | Gavin Romig-Koch | 1 | -8/+11 |
| 1997-07-28 | Fix MTSA opcode encoding. | Andrew Cagney | 1 | -1/+1 |
| 1997-07-11 | * mips-opc.c (mips_builtin_opcodes): If an insn uses single | Jeff Law | 1 | -393/+311 |
| 1997-06-30 | * mips-opc.c (mips_builtin_opcodes): Add "pinteh", "pexeh" and | Jeff Law | 1 | -450/+479 |
| 1997-03-27 | * mips-opc.c: Add cast when setting mips_opcodes. | Ian Lance Taylor | 1 | -7/+13 |
| 1997-02-23 | * mips-opc.c: Add macros for cop0, cop1 cop2 and cop3. | Dawn Perchik | 1 | -40/+117 |
| 1997-02-11 | Add r5900 | Gavin Romig-Koch | 1 | -21/+214 |
| 1996-11-26 | Add support for mips16 (16 bit MIPS implementation): | Ian Lance Taylor | 1 | -13/+107 |
| 1995-02-16 | * mips-opc.c: Add r4650 mul instruction. | Ian Lance Taylor | 1 | -0/+1 |
| 1995-02-15 | * mips-opc.c: Add uld and usd macros for unaligned double load and | Ian Lance Taylor | 1 | -0/+7 |
| 1994-12-20 | * mips-opc.c: Add dli as a synonym for li. | Ian Lance Taylor | 1 | -6/+10 |
| 1994-09-14 | * mips-opc.c (mips_opcodes): Set WR_t for sc and scd. | Ian Lance Taylor | 1 | -2/+2 |
| 1994-09-06 | * mips-opc.c: Set INSN_STORE_MEMORY flag for all instructions | Ian Lance Taylor | 1 | -34/+49 |
| 1993-10-05 | * mips-opc.c: Correct lwu opcode value (book had it wrong). | Ian Lance Taylor | 1 | -33/+34 |
| 1993-09-02 | * mips-opc.c: Change div machine instruction to be z,s,t rather | Ian Lance Taylor | 1 | -7/+9 |
| 1993-09-02 | * mips-opc.c: Move div machine instruction after macro forms. | Ian Lance Taylor | 1 | -8/+17 |
| 1993-08-27 | * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): Set | Ian Lance Taylor | 1 | -4/+4 |
| 1993-08-20 | * mips-opc.c: Added r6000 and r4000 instructions and macros. | Ian Lance Taylor | 1 | -26/+212 |
| 1993-08-18 | * mips-opc.c: li.d uses "T,L", not "S,F". Added li.s. | Ian Lance Taylor | 1 | -0/+380 |
