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2018-08-29[MIPS] Add Loongson 2K1000 proccessor support.Chenghua Xu1-0/+5
2018-08-29[MIPS] Add Loongson 3A2000/3A3000 proccessor support.Chenghua Xu1-0/+5
2018-08-29[MIPS] Add Loongson 3A1000 proccessor support.Chenghua Xu1-1/+7
2018-08-29[MIPS/GAS] Add Loongson EXT2 Instructions support.Chenghua Xu1-0/+11
2018-08-29[MIPS/GAS] Split Loongson EXT Instructions from loongson3a.Chenghua Xu1-1/+11
2018-08-29[MIPS/GAS] Split Loongson CAM Instructions from loongson3aChenghua Xu1-2/+13
2018-07-20MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3aChenghua Xu1-2/+12
2018-07-02GDB PR tdep/8282: MIPS: Wire in `set disassembler-options'Maciej W. Rozycki1-52/+158
2018-06-21MIPS/opcodes: Fix a typo in `-M ginv' option descriptionMaciej W. Rozycki1-1/+1
2018-06-14MIPS: Add Global INValidate ASE supportFaraz Shahbazker1-2/+12
2018-06-13MIPS: Add CRC ASE supportScott Egerton1-2/+3
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-06-30MIPS: Fix XPA base and Virtualization ASE instruction handlingMaciej W. Rozycki1-16/+32
2017-06-30MIPS/opcodes: Correctly combine ASE flags for ASE_MIPS16E2_MT calculationMaciej W. Rozycki1-3/+13
2017-06-28MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor supportMaciej W. Rozycki1-71/+109
2017-06-14Don't use print_insn_XXX in GDBYao Qi1-1/+1
2017-05-15MIPS16e2: Add MIPS16e2 ASE supportMaciej W. Rozycki1-16/+72
2017-05-15MIPS/opcodes: Remove an incorrect MT ASE reference in MFC0/MTC0 decodingMaciej W. Rozycki1-1/+1
2017-05-02MIPS16/opcodes: Keep the LSB of PC-relative offsets in disassemblyMaciej W. Rozycki1-3/+4
2017-04-25MIPS16/opcodes: Add `-M no-aliases' disassembler option help textMaciej W. Rozycki1-0/+3
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-23MIPS16: Simplify extended operand handlingMaciej W. Rozycki1-19/+17
2016-12-23MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki1-0/+1
2016-12-23opcodes: Use autoconf to check for `bfd_mips_elf_get_abiflags' in BFDMaciej W. Rozycki1-5/+6
2016-12-20MIPS16/opcodes: Respect ISA and ASE in disassemblyMaciej W. Rozycki1-1/+4
2016-12-20MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki1-78/+74
2016-12-19MIPS/opcodes: Only examine ELF file structures if SYMTAB_AVAILABLEMaciej W. Rozycki1-1/+1
2016-12-19MIPS/opcodes: Only call `bfd_mips_elf_get_abiflags' if BFD64Maciej W. Rozycki1-2/+9
2016-12-14MIPS/opcodes: Also set disassembler's ASE flags from ELF structuresMaciej W. Rozycki1-2/+42
2016-12-14MIPS/opcodes: Reorder ELF file header flag handling in disassemblerMaciej W. Rozycki1-13/+13
2016-12-09MIPS16/opcodes: Reformat raw EXTEND and undecoded outputMaciej W. Rozycki1-4/+4
2016-12-08MIPS16/opcodes: Fix off-by-one indentation in `print_mips16_insn_arg'Maciej W. Rozycki1-30/+30
2016-12-08MIPS16/opcodes: Fix PC-relative operation delay-slot adjustmentMaciej W. Rozycki1-6/+10
2016-12-07MIPS/opcodes: Correct an `interaction' comment typoMaciej W. Rozycki1-1/+1
2016-12-07MIPS/opcodes: Reformat `-M' disassembler option's help textMaciej W. Rozycki1-5/+6
2016-05-18MIPS/opcodes: Correct mixed MIPS16 and microMIPS disassemblyMaciej W. Rozycki1-17/+21
2016-05-11Add MIPS32 DSPr3 support.Matthew Fortune1-2/+2
2016-04-11MIPS/opcodes: Fix undecoded MIPS16 extended instruction bit disassemblyMaciej W. Rozycki1-2/+4
2016-01-18MIPS: Remove remnants of 48-bit microMIPS instruction supportMaciej W. Rozycki1-35/+1
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-09-23Fix compile time warnings generated when compiling with clang.Nick Clifton1-12/+0
2015-08-12Remove trailing spaces in opcodesH.J. Lu1-3/+3
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-10-31MIPS: Add Octeon 3 supportNaveen H.S1-0/+5
2014-09-15Add support for MIPS R6.Andrew Bennett1-15/+201
2014-05-07Add MIPS r3 and r5 support.Andrew Bennett1-2/+38
2014-04-23Add support for the MIPS eXtended Physical Address (XPA) ASE.Andrew Bennett1-2/+12
2014-03-05Update copyright yearsAlan Modra1-3/+1
2014-03-04bfd/Richard Sandiford1-1/+1
2013-12-16Add support to show the symbolic names of the MIPS CP1 registers.Andrew Bennett1-39/+101
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