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2005-09-06* mips-opc.c (MT32): New define.Chao-ying Fu1-1/+55
(mips_builtin_opcodes): Move "bc0f", "bc0fl", "bc0t", "bc0tl" to the bottom to avoid opcode collision with "mftr" and "mttr". Add MT instructions. * mips-dis.c (mips_arch_choices): Enable INSN_MT for mips32r2. (print_insn_args): Add supports for +t, +T, !, $, *, &, g operand formats.
2005-08-25* mips-opc.c (WR_a, RD_a, MOD_a, DSP_VOLA, D32): New define.Chao-ying Fu1-4/+65
(mips_builtin_opcodes): Add DSP instructions. * mips-dis.c (mips_arch_choices): Enable INSN_DSP for mips32, mips32r2, mips64, mips64r2. (print_insn_args): Add supports for 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats.
2005-07-07Kaveh Ghazi's printf format attribute checking patch.Jim Wilson1-23/+24
bfd: * elf32-xtensa.c (vsprint_msg): Add format attribute. Fix format bugs. * vms.h (_bfd_vms_debug): Add format attribute. (_bfd_vms_debug, _bfd_hexdump): Fix typos. binutils: * bucomm.h (report): Add format attribute. * dlltool.c (inform): Likewise. * dllwrap.c (display, inform, warn): Likewise. * objdump.c (objdump_sprintf): Likewise. * readelf.c (error, warn): Likewise. Fix format bugs. gas: * config/tc-tic30.c (debug): Add format attribute. Fix format bugs. include: * dis-asm.h (fprintf_ftype): Add format attribute. opcodes: * arc-dis.c, arm-dis.c, cris-dis.c, crx-dis.c, d10v-dis.c, d30v-dis.c, fr30-dis.c, h8300-dis.c, h8500-dis.c, i860-dis.c, ia64-dis.c, ip2k-dis.c, m10200-dis.c, m10300-dis.c, m88k-dis.c, mcore-dis.c, mips-dis.c, ms1-dis.c, or32-dis.c, ppc-dis.c, sh64-dis.c, sparc-dis.c, tic4x-dis.c, tic80-dis.c, v850-dis.c: Fix format bugs. * ia64-gen.c (fail, warn): Add format attribute. * or32-opc.c (debug): Likewise.
2005-07-01Update function declarations to ISO C90 formattingNick Clifton1-378/+351
2005-05-07Update the address and phone number of the FSFNick Clifton1-1/+1
2005-03-03update copyright datesAlan Modra1-1/+1
2005-01-21 2005-01-21 Fred Fish <fnf@specifixinc.com>Fred Fish1-3/+3
* mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS. Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC. * mips-dis.c: Ditto.
2005-01-19 2005-01-19 Fred Fish <fnf@specifixinc.com>Fred Fish1-3/+19
* mips-dis.c (no_aliases): New disassembly option flag. (set_default_mips_dis_options): Init no_aliases to zero. (parse_mips_dis_option): Handle no-aliases option. (print_insn_mips): Ignore table entries that are aliases if no_aliases is set. (print_insn_mips16): Ditto. * mips-opc.c (mips_builtin_opcodes): Add initializer column for new pinfo2 member and add INSN_ALIAS initializers as needed. Also move WR_MACC and RD_MACC initializers from pinfo to pinfo2. * mips16-opc.c (mips16_opcodes): Ditto.
2003-09-30[ bfd/ChangeLog ]Chris Demetriou1-0/+22
2003-09-30 Chris Demetriou <cgd@broadcom.com> * archures.c (bfd_mach_mipsisa64r2): New define. * bfd-in2.h: Regenerate. * aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2. * cpu-mips.c (I_mipsisa64r2): New enum value. (arch_info_struct): Add entry for I_mipsisa64r2. * elfxx-mips.c (_bfd_elf_mips_mach) (_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2. (mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case. (mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2. [ binutils/ChangeLog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2. [ gas/Changelog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs. * configure: Regenerate. * config/tc-mips.c (imm2_expr): New variable. (md_assemble, mips16_ip): Initialize imm2_expr. (ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2. (macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands. (macro): Handle M_DEXT and M_DINS. (validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands. (mips_ip): Likewise. (OPTION_MIPS64R2): New define. (md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2). OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2. (md_parse_option): Handle OPTION_MIPS64R2. (s_mipsset): Handle setting "mips64r2" ISA. (mips_cpu_info_table): Add mips64r2. (md_show_usage): Document -mips64r2 option. * doc/as.texinfo: Docuemnt -mips64r2 option. * doc/c-mips.texi: Likewise. [ gas/testsuite/ChangeLog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * gas/mips/cp0-names-mips64r2.d: New file. * gas/mips/cp0sel-names-mips64r2.d: New file. * gas/mips/elf_arch_mips64r2.d: New file. * gas/mips/hwr-names-mips64r2.d: New file. * gas/mips/mips32r2-ill-fp64.l: New file. * gas/mips/mips32r2-ill-fp64.s: New file. * gas/mips/mips64r2-ill.l: New file. * gas/mips/mips64r2-ill.s: New file. * gas/mips/mips64r2.d: New file. * gas/mips/mips64r2.s: New file. * gas/mips/mips.exp: Define "mips64r2" arch, and run new tests. [ include/elf/ChangeLog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * mips.h (E_MIPS_ARCH_64R2): New define. [ include/opcode/ChangeLog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * mips.h: Document +E, +F, +G, +H, and +I operand types. Update documentation of I, +B and +C operand types. (INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines. (M_DEXT, M_DINS): New enum values. [ ld/ChangeLog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * ldmain.c (get_emulation): Ignore "-mips64r2". [ ld/testsuite/ChangeLog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * ld-mips-elf/mips-elf-flags.exp: Add tests for combinations with MIPS64r2. [ opcodes/ChangeLog ] 2003-09-30 Chris Demetriou <cgd@broadcom.com> * mips-dis.c (mips_arch_choices): Add entry for "mips64r2" (print_insn_args): Add handing for +E, +F, +G, and +H. * mips-opc.c (I65): New define for MIPS64r2. (mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins", "dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh", and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to be supported on MIPS64r2.
2003-07-15include/opcode/Richard Sandiford1-0/+4
* mips.h (CPU_RM7000): New macro. (OPCODE_IS_MEMBER): Match CPU_RM7000 against 4650 insns. bfd/ * archures.c (bfd_mach_mips7000): New. * bfd-in2.h: Regenerated. * cpu-mips.c (arch_info_struct): Add an entry for mips:7000. * elfxx-mips.c (mips_set_isa_flags): Handle bfd_mach_mips7000. (mips_mach_extensions): Add an entry for it. opcodes/ * mips-dis.c (mips_arch_choices): Add rm7000 and rm9000 entries. gas/ * config/tc-mips.c (hilo_interlocks): True for CPU_RM7000. (mips_cpu_info_table): Add rm7000 and rm9000 entries. gas/testsuite/ * gas/mips/rm7000.[sd]: New test. * gas/mips/mips.exp: Run it.
2003-07-092003-07-09 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-2/+2
* mips-dis.c (set_default_mips_dis_options): Get BFD from the disassembler_info's section, rather than from the disassembler_info's symbols pointer.
2003-04-08* mips-dis.c (mips_gpr_names_newabi): Reverted previous patch.Alexandre Oliva1-1/+1
2003-04-08* mips-dis.c (mips_gpr_names_newabi): $12-$15 are named $t4-$t7.Alexandre Oliva1-1/+1
2003-02-232003-02-23 Elias Athanasopoulos <elathan@phys.uoa.gr>Chris Demetriou1-3/+3
* mips-dis.c (print_mips_disassembler_options): Make 'i' unsigned, use ARRAY_SIZE in loops.
2003-01-022003-01-02 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-9/+9
* mips-dis.c (print_insn_args): Use position extracted by "+A" to calculate size for "+B". Redo code for "+C" so it shares the same style as "+A" and "+B" now do.
2003-01-022003-01-02 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-290/+284
* mips-dis.c: Update copyright years. (print_insn_arg): Rename to... (print_insn_args): This, returning void. Process the whole string of args rather than a single one. Reindent. (print_insn_mips): Update to match the above.
2002-12-31[ gas/ChangeLog ]Chris Demetriou1-43/+217
2002-12-31 Chris Demetriou <cgd@broadcom.com> * config/tc-mips.c (validate_mips_insn, mips_ip): Recognize the "+D" operand, which will be used only by the disassembler. [ gas/testsuite/ChangeLog ] 2002-12-31 Chris Demetriou <cgd@broadcom.com> * gas/mips/cp0sel-names-mips32.d: New test. * gas/mips/cp0sel-names-mips32r2.d: New test. * gas/mips/cp0sel-names-mips64.d: New test. * gas/mips/cp0sel-names-numeric.d: New test. * gas/mips/cp0sel-names-sb1.d: New test. * gas/mips/cp0sel-names.s: New test source file. * gas/mips/mips.exp: Run new tests. [ include/opcode/ChangeLog ] 2002-12-31 Chris Demetriou <cgd@broadcom.com> * mips.h: Note that the "+D" operand type name is now used. [ opcodes/ChangeLog ] 2002-12-31 Chris Demetriou <cgd@broadcom.com> * mips-dis.c (mips_cp0sel_name): New structure. (mips_cp0sel_names_mips3264, mips_cp0sel_names_mips3264r2) (mips_cp0sel_names_sb1): New arrays. (mips_arch_choice): New structure members "cp0sel_names" and "cp0sel_names_len". (mips_arch_choices): Add references to new cp0sel_names arrays as appropriate, and make all existing entries reference appropriate mips_XXX_names_numeric arrays rather than simply using NULL. (mips_cp0sel_names, mips_cp0sel_names_len): New variables. (lookup_mips_cp0sel_name): New function. (set_default_mips_dis_options): Set mips_cp0sel_names and mips_cp0sel_names_len as appropriate. Remove now-unnecessary checks for NULL register name arrays. (parse_mips_dis_option): Likewise. (print_insn_arg): Handle "+D" operand type. * mips-opc.c (mips_builtin_opcodes): Add new "+D" variants of mfc0, mtc0, dmfc0, and dmtc0 to print CP0+sel register names symbolically.
2002-12-31[ bfd/ChangeLog ]Chris Demetriou1-31/+132
2002-12-30 Chris Demetriou <cgd@broadcom.com> * aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case. * archures.c (bfd_mach_mipsisa32r2): New define. * bfd-in2.h: Regenerate. * cpu-mips.c (I_mipsisa32r2): New enum value. (arch_info_struct): Add entry for I_mipsisa32r2. * elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach) (_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2. (_bfd_mips_elf_final_write_processing): Add bfd_mach_mipsisa32r2 case. (_bfd_mips_elf_merge_private_bfd_data): Handle merging of binaries marked as using MIPS32 Release 2. [ binutils/ChangeLog ] 2002-12-30 Chris Demetriou <cgd@broadcom.com> * doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register) changes in MIPS -M options. [ gas/ChangeLog ] 2002-12-30 Chris Demetriou <cgd@broadcom.com> * configure.in: Recognize mipsisa32r2, mipsisa32r2el, and CPU variants. * configure: Regenerate. * config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines. (macro_build): Handle "K" operand. (macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where CPU_HAS_DROR and CPU_HAS_ROR are currently used. (mips_ip): New variable "lastpos", and implement "+A", "+B", and "+C" operands for MIPS32 Release 2 ins/ext instructions. Implement "K" operand for MIPS32 Release 2 rdhwr instruction. (validate_mips_insn): Implement "+" as a way to extend the allowed operands, and implement "K", "+A", "+B", and "+C" operands. (OPTION_MIPS32R2): New define. (md_longopts): Add entry for OPTION_MIPS32R2. (OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2. (md_parse_option): Handle OPTION_MIPS32R2. (s_mipsset): Reimplement handling of ".set mipsN" options and add support for ".set mips32r2". (mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2). (md_show_usage): Document "-mips32r2" option. * doc/as.texinfo: Document "-mips32r2" option. * doc/c-mips.texi: Likewise. [ gas/testsuite/ChangeLog ] 2002-12-30 Chris Demetriou <cgd@broadcom.com> * gas/mips/cp0-names-mips32r2.d: New test. * gas/mips/hwr-names-mips32r2.d: New test. * gas/mips/hwr-names-numeric.d: New test. * gas/mips/hwr-names.s: New test source file. * gas/mips/mips32r2.d: New test. * gas/mips/mips32r2.s: New test source file. * gas/mips/mips32r2-ill.l: New test. * gas/mips/mips32r2-ill.s: New test source file. * gas/mips/mips.exp: Add mips32r2 architecture data array entry. Run new tests mentioned above. [ include/elf/ChangeLog ] 2002-12-30 Chris Demetriou <cgd@broadcom.com> * mips.h (E_MIPS_ARCH_32R2): New define. [ include/opcode/ChangeLog ] 2002-12-30 Chris Demetriou <cgd@broadcom.com> * mips.h: Document "+" as the start of two-character operand type names, and add new "K", "+A", "+B", and "+C" operand types. (OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB) (OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New defines. [ opcodes/ChangeLog ] 2002-12-30 Chris Demetriou <cgd@broadcom.com> * mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric) (mips_hwr_names_mips3264r2): New arrays. (mips_arch_choice): New "hwr_names" member. (mips_arch_choices): Adjust for structure change, and add a new entry for "mips32r2" ISA. (mips_hwr_names): New variable. (set_default_mips_dis_options): Set mips_hwr_names. (parse_mips_dis_option): New "hwr-names" option which sets mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names. (print_insn_arg): Change return type to "int" and use that to indicate number of characters consumed. Add support for "+" operand extension character, "+A", "+B", "+C", and "K" operands. (print_insn_mips): Adjust for changes to print_insn_arg. (print_mips_disassembler_options): Adjust for "hwr-names" addition and "reg-names" change. * mips-opc (I33): New define (shorthand for INSN_ISA32R2). (mips_builtin_opcodes): Note that "nop" and "ssnop" are special forms of "sll". Add new MIPS32 Release 2 instructions: ehb, di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2, rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh. Note that hardware rotate instructions (ror, rorv) can be used on MIPS32 Release 2, and add the official mnemonics for them (rotr, rotrv) and the similar "rotl" mnemonic for left-rotate.
2002-12-27[ binutils/ChangeLog ]Chris Demetriou1-199/+500
2002-12-27 Chris Demetriou <cgd@broadcom.com> * doc/binutils.texi (objdump): Document MIPS -M options. [ gas/testsuite/ChangeLog ] 2002-12-27 Chris Demetriou <cgd@broadcom.com> * gas/mips/cp0-names-mips32.d: New file. * gas/mips/cp0-names-mips64.d: New file. * gas/mips/cp0-names-numeric.d: New file. * gas/mips/cp0-names-sb1.d: New file. * gas/mips/cp0-names.s: New file. * gas/mips/fpr-names-32.d: New file. * gas/mips/fpr-names-64.d: New file. * gas/mips/fpr-names-n32.d: New file. * gas/mips/fpr-names-numeric.d: New file. * gas/mips/fpr-names.s: New file. * gas/mips/gpr-names-32.d: New file. * gas/mips/gpr-names-64.d: New file. * gas/mips/gpr-names-n32.d: New file. * gas/mips/gpr-names-numeric.d: New file. * gas/mips/gpr-names.s: New file. * gas/mips/mips.exp: Run new tests. [ include/ChangeLog ] 2002-12-27 Chris Demetriou <cgd@broadcom.com> * dis-asm.h (print_mips_disassembler_options): Prototype. [ include/opcode/ChangeLog ] 2002-12-19 Chris Demetriou <cgd@broadcom.com> * mips.h (OP_OP_COP0, OP_OP_COP1, OP_OP_COP2, OP_OP_COP3) (OP_OP_LWC1, OP_OP_LWC2, OP_OP_LWC3, OP_OP_LDC1, OP_OP_LDC2) (OP_OP_LDC3, OP_OP_SWC1, OP_OP_SWC2, OP_OP_SWC3, OP_OP_SDC1) (OP_OP_SDC2, OP_OP_SDC3): Define. [ opcodes/ChangeLog ] 2002-12-27 Chris Demetriou <cgd@broadcom.com> * disassemble.c (disassembler_usage): Add invocation of print_mips_disassembler_options. * mips-dis.c (print_mips_disassembler_options) (set_default_mips_dis_options, parse_mips_dis_option) (parse_mips_dis_options, choose_abi_by_name, choose_arch_by_name) (choose_arch_by_number): New functions. (mips_abi_choice, mips_arch_choice): New structures. (mips32_reg_names, mips64_reg_names, reg_names): Remove. (mips_gpr_names_numeric, mips_gpr_names_oldabi) (mips_gpr_names_newabi, mips_fpr_names_numeric) (mips_fpr_names_32, mips_fpr_names_n32, mips_fpr_names_64) (mips_cp0_names_numeric, mips_cp0_names_mips3264) (mips_cp0_names_sb1, mips_abi_choices, mips_arch_choices) (mips_processor, mips_isa, mips_gpr_names, mips_fpr_names) (mips_cp0_names): New variables. (print_insn_args): Use new variables to print GPR, FPR, and CP0 register names. (mips_isa_type): Remove. (print_insn_mips): Remove ISA and CPU setup since it is now done... (_print_insn_mips): Here. Remove register setup code, and call set_default_mips_dis_options and parse_mips_dis_options instead. (print_mips16_insn_arg): Use mips_gpr_names instead of mips32_names.
2002-11-30s/boolean/bfd_boolean/ s/true/TRUE/ s/false/FALSE/. SimplifyAlan Modra1-9/+9
comparisons of bfd_boolean vars with TRUE/FALSE. Formatting.
2002-09-30[include/opcode/]Richard Sandiford1-0/+24
* mips.h: Update comment for new opcodes. (OP_MASK_VECBYTE, OP_SH_VECBYTE): New. (OP_MASK_VECALIGN, OP_SH_VECALIGN): New. (INSN_4111, INSN_4120, INSN_5400, INSN_5500): New. (CPU_VR4120, CPU_VR5400, CPU_VR5500): New. (OPCODE_IS_MEMBER): Handle the new CPU_* values and INSN_* flags. Don't match CPU_R4111 with INSN_4100. [opcodes/] * mips-dis.c (print_insn_arg): Handle '[', ']', 'e' and '%'. (mips_isa_type): Handle bfd_mach_mips4120, bfd_mach_mips5400 and bfd_mach_mips5500. * mips-opc.c (V1): Include INSN_4111 and INSN_4120. (N411, N412, N5, N54, N55): New convenience defines. (mips_builtin_opcodes): Add vr4120, vr5400 and vr5500 opcodes. Change dmadd16 and madd16 from V1 to N411.
2002-09-26 /gas/ChangeLogThiemo Seufer1-1/+3
* config/tc-mips.c (CPU_HAS_MIPS16): Add mips-lsi-elf as MIPS16 capable configuration. (macro_build): Check for MIPS16 capability, not for actual MIPS16 code generation. (mips_ip): Likewise. /gas/testsuite/ChangeLog * gas/mips/mips-jalx.d: New file, check jalx assembly. * gas/mips/mips-jalx.s: Likewise. * gas/mips/mips-no-jalx.l: Likewise. * gas/mips/mips-no-jalx.s: Likewise. * gas/mips/mips16-jalx.d: Likewise. * gas/mips/mips16-jalx.s: Likewise. * gas/mips/mips.exp: Add new tests. /opcodes/ChangeLog: * mips-dis.c (print_insn_mips): Always allow disassembly of 32-bit jalx opcode.
2002-08-30 * v850-dis.c (disassemble): Remove bfd_mach_v850ea case.Alan Modra1-1/+1
* mips-dis.c (_print_insn_mips): Don't use hard-coded mach constants.
2002-07-09 * config/tc-mips.c (macro_build): Handle MIPS16 insns.Thiemo Seufer1-3/+3
(mips_ip): Likewise. * mips.h (INSN_MIPS16): New define. * mips-dis.c (mips_isa_type): Add MIPS16 insn handling. * mips-opc.c (I16): New define. (mips_builtin_opcodes): Make jalx an I16 insn.
2002-05-31[ gas/ChangeLog ]Chris Demetriou1-3/+50
2002-05-30 Chris G. Demetriou <cgd@broadcom.com> Ed Satterthwaite <ehs@broadcom.com> * config/tc-mips.c (mips_set_options): New "ase_mdmx" member. (mips_opts): Initialize "ase_mdmx" member. (file_ase_mdmx): New variable. (CPU_HAS_MDMX): New macro. (md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx based on command line options and configuration defaults. (macro_build): Note in comment that use of MDMX in macros is not currently allowed. (validate_mips_insn): Add support for the "O", "Q", "X", "Y", and "Z" MDMX operand types. (mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set, and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand types. (OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option): Add support for "-mdmx" and "-no-mdmx" options. (OPTION_ELF_BASE): Move to accomodate new options. (s_mipsset): Support ".set mdmx" and ".set nomdmx". (mips_elf_final_processing): Set MDMX ASE ELF header flag if file_ase_mdmx was set. * doc/as.texinfo: Document -mdmx and -no-mdmx options. * doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set nomdmx" directives. [ gas/testsuite/ChangeLog ] 2002-05-30 Chris G. Demetriou <cgd@broadcom.com> * gas/mips/mips64-mdmx.s: New file. * gas/mips/mips64-mdmx.d: Likewise. * gas/mips/mips.exp: Run new "mips64-mdmx" test. [ include/opcode/ChangeLog ] 2002-05-30 Chris G. Demetriou <cgd@broadcom.com> * mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL) (MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH) (MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC) (INSN_MDMX): New constants, for MDMX support. (opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX. [ opcodes/ChangeLog ] 2002-05-30 Chris G. Demetriou <cgd@broadcom.com> Ed Satterthwaite <ehs@broadcom.com> * mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y', and 'Z' formats, for MDMX. (mips_isa_type): Add MDMX instructions to the ISA bit mask for bfd_mach_mipsisa64. * mips-opc.c: Add support for MDMX instructions. (MX): New definition. * mips-dis.c: Update copyright years to include 2002.
2002-05-14 * mips-dis.c (is_newabi): EABI is not a NewABI.Thiemo Seufer1-4/+2
2002-03-162002-03-15 Chris G. Demetriou <cgd@broadcom.com>Chris Demetriou1-1/+1
* mips-dis.c: Update copyright years.
2002-03-16[ gas/ChangeLog ]Chris Demetriou1-2/+8
2002-03-15 Chris G. Demetriou <cgd@broadcom.com> * config/tc-mips.c (mips_set_options): New "ase_mips3d" member. (mips_opts): Initialize "ase_mips3d" member. (file_ase_mips3d): New variable. (CPU_HAS_MIPS3D): New macro. (md_begin): Initialize mips_opts.ase_mips3d and file_ase_mips3d based on command line options and configuration defaults. (macro_build, mips_ip): Accept MIPS-3D instructions if mips_opts.ase_mips3d is set. (OPTION_MIPS3D, OPTION_NO_MIPS3D, md_longopts, md_parse_option): Add support for "-mips3d" and "-no-mips3d" options. (OPTION_ELF_BASE): Move to accomodate new options. (s_mipsset): Support ".set mips3d" and ".set nomips3d". (mips_elf_final_processing): Add a comment indicating that a MIPS-3D ASE ELF header flag should be set, when one exists. * doc/as.texinfo: Document -mips3d and -no-mips3d options. * doc/c-mips.texi: Likewise, and document ".set mips3d" and ".set nomips3d" directives. [ gas/testsuite/ChangeLog ] 2002-03-15 Chris G. Demetriou <cgd@broadcom.com> * gas/mips/mips64-mips3d.s: New file. * gas/mips/mips64-mips3d.d: Likewise. * gas/mips/mips.exp: Run new "mips64-mips3d" test. [ include/opcode/ChangeLog ] 2002-03-15 Chris G. Demetriou <cgd@broadcom.com> * mips.h (INSN_MIPS3D): New definition used to mark MIPS-3D instructions. (OPCODE_IS_MEMBER): Adjust comments to indicate that ASE bit masks may be passed along with the ISA bitmask. [ opcodes/ChangeLog ] 2002-03-15 Chris G. Demetriou <cgd@broadcom.com> * mips-dis.c (mips_isa_type): Add MIPS3D instructions to the ISA bit masks for bfd_mach_mips_sb1 and bfd_mach_mipsisa64. Add comments for bfd_mach_mipsisa32 and bfd_mach_mipsisa64 that indicate that they should dissassemble all applicable MIPS-specified ASEs. * mips-opc.c: Add support for MIPS-3D instructions. (M3D): New definition. * mips-opc.c: Update copyright years.
2002-03-152002-03-15 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-4/+8
* mips-dis.c (is_newabi): Fix ABI decoding.
2002-03-152002-03-14 Chris G. Demetriou <cgd@broadcom.com>Chris Demetriou1-4/+4
* mips-dis.c (mips_isa_type): Fix formatting of bfd_mach_mipsisa32 and bfd_mach_mipsisa64 cases to match the rest.
2001-11-052001-11-04 Chris Demetriou <cgd@broadcom.com>Chris Demetriou1-1/+1
* mips-dis.c (print_insn_mips): Remove spaces at end of line.
2001-10-23[opcodes/ChangeLog]Chris Demetriou1-13/+38
2001-10-21 Chris Demetriou <cgd@broadcom.com> * mips-opc.c (mips_builtin_opcodes): Mark "bgezall" and "bltzall" as writing GPR 31 (since they do). * mips-dis.c (print_insn_arg): Calculate info->target where appropriate. (print_insn_mips): Fill in instruction info. (print_mips16_insn_arg): Remove unneded variable 'val'. Removed duplicated instruction target calculations, calculate once and print that result. Use same idiom for masking the jump segment bits as is used in print_insn_arg. [gas/testsuite/ChangeLog] 2001-10-21 Chris Demetriou <cgd@broadcom.com> * gas/mips/beq.s: Add zero words at end of instructions so that objdump will print "..." when disassembling. * gas/mips/beq.d: Update for disassembler changes which force branch delay-slot nops to be printed. * gas/mips/bge.d: Ditto. * gas/mips/bgeu.d: Ditto. * gas/mips/blt.d: Ditto. * gas/mips/bltu.d: Ditto. * gas/mips/jal-svr4pic.d: Ditto. * gas/mips/jal-xgot.d: Ditto.
2001-10-18[gas/testsuite/ChangeLog]Chris Demetriou1-1/+1
2001-10-17 Chris Demetriou <cgd@broadcom.com> * gas/mips/mips.exp (sb1-ext-ps): New test to test SB-1 core's paired-single extensions to the MIPS64 ISA. * gas/mips/sb1-ext-ps.d: New file. * gas/mips/sb1-ext-ps.s: New file. [include/opcode/ChangeLog] 2001-10-17 Chris Demetriou <cgd@broadcom.com> * mips.h (INSN_SB1): New cpu-specific instruction bit. (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1 if cpu is CPU_SB1. [opcodes/ChangeLog] 2001-10-17 Chris Demetriou <cgd@broadcom.com> * mips-dis.c (mips_isa_type): Make the ISA used to disassemble SB-1 binaries include instructions specific to the SB-1. * mips-opc.c (SB1): New definition. (mips_builtin_opcodes): Add SB-1 extension opcodes "div.ps", "recip.ps", "rsqrt.ps", and "sqrt.ps".
2001-08-312001-08-31 Eric Christopher <echristo@redhat.com>Eric Christopher1-12/+9
Jason Eckhardt <jle@redhat.com> * mips-dis.c: Add support for bfd_mach_mipsisa32 and bfd_mach_mipsisa64. Remove bfd_mach_mips32, bfd_mach_mips32_4k, bfd_mach_mips64.
2001-08-21 * i960-dis.c: Add parameters for prototypesAndreas Jaeger1-0/+4
(ctrl): Add unused attributes. (cobr): Likewise. (put_abs): Likewise. * mips-dis.c: Add missing prototypes. * a29k-dis.c: Likewise. * arc-dis.c: Likewise. * ia64-opc.c: Likewise. * s390-dis.c: Add missing prototypes. (init_disasm): Remove unused attribute since the parameter is used.
2001-08-13 * mcore-dis.c: Fix formatting.Kazu Hirata1-41/+38
* mips-dis.c: Likewise. * pj-dis.c: Likewise. * z8k-dis.c: Likewise.
2001-08-10 * mips-dis.c (print_insn_mips): Remove OPCODE_IS_MEMBER's gp32Richard Sandiford1-1/+1
argument. * mips-opc.c (G6): Undefine. (mips_builtin_opcodes): Remove gp32 entry for "move". Add macro as the first "move" alternative.
2001-08-07 * mips-dis.c (print_insn_arg): Don't use software integer registersThiemo Seufer1-19/+23
for coprocessor registers. (_print_insn_mips): Get distinction between old ABI and new ABI right.
2001-05-23Add MIPS r12k supportNick Clifton1-0/+4
2001-05-15Fix MIPS disassembler so that it produces reassemblable code.Nick Clifton1-163/+183
2001-03-24Remove extraneous whitespaceNick Clifton1-8/+8
2001-03-13Fix typos in ChangeLogs; fix dates in copyright noticesNick Clifton1-1/+2
2001-02-11Apply several patches from Maciej W. RozyckiNick Clifton1-3/+3
2000-12-02Add MIPS SB1 machineNick Clifton1-0/+4
2000-12-02Add MIPS V and MIPS 64 machine numbersNick Clifton1-0/+8
2000-12-01Add MIPS32 as a seperate MIPS architectureNick Clifton1-22/+26
2000-12-01Improve MIPS32 supportNick Clifton1-8/+30
2000-09-14Add support for the MIPS32Nick Clifton1-65/+77
2000-05-24 * mips-dis.c (REGISTER_NAMES): Rename to STD_REGISTER_NAMES.Diego Novillo1-2/+9
(STD_REGISTER_NAMES): New name for REGISTER_NAMES. (reg_names): Rename to std_reg_names. Change it to a char ** static variable. (std_reg_names): New name for reg_names. (set_mips_isa_type): Set reg_names to point to std_reg_names by default.
2000-05-11Don't mask top 32 bits of 64-bit address.Alan Modra1-2/+4
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