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2022-03-06MIPS/opcodes: Fix alias annotation for branch instructionsMaciej W. Rozycki1-2/+2
Correct issues with INSN2_ALIAS annotation for branch instructions: - regular MIPS BEQZ/L and BNEZ/L assembly instructions are idioms for BEQ/L and BNE/L respectively with the `rs' operand equal to $0, - microMIPS 32-bit BEQZ and BNEZ assembly instructions are idioms for BEQ and BNE respectively with the `rt' operand equal to $0, - regular MIPS BAL assembly instruction is an idiom for architecture levels of up to the MIPSr5 ISA and a machine instruction on its own from the MIPSr6 ISA up. Add missing annotation to BEQZ/L and BNEZ/L accordingly then and add a new entry for BAL for the MIPSr6 ISA, correcting a disassembly bug: $ mips-linux-gnu-objdump -m mips:isa64r6 -M no-aliases -d bal.o bal.o: file format elf32-tradlittlemips Disassembly of section .text: 00000000 <foo>: 0: 04110000 0x4110000 ... $ Add test cases accordingly. Parts for regular MIPS BEQZ/L and BNEZ/L instructions from Sagar Patel. 2022-03-06 Maciej W. Rozycki <macro@orcam.me.uk> binutils/ * testsuite/binutils-all/mips/mips1-branch-alias.d: New test. * testsuite/binutils-all/mips/mips1-branch-noalias.d: New test. * testsuite/binutils-all/mips/mips2-branch-alias.d: New test. * testsuite/binutils-all/mips/mips2-branch-noalias.d: New test. * testsuite/binutils-all/mips/mips32r6-branch-alias.d: New test. * testsuite/binutils-all/mips/mips32r6-branch-noalias.d: New test. * testsuite/binutils-all/mips/micromips-branch-alias.d: New test. * testsuite/binutils-all/mips/micromips-branch-noalias.d: New test. * testsuite/binutils-all/mips/mips-branch-alias.s: New test source. * testsuite/binutils-all/mips/micromips-branch-alias.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests. 2022-03-06 Sagar Patel <sagarmp@cs.unc.edu> Maciej W. Rozycki <macro@orcam.me.uk> opcodes/ * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions. * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and "bnez" instructions.
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out */po/*.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.
2021-05-29MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki1-4/+5
The CP0 control register set has never been defined, however encodings for the CFC0 and CTC0 instructions remained available for implementers up until the MIPS32 ISA declared them invalid and causing the Reserved Instruction exception[1]. Therefore we handle them for both assembly and disassembly, however in the latter case the names of CP0 registers from the regular set are incorrectly printed if named registers are requested. This is because we do not define separate operand classes for coprocessor regular and control registers respectively, which means the disassembler has no way to tell the two cases apart. Consequently nonsensical disassembly is produced like: cfc0 v0,c0_random Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0 instructions[2] although it failed to document them in the relevant opcode table until MIPSr6 only. Correct the issue then by defining a new register class, OP_REG_CONTROL, and corresponding operand codes, `g' and `y' for the two positions in the machine instruction a control register operand can take. Adjust the test cases affected accordingly. While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries with each other so that they come in the alphabetical order. References: [1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of rs Field", p. 242 [2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of Instructions", pp. 195, 216 include/ * opcode/mips.h: Document `g' and `y' operand codes. (mips_reg_operand_type): Add OP_REG_CONTROL enumeration constant. gas/ * tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case. (macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G' operand code. opcodes/ * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register handling code over to... <OP_REG_CONTROL>: ... this new case. * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases. (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2", "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries replacing the `G' operand code with `g'. Update "cftc1" and "cftc2" entries replacing the `E' operand code with `y'. * micromips-opc.c (decode_micromips_operand) <'g'>: New case. (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2" entries replacing the `G' operand code with `g'. binutils/ * testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0 operand disassembly. * testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
2021-05-29microMIPS/opcodes: Refer FPRs rather than FCRs with DMTC1Maciej W. Rozycki1-1/+1
The DMTC1 instruction operates on a floating-point general register as its second operand, however in the disassembly of the microMIPS encoding a floating-point control register is shown instead. This is due to an incorrect ordering of the two "dmtc1" entries in the opcode table, which gives precedence to one using the `G' aka coprocessor format over one using the `S' or floating-point register format. The coprocessor format, or OP_REG_COPRO, is used so that GAS supports referring to FPRs by their numbers in assembly, such as $0, $1, etc. however in the case of CP1/FPU it is also used by the disassembler to decode those numbers to the names of corresponding control registers. This in turn causes nonsensical disassembly such as: dmtc1 a1,c1_fir in a reference to $f0. It has been like this ever since microMIPS ISA support has been added. Correct the ordering of the two entries then by swapping them with each other, making disassembly output consistent with the regular MIPS DMTC1 instruction as well all the remaining CP1 move instructions. Adjust all the test cases affected accordingly. opcodes/ * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1" entries with each other. gas/ * testsuite/gas/mips/micromips.d: Update disassembly according to "dmtc1" entry fix with opcodes. * testsuite/gas/mips/micromips-compact.d: Likewise. * testsuite/gas/mips/micromips-insn32.d: Likewise. * testsuite/gas/mips/micromips-noinsn32.d: Likewise. * testsuite/gas/mips/micromips-trap.d: Likewise. * testsuite/gas/mips/micromips@isa-override-1.d: Likewise.
2021-03-31Use bool in opcodesAlan Modra1-22/+22
cpu/ * frv.opc: Replace bfd_boolean with bool, FALSE with false, and TRUE with true throughout. opcodes/ * sysdep.h (POISON_BFD_BOOLEAN): Define. * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h, * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h, * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c, * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c, * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c, * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c, * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c, * microblaze-dis.h, * micromips-opc.c, * mips-dis.c, * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c, * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c, * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c, * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c, * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false, and TRUE with true throughout.
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-06-30MIPS: Add microMIPS XPA supportMaciej W. Rozycki1-0/+12
Add support for the base and Virtualization ASE microMIPS instructions as per the architecture specifications[1][2][3][4]. Most of this change by Andrew Bennett. [1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00582, Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit Instructions", p. 340 [2] "microMIPS32 Architecture for Programmers Volume IV-i: Virtualization Module of the microMIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00848, Revision 1.06, December 10, 2013, Section 6.1 "Overview", pp. 133, 136 [3] "MIPS Architecture for Programmers Volume II-B: The microMIPS64 Instruction Set", MIPS Technologies, Inc., Document Number: MD00594, Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit Instructions", pp. 415, 444 [4] "microMIPS64 Architecture for Programmers Volume IV-i: Virtualization Module of the microMIPS64 Architecture", MIPS Technologies, Inc., Document Number: MD00849, Revision 1.06, December 10, 2013, Section 6.1 "Overview", pp. 134-135, 139-140 binutils/ * NEWS: Mention microMIPS XPA support. opcodes/ * micromips-opc.c (XPA, XPAVZ): New macros. (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and "mthgc0". gas/ * config/tc-mips.c (mips_ases): Add microMIPS XPA support. * testsuite/gas/mips/micromips@xpa.d: New test. * testsuite/gas/mips/mips.exp: Run the new test. Enable `xpa-virt-err' test for `micromips'.
2017-06-30MIPS: Add microMIPS R5 supportMaciej W. Rozycki1-0/+2
Add base microMIPS Release 5 ISA support and the ERETNC instruction in particular, as per the architecture specifications[1][2]. Most of this change by Andrew Bennett. References: [1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00582, Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit Instructions", pp. 266-267 [2] "MIPS Architecture for Programmers Volume II-B: The microMIPS64 Instruction Set", MIPS Technologies, Inc., Document Number: MD00594, Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit Instructions", pp. 326-327 binutils/ * NEWS: Mention microMIPS Release 5 ISA support. opcodes/ * micromips-opc.c (I36): New macro. (micromips_opcodes): Add "eretnc". gas/ * testsuite/gas/mips/micromips@r5.d: New test. * testsuite/gas/mips/mips.exp: Run the new test.
2017-05-12MIPS/opcodes: Mark descriptive SYNC mnemonics as aliasesMaciej W. Rozycki1-5/+5
Following the way how descriptive SYNC mnemonics have been defined in the architecture[1][2] mark them as aliases, so that the generic SYNC instruction can be alternatively disassembled along with its immediate operand, as noted in the documents referred. References: [1] "MIPS Architecture For Programmers, Volume II-A: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 5.04, December 11, 2013, Table 4.7 "Encodings of the Bits[10:6] of the SYNC instruction; the SType Field", p. 305 [2] "MIPS Architecture for Programmers, Volume II-B: The microMIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00582, Revision 5.04, January 15, 2014, Table 5.28 "Encodings of the Bits[10:6] of the SYNC instruction; the SType Field", p. 481 opcodes/ * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs", "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases. * micromips-opc.c (micromips_opcodes): Mark "sync_acquire", "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases. gas/ * testsuite/gas/mips/mips32r2-sync-1.d: New test. * testsuite/gas/mips/micromips@mips32r2-sync-1.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests.
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-07-27MIPS/GAS: Implement microMIPS branch/jump compactionMaciej W. Rozycki1-7/+15
Convert microMIPS branches and jumps whose delay slot would be filled by a generated NOP instruction to the corresponding compact form where one exists, in a manner similar to MIPS16 JR->JRC and JALR->JALRC swap. Do so even where the transformation switches from a 16-bit to a 32-bit branch encoding for no benefit in code size reduction, as this is still advantageous. This is because a branch/NOP pair takes 2 pipeline slots or a 2-cycle completion latency except in superscalar implementations. Whereas a compact branch may or may not stall on its target fetch, so it will at most have a 2-cycle completion latency and may have only 1 even in scalar implementations, and in superscalar implementations it is expected to have no worse latency as a branch/NOP pair has. Also it won't stall and therefore take the extra latency cycle in the not-taken case. Technically this is the same as MIPS16 compaction: for the qualifying instruction encodings the APPEND_ADD_COMPACT machine code generation method is selected where APPEND_ADD_WITH_NOP otherwise would and tells the code generator in `append_insn' to convert the regular form of an instruction to its corresponding compact form. For this the opcode is tweaked as necessary and the microMIPS opcode table is scanned for the matching updated instruction. A non-$0 `rt' operand to BEQ and BNE instructions is moved to the `rs' operand field of BEQZC and BNEZC encodings as required. Unlike with MIPS16 compaction however we need to handle out-of-distance branch relaxation as well. We do this by deferring the generation of any delay-slot NOP required to relaxation made in `md_convert_frag', by converting the APPEND_ADD_WITH_NOP machine code generation to APPEND_ADD where a relaxed instruction is recorded. Relaxation then, depending on actual code produced, chooses between either using a compact branch or jump encoding and emitting the NOP outstanding if no compact encoding is possible. For code simplicity's sake the relaxation pass is retained even if the principle of preferring a compact encoding to a 16-bit branch/NOP pair means, in the absence of out-of-range branch relaxation, that a single compact branch machine code instruction will eventually be produced from a given assembly source instruction. gas/ * config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Add `nods' flag. (RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16) (RELAX_MICROMIPS_MARK_TOOFAR16, RELAX_MICROMIPS_CLEAR_TOOFAR16) (RELAX_MICROMIPS_TOOFAR32, RELAX_MICROMIPS_MARK_TOOFAR32) (RELAX_MICROMIPS_CLEAR_TOOFAR32): Shift bits. (get_append_method): Also return APPEND_ADD_COMPACT for microMIPS instructions. (find_altered_mips16_opcode): Exclude macros from matching. Factor code out... (find_altered_opcode): ... to this new function. (find_altered_micromips_opcode): New function. (frag_branch_delay_slot_size): Likewise. (append_insn): Handle microMIPS branch/jump compaction. (macro_start): Likewise. (relaxed_micromips_32bit_branch_length): Likewise. (md_convert_frag): Likewise. * testsuite/gas/mips/micromips.s: Add conditional explicit NOPs for delay slot filling. * testsuite/gas/mips/micromips-b16.s: Add explicit NOPs for delay slot filling. * testsuite/gas/mips/micromips-size-1.s: Likewise. * testsuite/gas/mips/micromips.l: Adjust line numbers. * testsuite/gas/mips/micromips-warn.l: Likewise. * testsuite/gas/mips/micromips-size-1.l: Likewise. * testsuite/gas/mips/micromips.d: Adjust padding. * testsuite/gas/mips/micromips-trap.d: Likewise. * testsuite/gas/mips/micromips-insn32.d: Likewise. * testsuite/gas/mips/micromips-noinsn32.d: Likewise. * testsuite/gas/mips/micromips@beq.d: Update patterns for branch/jump compaction. * testsuite/gas/mips/micromips@bge.d: Likewise. * testsuite/gas/mips/micromips@bgeu.d: Likewise. * testsuite/gas/mips/micromips@blt.d: Likewise. * testsuite/gas/mips/micromips@bltu.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-4.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-4-64.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-5.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-5pic.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-5-64.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise. * testsuite/gas/mips/micromips@jal-svr4pic-local.d: Likewise. * testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d: Likewise. * testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d: Likewise. * testsuite/gas/mips/micromips@loc-swap.d: Likewise. * testsuite/gas/mips/micromips@loc-swap-dis.d: Likewise. * testsuite/gas/mips/micromips@relax.d: Likewise. * testsuite/gas/mips/micromips@relax-at.d: Likewise. * testsuite/gas/mips/micromips@relax-swap3.d: Likewise. * testsuite/gas/mips/branch-extern-2.d: Likewise. * testsuite/gas/mips/branch-extern-4.d: Likewise. * testsuite/gas/mips/branch-section-2.d: Likewise. * testsuite/gas/mips/branch-section-4.d: Likewise. * testsuite/gas/mips/branch-weak-2.d: Likewise. * testsuite/gas/mips/branch-weak-5.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-addend.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-addend-n32.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-addend-n64.d: Likewise. * testsuite/gas/mips/micromips-compact.d: New test. * testsuite/gas/mips/mips.exp: Run the new test. ld/ * testsuite/ld-mips-elf/micromips-branch-absolute.d: Update patterns for branch compaction. * testsuite/ld-mips-elf/micromips-branch-absolute-addend.d: Likewise. opcodes/ * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b", "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to "j".
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-08-12[MIPS] Map 'move' to 'or'.Simon Dardis1-2/+1
The MIPS assembly idiom 'move' now maps to the 'or' machine instruction. This change affects microMIPS, MIPS32, MIPS64. 2015-08-12 Simon Dardis <simon.dardis@imgtec.com> opcodes/ * micromips-opc.c (micromips_opcodes): Re-order table so that move based on 'or' is first. * mips-opc.c (mips_builtin_opcodes): Ditto. bfd/ * elfxx-mips.c (STUB_MOVE): Change to use 'or' only. (mips_o32_exec_plt0_entry, mips_n32_exec_plt0_entry, mips_n64_exec_plt0_entry, micromips_insn32_o32_exec_plt0_entry): Update to use 'or' instead of 'addu/daddu'. (_bfd_mips_elf_finish_dynamic_symbol): Update usage of STUB_MOVE. (move_insns_32): Reorder table. gas/ * config/tc-mips.c (move_register): Change to use 'or' only. (s_cpload, s_cpsetup, s_cprestore, s_cpreturn): Update to use or for move. gas/testsuite/ * gas/mips/elf-rel23.d: Update test. * gas/mips/elf-rel23.d: Ditto. * gas/mips/elf-rel23a.d: Ditto. * gas/mips/elf-rel23b.d: Ditto. * gas/mips/elf_e_flags1.d: Ditto. * gas/mips/elf_e_flags2.d: Ditto. * gas/mips/elf_e_flags3.d: Ditto. * gas/mips/elf_e_flags4.d: Ditto. * gas/mips/loc-swap-dis.d: Ditto. * gas/mips/micromips-insn32.d: Ditto. * gas/mips/micromips-noinsn32.d: Ditto. * gas/mips/micromips-trap.d: Ditto. * gas/mips/micromips.d: Ditto. * gas/mips/mips-abi32-pic.d: Ditto. * gas/mips/mips-abi32.d: Ditto. * gas/mips/mips-gp32-fp32-pic.d: Ditto. * gas/mips/mips-gp32-fp32.d: Ditto. * gas/mips/mips-gp32-fp64-pic.d: Ditto. * gas/mips/mips-gp32-fp64.d: Ditto. * gas/mips/mips-gp64-fp32-pic.d: Ditto. * gas/mips/mips-gp64-fp32.d: Ditto. * gas/mips/mips-gp64-fp64-pic.d: Ditto. * gas/mips/mips-gp64-fp64.d: Ditto. * gas/mips/mipsr6@loc-swap-dis.d: Ditto. * gas/mips/tls-o32.d: Ditto. * gas/mips/uld2-eb.d: Ditto. * gas/mips/uld2-el.d: Ditto. * gas/mips/ulw2-eb-ilocks.d: Ditto. * gas/mips/ulw2-eb.d: Ditto. * gas/mips/ulw2-el-ilocks.d: Ditto. * gas/mips/ulw2-el.d: Ditto. * gas/mips/move.d: New test. * gas/mips/move.s: Ditto. * gas/mips/micromips32-move.d: Ditto. * gas/mips/micromips32-move.s: Ditto. * gas/mips/mips.exp: Run the new tests. gold/ * mips.cc (plt0_entry_o32, plt0_entry_n32, plt0_entry_n64, lazy_stub_normal_1, lazy_stub_normal_1_n64, lazy_stub_normal_2, lazy_stub_normal_2_n64, lazy_stub_big, lazy_stub_big_n64, lazy_stub_micromips32_normal_1_n64, lazy_stub_micromips32_normal_2_n64, lazy_stub_micromips32_big, lazy_stub_micromips32_big_n64): Update to use 'or' for move instead of 'addu/daddu'. ld/testsuite/ * ld-mips-elf/compressed-plt-1-n32-mips16.od: Update test. * ld-mips-elf/compressed-plt-1-n32-umips.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-mips16-got.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-mips16-only.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-mips16-word.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-mips16.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-se.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-umips-got.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-umips-word.od: Ditto. * ld-mips-elf/compressed-plt-1-o32-umips.od: Ditto. * ld-mips-elf/jalx-2.dd: Ditto. * ld-mips-elf/mips16-pic-3.dd: Ditto. * ld-mips-elf/pic-and-nonpic-3a.dd: Ditto. * ld-mips-elf/pic-and-nonpic-3b.dd: Ditto. * ld-mips-elf/pic-and-nonpic-5b.dd: Ditto. * ld-mips-elf/pic-and-nonpic-6-n32.dd: Ditto. * ld-mips-elf/pic-and-nonpic-6-o32.dd: Ditto. * ld-mips-elf/stub-dynsym-1-10000.d: Ditto. * ld-mips-elf/stub-dynsym-1-2fe80.d: Ditto. * ld-mips-elf/stub-dynsym-1-7fff.d: Ditto. * ld-mips-elf/stub-dynsym-1-8000.d: Ditto. * ld-mips-elf/stub-dynsym-1-fff0.d: Ditto. * ld-mips-elf/tlsbin-o32.d: Ditto. * ld-mips-elf/tlsdyn-o32-1.d: Ditto. * ld-mips-elf/tlsdyn-o32-2.d: Ditto. * ld-mips-elf/tlsdyn-o32-3.d: Ditto. * ld-mips-elf/tlsdyn-o32.d: Ditto. * ld-mips-elf/tlslib-o32.d: Ditto.
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-08-26MIPS: Make the CODE10 operand code consistent between ISAsMaciej W. Rozycki1-5/+5
This change moves the microMIPS 10-bit uninterpreted immediate code embedded at bits 25..16 in the SYSCALL, WAIT, SDBBP and HYPCALL instructions from `B' over to `+J' which is the operand code used in the standard MIPS instruction set for a similar code embedded at bits 20..11, currently used by HYPCALL only in that set. opcodes/ * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'. (micromips_opcodes): Use "+J" in place of "B" for "hypcall", "sdbbp", "syscall" and "wait". include/opcode/ * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B' over to `+J'.
2014-08-21MIPS/opcodes: Remove microMIPS 48-bit LI instructionMaciej W. Rozycki1-4/+0
The 48-bit LI instruction encoding has been removed from the microMIPS ISA and no implementation ever made that included it. * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out 48-bit "li" encoding.
2014-07-29[MIPS] Rename COPROC related macrosMatthew Fortune1-14/+14
gas/ * config/tc-mips.c: Rename INSN_LOAD_COPROC_DELAY to INSN_LOAD_COPROC and INSN_COPROC_MOVE_DELAY to INSN_COPROC_MOVE throughout. include/opcode/ * mips.h (INSN_LOAD_COPROC_DELAY): Rename to... (INSN_LOAD_COPROC): New define. (INSN_COPROC_MOVE_DELAY): Rename to... (INSN_COPROC_MOVE): New define. opcodes/ * micromips-opc.c (COD): Rename throughout to... (CM): New define, update to use INSN_COPROC_MOVE. (LCD): Rename throughout to... (LC): New define, update to use INSN_LOAD_COPROC. * mips-opc.c: Likewise.
2014-07-29[MIPS] Implement O32 FPXX, FP64 and FP64A ABI extensionsMatthew Fortune1-16/+18
Specification: https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking include/ * elf/mips.h (PT_MIPS_ABIFLAGS, SHT_MIPS_ABIFLAGS): Define. (Val_GNU_MIPS_ABI_FP_OLD_64): Rename from Val_GNU_MIPS_ABI_FP_64. (Val_GNU_MIPS_ABI_FP_64): Redefine. (Val_GNU_MIPS_ABI_FP_XX): Define. (Elf_External_ABIFlags_v0, Elf_Internal_ABIFlags_v0): New structures. (AFL_REG_NONE, AFL_REG_32, AFL_REG_64, AFL_REG_128): Define. (AFL_ASE_DSP, AFL_ASE_DSPR2, AFL_ASE_EVA, AFL_ASE_MCU): Likewise. (AFL_ASE_MDMX, AFL_ASE_MIPS3D, AFL_ASE_MT, AFL_ASE_SMARTMIPS): Likewise. (AFL_ASE_VIRT, AFL_ASE_MSA, AFL_ASE_MIPS16): Likewise. (AFL_ASE_MICROMIPS, AFL_ASE_XPA): Likewise. (AFL_EXT_XLR, AFL_EXT_OCTEON2, AFL_EXT_OCTEONP): Likewise. (AFL_EXT_LOONGSON_3A, AFL_EXT_OCTEON, AFL_EXT_5900): Likewise. (AFL_EXT_4650, AFL_EXT_4010, AFL_EXT_4100, AFL_EXT_3900): Likewise. (AFL_EXT_10000, AFL_EXT_SB1, AFL_EXT_4111, AFL_EXT_4120): Likewise. (AFL_EXT_5400, AFL_EXT_5500, AFL_EXT_LOONGSON_2E): Likewise. (AFL_EXT_LOONGSON_2F): Likewise. (bfd_mips_elf_swap_abiflags_v0_in): Prototype. (bfd_mips_elf_swap_abiflags_v0_out): Likewise. (bfd_mips_isa_ext): Likewise. bfd/ * elfxx-mips.c (ABI_O32_P, MIPS_ELF_ABIFLAGS_SECTION_NAME_P): New macro. (mips_elf_obj_tdata): Add abiflags and abiflags_valid fields. (bfd_mips_elf_swap_abiflags_v0_in): New function. (bfd_mips_elf_swap_abiflags_v0_out): Likewise. (_bfd_mips_elf_section_from_shdr): Handle SHT_MIPS_ABIFLAGS. (_bfd_mips_elf_fake_sections): Likewise. (_bfd_mips_elf_always_size_sections): Handle .MIPS.abiflags. (_bfd_mips_elf_additional_program_headers): Account for new PT_MIPS_ABIFLAGS program header. (_bfd_mips_elf_modify_segment_map): Create PT_MIPS_ABIFLAGS segment and associate with .MIPS.abiflags. (_bfd_mips_elf_gc_mark_extra_sections): New function. (bfd_mips_isa_ext, update_mips_abiflags_isa): New static function. (infer_mips_abiflags): Likewise. (_bfd_mips_elf_final_link): Handle .MIPS.abiflags. (mips_32bit_flags_p): Moved higher. (mips_elf_merge_obj_attributes, _bfd_mips_fp_abi_string): Error checking for FP ABIs. (_bfd_mips_elf_merge_private_bfd_data): Restructure and add abiflags checks. Check EF_MIPS_FP64 flag consistency. (print_mips_ases, print_mips_isa_ext): New static function. (print_mips_fp_abi_value, get_mips_reg_size): Likewise. (_bfd_mips_elf_print_private_bfd_data): Display abiflags data. (_bfd_mips_post_process_headers): Set EI_ABIVERSION = 3 for Val_GNU_MIPS_ABI_FP_64 or Val_GNU_MIPS_ABI_FP_64A. * elfxx-mips.h (_bfd_mips_elf_gc_mark_extra_sections): New prototype. * elf32-mips.c (elf_backend_gc_mark_extra_sections): Implement. * elfn32-mips.c (elf_backend_gc_mark_extra_sections): Implement. * elf64-mips.c (elf_backend_gc_mark_extra_sections): Implement. binutils/ * readelf.c (get_mips_segment_type): Display name for PT_MIPS_ABIFLAGS. (get_mips_section_type_name): Display name for SHT_MIPS_ABIFLAGS. (display_mips_gnu_attribute): Abstracted fp abi printing to... (print_mips_fp_abi_value): New static function. Handle new FP ABIs. (print_mips_ases, print_mips_isa_ext): New static functions. (get_mips_reg_size): Likewise. (process_mips_specific): Display abiflags data. elfcpp/ * elfcpp.h (PT_MIPS_ABIFLAGS): New program header type. gas/ * config/tc-mips.c (mips_flags_frag): New static global. (struct mips_set_options): Add oddspreg field. (file_mips_opts, mips_opts): Initialize oddspreg. (ISA_HAS_ODD_SINGLE_FPR): Add CPU argument and update for R5900 and Loongson-3a. (enum options, md_longopts, md_parse_option): Add -mfpxx, -modd-spreg and -mno-odd-spreg options. (md_begin): Create .MIPS.abiflags section. (fpabi_incompatible_with, fpabi_requires): New static function. (check_fpabi): Likewise. (mips_check_options): Handle fp=xx and oddspreg restrictions. (file_mips_check_options): Set oddspreg by default for fp=xx. (mips_oddfpreg_ok): Re-write function. (check_regno): Check odd numbered registers regardless of FPR size. For fp != 32 use as_bad instead of as_warn. (match_float_constant): Rewrite check regarding FP register width. Add support for generating constants when MXHC1 is present. Handle fp=xx to comply with the ABI. (macro): Update M_LI_DD similarly to match_float_constant. Generate MTHC1 when available. Check that correct code can be generated for fp=xx and fp=64 ABIs. (parse_code_option, s_mipsset): Add fp=xx, oddspreg and nooddspreg options. (mips_convert_ase_flags): New static function. (mips_elf_final_processing): Use fpabi == Val_GNU_MIPS_ABI_FP_OLD_64 to determine when to add the EF_MIPS_FP64 flag. Populate the .MIPS.abiflags section. (md_mips_end): Update .gnu_attribute based on command line and .module as applicable. Use check_fpabi to ensure .gnu.attribute and command line/.module options are consistent. * doc/as.texinfo: Add missing -mgp64/-mfp64 options and document new -mfpxx, -modd-spreg and -mno-odd-spreg options. * doc/c-mips.texi: Document -mfpxx, -modd-spreg, -mno-odd-spreg, gnu_attribute values and FP ABIs. ld/ * emulparams/elf32bmip.sh: Add .MIPS.abiflags. * emulparams/elf32bmipn32-defs.sh: Likewise. * emulparams/elf64bmip-defs.sh: Likewise. opcodes/ * micromips-opc.c (COD, LCD) New macros. (cfc1, ctc1): Remove FP_S attribute. (dmfc1, mfc1, mfhc1): Add LCD attribute. (dmtc1, mtc1, mthc1): Add COD attribute. * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute. binutils/testsuite/ * binutils-all/readelf.s: Account for .MIPS.abiflags and .gnu.attributes. * binutils-all/readelf.ss-tmips: Likewise. * binutils-all/strip-3.d: Likewise. gas/testsuite/ * gas/mips/attr-gnu-4-0.d: New. * gas/mips/attr-gnu-4-0.s: Likewise. * gas/mips/attr-gnu-4-1-mfp32.l: Likewise. * gas/mips/attr-gnu-4-1-mfp32.s: Likewise. * gas/mips/attr-gnu-4-1-mfp64.l: Likewise. * gas/mips/attr-gnu-4-1-mfp64.s: Likewise. * gas/mips/attr-gnu-4-1-mfpxx.s: Likewise. * gas/mips/attr-gnu-4-1-msingle-float.l: Likewise. * gas/mips/attr-gnu-4-1-msingle-float.s: Likewise. * gas/mips/attr-gnu-4-1-msoft-float.l: Likewise. * gas/mips/attr-gnu-4-1-msoft-float.s: Likewise. * gas/mips/attr-gnu-4-1.d: Likewise. * gas/mips/attr-gnu-4-1.s: Likewise. * gas/mips/attr-gnu-4-2-mdouble-float.l: Likewise. * gas/mips/attr-gnu-4-2-mdouble-float.s: Likewise. * gas/mips/attr-gnu-4-2-msoft-float.l: Likewise. * gas/mips/attr-gnu-4-2-msoft-float.s: Likewise. * gas/mips/attr-gnu-4-2.d: Likewise. * gas/mips/attr-gnu-4-2.s: Likewise. * gas/mips/attr-gnu-4-3-mhard-float.l: Likewise. * gas/mips/attr-gnu-4-3-mhard-float.s: Likewise. * gas/mips/attr-gnu-4-3.d: Likewise. * gas/mips/attr-gnu-4-3.s: Likewise. * gas/mips/attr-gnu-4-4.l: Likewise. * gas/mips/attr-gnu-4-4.s: Likewise. * gas/mips/attr-gnu-4-5-64.l: Likewise. * gas/mips/attr-gnu-4-5-64.s: Likewise. * gas/mips/attr-gnu-4-5.d: Likewise. * gas/mips/attr-gnu-4-5.l: Likewise. * gas/mips/attr-gnu-4-5.s: Likewise. * gas/mips/attr-gnu-4-6-64.l: Likewise. * gas/mips/attr-gnu-4-6-64.s: Likewise. * gas/mips/attr-gnu-4-6.d: Likewise. * gas/mips/attr-gnu-4-6.l: Likewise. * gas/mips/attr-gnu-4-6.s: Likewise. * gas/mips/attr-gnu-4-6-msingle-float.l: Likewise. * gas/mips/attr-gnu-4-6-msingle-float.s: Likewise. * gas/mips/attr-gnu-4-6-msoft-float.l: Likewise. * gas/mips/attr-gnu-4-6-msoft-float.s: Likewise. * gas/mips/attr-gnu-4-6-noodd.l: Likewise. * gas/mips/attr-gnu-4-6-noodd.s: Likewise. * gas/mips/attr-gnu-4-7-64.l: Likewise. * gas/mips/attr-gnu-4-7-64.s: Likewise. * gas/mips/attr-gnu-4-7-msingle-float.l: Likewise. * gas/mips/attr-gnu-4-7-msingle-float.s: Likewise. * gas/mips/attr-gnu-4-7-msoft-float.l: Likewise. * gas/mips/attr-gnu-4-7-msoft-float.s: Likewise. * gas/mips/attr-gnu-4-7-odd.l: Likewise. * gas/mips/attr-gnu-4-7-odd.s: Likewise. * gas/mips/attr-gnu-4-7.d: Likewise. * gas/mips/attr-gnu-4-7.l: Likewise. * gas/mips/attr-gnu-4-7.s: Likewise. * gas/mips/attr-none-double.d: Likewise. * gas/mips/attr-none-o32-fp64.d: Likewise. * gas/mips/attr-none-o32-fp64-nooddspreg.d * gas/mips/attr-none-o32-fpxx.d: Likewise. * gas/mips/attr-none-single-float.d: Likewise. * gas/mips/attr-none-soft-float.d: Likewise. * gas/mips/elf_arch_mips32r3.d: Likewise. * gas/mips/elf_arch_mips32r5.d: Likewise. * gas/mips/elf_arch_mips64r3.d: Likewise. * gas/mips/elf_arch_mips64r5.d: Likewise. * gas/mips/li-d.d: Likewise. * gas/mips/li-d.s: Likewise. * gas/mips/module-check-warn.l: Likewise. * gas/mips/module-check-warn.s: Likewise. * gas/mips/module-check.d: Likewise. * gas/mips/module-check.s: Likewise. * gas/mips/module-mfp32.d: Likewise. * gas/mips/module-mfp32.s: Likewise. * gas/mips/module-mfp64.d: Likewise. * gas/mips/module-mfp64.s: Likewise. * gas/mips/module-mfp64-noodd.d: Likewise. * gas/mips/module-mfp64-noodd.s: Likewise. * gas/mips/module-mfpxx.d: Likewise. * gas/mips/module-mfpxx.s: Likewise. * gas/mips/module-msingle-float.d: Likewise. * gas/mips/module-msingle-float.s: Likewise. * gas/mips/module-msoft-float.d: Likewise. * gas/mips/module-msoft-float.s: Likewise. * gas/mips/module-set-mfpxx.d: Likewise. * gas/mips/module-set-mfpxx.s: Likewise. * gas/mips/fpxx-oddfpreg.d: Likewise. * gas/mips/fpxx-oddfpreg.l: Likewise. * gas/mips/fpxx-oddfpreg.s: Likewise. * gas/mips/no-odd-spreg.d: Likewise. * gas/mips/odd-spreg.d: Likewise. * gas/elf/section2.e-mips: Adjust expected output. * gas/mips/attr-gnu-abi-fp-1.d: Likewise. * gas/mips/attr-gnu-abi-msa-1.d: Likewise. * gas/mips/call-nonpic-1.d: Likewise. * gas/mips/elf_arch_mips1.d: Likewise. * gas/mips/elf_arch_mips2.d: Likewise. * gas/mips/elf_arch_mips3.d: Likewise. * gas/mips/elf_arch_mips32.d: Likewise. * gas/mips/elf_arch_mips32r2.d: Likewise. * gas/mips/elf_arch_mips4.d: Likewise. * gas/mips/elf_arch_mips5.d: Likewise. * gas/mips/elf_arch_mips64.d: Likewise. * gas/mips/elf_arch_mips64r2.d: Likewise. * gas/mips/elf_ase_micromips-2.d: Likewise. * gas/mips/elf_ase_micromips.d: Likewise. * gas/mips/elf_ase_mips16-2.d: Likewise. * gas/mips/elf_ase_mips16.d: Likewise. * gas/mips/module-defer-warn1.d: Likewise. * gas/mips/module-override.d: Likewise. * gas/mips/n32-consec.d: Likewise. * gas/mips/nan-2008-1.d: Likewise. * gas/mips/nan-2008-2.d: Likewise. * gas/mips/nan-2008-3.d: Likewise. * gas/mips/nan-2008-4.d: Likewise. * gas/mips/nan-legacy-1.d: Likewise. * gas/mips/nan-legacy-2.d: Likewise. * gas/mips/nan-legacy-3.d: Likewise. * gas/mips/nan-legacy-4.d: Likewise. * gas/mips/nan-legacy-5.d: Likewise. * gas/mips/tmips16-e.d: Likewise. * gas/mips/tmips16-f.d: Likewise. * gas/mips/tmipsel16-e.d: Likewise. * gas/mips/tmipsel16-f.d: Likewise. * gas/testsuite/gas/mips/mips.exp: Add new tests. ld/testsuite/ * ld-mips-elf/abiflags-strip1-ph.d: New. * ld-mips-elf/abiflags-strip2-ph.d: Likewise. * ld-mips-elf/abiflags-strip3-ph.d: Likewise. * ld-mips-elf/abiflags-strip4-ph.d: Likewise. * ld-mips-elf/abiflags-strip5-ph.d: Likewise. * ld-mips-elf/abiflags-strip6-ph.d: Likewise. * ld-mips-elf/abiflags-strip7-ph.d: Likewise. * ld-mips-elf/abiflags-strip8-ph.d: Likewise. * ld-mips-elf/abiflags-strip9-ph.d: Likewise. * ld-mips-elf/attr-gnu-4-0-n32-ph.d: Likewise. * ld-mips-elf/attr-gnu-4-0-n64-ph.d: Likewise. * ld-mips-elf/attr-gnu-4-0-ph.d: Likewise. * ld-mips-elf/attr-gnu-4-06.d: Likewise. * ld-mips-elf/attr-gnu-4-07.d: Likewise. * ld-mips-elf/attr-gnu-4-08.d: Likewise. * ld-mips-elf/attr-gnu-4-1-n32-ph.d: Likewise. * ld-mips-elf/attr-gnu-4-1-n64-ph.d: Likewise. * ld-mips-elf/attr-gnu-4-1-ph.d: Likewise. * ld-mips-elf/attr-gnu-4-16.d: Likewise. * ld-mips-elf/attr-gnu-4-17.d: Likewise. * ld-mips-elf/attr-gnu-4-18.d: Likewise. * ld-mips-elf/attr-gnu-4-2-n32-ph.d: Likewise. * ld-mips-elf/attr-gnu-4-2-n64-ph.d: Likewise. * ld-mips-elf/attr-gnu-4-2-ph.d: Likewise. * ld-mips-elf/attr-gnu-4-26.d: Likewise. * ld-mips-elf/attr-gnu-4-27.d: Likewise. * ld-mips-elf/attr-gnu-4-28.d: Likewise. * ld-mips-elf/attr-gnu-4-3-n32-ph.d: Likewise. * ld-mips-elf/attr-gnu-4-3-n64-ph.d: Likewise. * ld-mips-elf/attr-gnu-4-3-ph.d: Likewise. * ld-mips-elf/attr-gnu-4-36.d: Likewise. * ld-mips-elf/attr-gnu-4-37.d: Likewise. * ld-mips-elf/attr-gnu-4-38.d: Likewise. * ld-mips-elf/attr-gnu-4-4-ph.d: Likewise. * ld-mips-elf/attr-gnu-4-46.d: Likewise. * ld-mips-elf/attr-gnu-4-47.d: Likewise. * ld-mips-elf/attr-gnu-4-48.d: Likewise. * ld-mips-elf/attr-gnu-4-5-ph.d: Likewise. * ld-mips-elf/attr-gnu-4-50.d: Likewise. * ld-mips-elf/attr-gnu-4-52.d: Likewise. * ld-mips-elf/attr-gnu-4-53.d: Likewise. * ld-mips-elf/attr-gnu-4-54.d: Likewise. * ld-mips-elf/attr-gnu-4-55.d: Likewise. * ld-mips-elf/attr-gnu-4-56.d: Likewise. * ld-mips-elf/attr-gnu-4-57.d: Likewise. * ld-mips-elf/attr-gnu-4-58.d: Likewise. * ld-mips-elf/attr-gnu-4-6-ph.d: Likewise. * ld-mips-elf/attr-gnu-4-6.s: Likewise. * ld-mips-elf/attr-gnu-4-60.d: Likewise. * ld-mips-elf/attr-gnu-4-61.d: Likewise. * ld-mips-elf/attr-gnu-4-62.d: Likewise. * ld-mips-elf/attr-gnu-4-63.d: Likewise. * ld-mips-elf/attr-gnu-4-64.d: Likewise. * ld-mips-elf/attr-gnu-4-65.d: Likewise. * ld-mips-elf/attr-gnu-4-66.d: Likewise. * ld-mips-elf/attr-gnu-4-67.d: Likewise. * ld-mips-elf/attr-gnu-4-68.d: Likewise. * ld-mips-elf/attr-gnu-4-7-ph.d: Likewise. * ld-mips-elf/attr-gnu-4-7.s: Likewise. * ld-mips-elf/attr-gnu-4-70.d: Likewise. * ld-mips-elf/attr-gnu-4-71.d: Likewise. * ld-mips-elf/attr-gnu-4-72.d: Likewise. * ld-mips-elf/attr-gnu-4-73.d: Likewise. * ld-mips-elf/attr-gnu-4-74.d: Likewise. * ld-mips-elf/attr-gnu-4-75.d: Likewise. * ld-mips-elf/attr-gnu-4-76.d: Likewise. * ld-mips-elf/attr-gnu-4-77.d: Likewise. * ld-mips-elf/attr-gnu-4-78.d: Likewise. * ld-mips-elf/attr-gnu-4-8.s: Likewise. * ld-mips-elf/attr-gnu-4-81.d: Likewise. * ld-mips-elf/empty.s: Likewise. * ld-mips-elf/attr-gnu-4-00.d: Adjust expected output. * ld-mips-elf/attr-gnu-4-01.d: Likewise. * ld-mips-elf/attr-gnu-4-02.d: Likewise. * ld-mips-elf/attr-gnu-4-03.d: Likewise. * ld-mips-elf/attr-gnu-4-04.d: Likewise. * ld-mips-elf/attr-gnu-4-05.d: Likewise. * ld-mips-elf/attr-gnu-4-10.d: Likewise. * ld-mips-elf/attr-gnu-4-11.d: Likewise. * ld-mips-elf/attr-gnu-4-14.d: Likewise. * ld-mips-elf/attr-gnu-4-15.d: Likewise. * ld-mips-elf/attr-gnu-4-2.s: Likewise. * ld-mips-elf/attr-gnu-4-20.d: Likewise. * ld-mips-elf/attr-gnu-4-22.d: Likewise. * ld-mips-elf/attr-gnu-4-24.d: Likewise. * ld-mips-elf/attr-gnu-4-25.d: Likewise. * ld-mips-elf/attr-gnu-4-3.s: Likewise. * ld-mips-elf/attr-gnu-4-30.d: Likewise. * ld-mips-elf/attr-gnu-4-33.d: Likewise. * ld-mips-elf/attr-gnu-4-34.d: Likewise. * ld-mips-elf/attr-gnu-4-35.d: Likewise. * ld-mips-elf/attr-gnu-4-40.d: Likewise. * ld-mips-elf/attr-gnu-4-41.d: Likewise. * ld-mips-elf/attr-gnu-4-42.d: Likewise. * ld-mips-elf/attr-gnu-4-43.d: Likewise. * ld-mips-elf/attr-gnu-4-44.d: Likewise. * ld-mips-elf/attr-gnu-4-45.d: Likewise. * ld-mips-elf/attr-gnu-4-5.s: Likewise. * ld-mips-elf/attr-gnu-4-51.d: Likewise. * ld-mips-elf/attr-gnu-8-00.d: Likewise. * ld-mips-elf/attr-gnu-8-01.d: Likewise. * ld-mips-elf/attr-gnu-8-02.d: Likewise. * ld-mips-elf/attr-gnu-8-10.d: Likewise. * ld-mips-elf/attr-gnu-8-11.d: Likewise. * ld-mips-elf/attr-gnu-8-20.d: Likewise. * ld-mips-elf/attr-gnu-8-22.d: Likewise. * ld-mips-elf/jalx-2.dd: Likewise. * ld-mips-elf/mips16-pic-1.gd: Likewise. * ld-mips-elf/mips16-pic-2.gd: Likewise. * ld-mips-elf/mips16-pic-3.gd: Likewise. * ld-mips-elf/mips16-pic-4a.gd: Likewise. * ld-mips-elf/multi-got-no-shared.d: Likewise. * ld-mips-elf/nan-2008.d: Likewise. * ld-mips-elf/nan-legacy.d: Rework test. * ld-mips-elf/pic-and-nonpic-3a.gd: Likewise. * ld-mips-elf/pic-and-nonpic-3b.gd: Likewise. * ld-mips-elf/pic-and-nonpic-5b.gd: Likewise. * ld-mips-elf/pic-and-nonpic-6.ld: Likewise. * ld-mips-elf/rel32-n32.d: Likewise. * ld-mips-elf/rel32-o32.d: Likewise. * ld-mips-elf/rel64.d: Likewise. * ld-mips-elf/tls-multi-got-1.r: Likewise. * ld-elf/group.ld: Discard .MIPS.abiflags and .gnu.attributes. * ld-elf/orphan-region.ld: Likewise. * ld-elf/orphan.ld: Likewise. * ld-mips-elf/compressed-plt-1.ld: Likewise. * ld-mips-elf/dyn-sec64.ld: Likewise. * ld-mips-elf/got-dump-1.ld: Likewise. * ld-mips-elf/got-dump-2.ld: Likewise. * ld-mips-elf/got-page-1.ld: Likewise. * ld-mips-elf/mips-dyn.ld: Likewise. * ld-mips-elf/mips-lib.ld: Likewise. * ld-mips-elf/pic-and-nonpic-3a.ld: Likewise. * ld-mips-elf/pic-and-nonpic-3b.ld: Likewise. * ld-mips-elf/pic-and-nonpic-4b.ld: Likewise. * ld-mips-elf/pic-and-nonpic-5b.ld: Likewise. * ld-mips-elf/region1.t: Likewise. * ld-mips-elf/stub-dynsym-1.ld: Likewise. * ld-mips-elf/tls-hidden3.ld: Likewise. * ld-mips-elf/vxworks1.ld: Likewise. * ld-scripts/overlay-size.t: Likewise. * ld-mips-elf/elf-rel-got-n32-embed.d: Remove .MIPS.abiflags from objects. * ld-mips-elf/elf-rel-got-n32.d: Likewise. * ld-mips-elf/elf-rel-got-n64-embed.d: Likewise. * ld-mips-elf/elf-rel-got-n64-linux.d: Likewise. * ld-mips-elf/elf-rel-got-n64.d: Likewise. * ld-mips-elf/elf-rel-xgot-n32.d: Likewise. * ld-mips-elf/elf-rel-xgot-n32-embed.d: Likewise. * ld-mips-elf/elf-rel-xgot-n64.d: Likewise. * ld-mips-elf/elf-rel-xgot-n64-linux.d: Likewise. * ld-mips-elf/elf-rel-xgot-n64-embed.d: Likewise. * ld-mips-elf/mips-elf.exp: Add new tests.
2014-03-05Update copyright yearsAlan Modra1-1/+1
2013-12-16Range of element index is too large on MIPS MSA element selection instructions.Andrew Bennett1-28/+28
The element index range for the following MIPS MSA instructions: sldi, splati, copy_s, copy_u, insert and insve is 1 bit too large. This patch fixes this issue. ChangeLog: gas/testsuite/gas/mips/ * msa.s: Reduced maximum element index range for sldi, splati, copy_s, copy_u, insert and insve instructions. * msa64.s: Likewise. * micromips@msa.d: Likewise. * micromips@msa64.d: Likewise. * msa.d: Likewise. * msa64.d: Likewise. include/opcode/ * mips.h: Updated description of +o, +u, +v and +w for MIPS and microMIPS. opcodes/ * micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u, +v and +w. (micromips_opcodes): Reduced element index range for sldi, splati, copy_s, copy_u, insert and insve instructions. * opcodes/mips-opc.c (decode_mips_operand): Reduced range of +o, +u, +v and +w. (mips_builtin_opcodes): Reduced element index range for sldi, splati, copy_s, copy_u, insert and insve instructions.
2013-11-192013-11-19 Catherine Moore <clm@codesourcery.com>Catherine Moore1-56/+57
* micromips-opc.c (LM): Define. (micromips_opcodes): Add LM to load instructions. * mips-opc.c (prefe): Add LM attribute.
2013-10-142013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>Chao-ying Fu1-0/+563
* micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. (MSA): New define. (MSA64): New define. (micromips_opcodes): Add MSA instructions. * mips-dis.c (msa_control_names): New array. (mips_abi_choice): Add ASE_MSA to mips32r2. Remove ASE_MDMX from mips64r2. Add ASE_MSA and ASE_MSA64 to mips64r2. (parse_mips_dis_option): Handle -Mmsa. (print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL. (print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX. (print_mips_disassembler_options): Print -Mmsa. * mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. (MSA): New define. (MSA64): New define. (mips_builtin_op): Add MSA instructions.
2013-10-072013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com>Chao-ying Fu1-4/+4
* micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
2013-08-23 opcodes/Maciej W. Rozycki1-3/+1
* micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps", replacing NODS. gas/testsuite/ * gas/testsuite/gas/mips/micromips-insn32.d: Adjust for delay slot scheduling of ALNV.PS. * gas/testsuite/gas/mips/micromips-noinsn32.d: Likewise. * gas/testsuite/gas/mips/micromips-trap.d: Likewise. * gas/testsuite/gas/mips/micromips.d: Likewise. * gas/testsuite/gas/mips/micromips@alnv_ps-swap.d: Likewise.
2013-08-19include/opcode/Richard Sandiford1-3/+5
* mips.h (M_DEXT, M_DINS): Delete. opcodes/ * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins" macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases. Use +H rather than +C for the real "dext". * mips-opc.c (mips_builtin_opcodes): Likewise. gas/ * config/tc-mips.c (report_bad_range, report_bad_field): Delete. (macro): Remove M_DEXT and M_DINS handling. gas/testsuite/ * gas/mips/ext-ill.l, gas/mips/mips64r2-ill.l: Expect DEXT and DINS error messages to have the same form as the EXT and INS ones. * gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d, gas/mips/micromips.d, gas/mips/micromips@mips64r2.d, gas/mips/mips64r2.d: Expect "dext" and "dins" instead of "dextm", "dextu", "dinsm" and "dinsu".
2013-08-19include/opcode/Richard Sandiford1-6/+6
* mips.h (OP_OPTIONAL_REG): New mips_operand_type. (mips_optional_operand_p): New function. opcodes/ * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros. * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG and OPTIONAL_MAPPED_REG. * mips-opc.c (decode_mips_operand): Likewise. * mips16-opc.c (decode_mips16_operand): Likewise. * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG. gas/ * config/tc-mips.c (operand_reg_mask, match_operand): Handle OP_OPTIONAL_REG. (mips_ip, mips16_ip): Use mips_optional_operand_p to check for optional operands.
2013-08-01opcodes/Richard Sandiford1-1/+0
* micromips-opc.c (WR_s): Delete.
2013-08-01include/opcode/Richard Sandiford1-735/+715
* mips.h (mips_decode_reg_operand): New function. (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL) (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4) (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI): New macros. (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D) (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T) (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S) (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z) (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D) (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD) (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG) (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP) (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP) (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other macros to cover the gaps. (INSN2_MOD_SP): Replace with... (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros. (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z) (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y) (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z) (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X): Delete. opcodes/ * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI): New macros. (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R) (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete. (mips_builtin_opcodes): Use the new position-based read-write flags instead of field-based ones. Use UDI for "udi..." instructions. * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): New macros. (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete. (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags. (WR_SP, RD_16): New macros. (RD_SP): Redefine as an INSN2_* flag. (MOD_SP): Redefine in terms of RD_SP and WR_SP. (mips16_opcodes): Use the new position-based read-write flags instead of field-based ones. Use RD_16 for "nop". Move RD_SP to pinfo2 field. * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): New macros. (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj) (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D) (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete. (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP. (micromips_opcodes): Use the new position-based read-write flags instead of field-based ones. * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand. (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead of field-based flags. gas/ * config/tc-mips.c (MAX_OPERANDS): New macro. (mips_operand_array): New structure. (mips_operands, mips16_operands, micromips_operands): New arrays. (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map) (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map) (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map) (micromips_to_32_reg_q_map): Delete. (insn_operands, insn_opno, insn_extract_operand): New functions. (validate_mips_insn): Take a mips_operand_array as argument and use it to build up a list of operands. Extend to handle INSN_MACRO and MIPS16. (validate_mips16_insn): New function. (validate_micromips_insn): Take a mips_operand_array as argument. Handle INSN_MACRO. (md_begin): Initialize mips_operands, mips16_operands and micromips_operands. Call validate_mips_insn and validate_micromips_insn for macro instructions too. Call validate_mips16_insn for MIPS16 instructions. (insn_read_mask, insn_write_mask, operand_reg_mask, insn_reg_mask): New functions. (gpr_read_mask, gpr_write_mask, fpr_read_mask, fpr_write_mask): Use them. Handle INSN_UDI. (get_append_method): Use gpr_read_mask.
2013-08-01opcodes/Richard Sandiford1-7/+7
* mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags for operands that are hard-coded to $0. * micromips-opc.c (micromips_opcodes): Likewise.
2013-08-01opcodes/Richard Sandiford1-4/+4
* mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d for the single-operand forms of JALR and JALR.HB. * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB and JALRS.HB.
2013-07-14opcodes/Richard Sandiford1-996/+996
* Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove special rules. * Makefile.in: Regenerate. * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize all fields. Reformat.
2013-07-14include/opcode/Richard Sandiford1-1/+148
* mips.h (mips_operand_type, mips_reg_operand_type): New enums. (mips_operand, mips_int_operand, mips_mapped_int_operand) (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand) (mips_pcrel_operand): New structures. (mips_insert_operand, mips_extract_operand, mips_signed_operand) (mips_decode_int_operand, mips_decode_pcrel_operand): New functions. (decode_mips_operand, decode_micromips_operand): Declare. opcodes/ * mips-formats.h: New file. * mips-opc.c: Include mips-formats.h. (reg_0_map): New static array. (decode_mips_operand): New function. * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h. (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map) (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map) (int_c_map): New static arrays. (decode_micromips_operand): New function. * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map) (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map) (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map) (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2) (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map) (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map) (micromips_imm_b_map, micromips_imm_c_map): Delete. (print_reg): New function. (mips_print_arg_state): New structure. (init_print_arg_state, print_insn_arg): New functions. (print_insn_args): Change interface and use mips_operand structures. Delete GET_OP_S. Move GET_OP definition to... (print_insn_mips): ...here. Update the call to print_insn_args. (print_insn_micromips): Use print_insn_args. gas/ * config/tc-mips.c (validate_mips_insn): Move further up file. Add insn_bits and decode_operand arguments. Use the mips_operand fields to work out which bits an operand occupies. Detect double definitions. (validate_micromips_insn): Move further up file. Call into validate_mips_insn.
2013-07-07include/opcode/Richard Sandiford1-67/+9
* mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB) (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB) (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A) (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB) (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB) (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB) (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB) (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB) (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A) (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A) (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB) (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete. (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A): Rename to... (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB) (M_USD_AB): ...these. opcodes/ * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD and SD A(B) macros up. * micromips-opc.c (micromips_opcodes): Likewise. gas/ * config/tc-mips.c (gprel16_reloc_p): New function. (macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are BFD_RELOC_UNUSED. (offset_high_part, small_offset_p): New functions. (nacro): Use them. Remove *_OB and *_DOB cases. For single- register load and store macros, handle the 16-bit offset case first. If a 16-bit offset is not suitable for the instruction we're generating, load it into the temporary register using ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the M_L_DAB code once the address has been constructed. For double load and store macros, again handle the 16-bit offset case first. If the second register cannot be accessed from the same high part as the first, load it into AT using ADDRESS_ADDI_INSN. Fix the handling of LD in cases where the first register is the same as the base. Also handle the case where the offset is not 16 bits and the second register cannot be accessed from the same high part as the first. For unaligned loads and stores, fuse the offbits == 12 and old "ab" handling. Apply this handling whenever the second offset needs a different high part from the first. Construct the offset using ADDRESS_ADDI_INSN where possible, for offbits == 16 as well as offbits == 12. Use offset_reloc when constructing the individual loads and stores. (mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc and offset_reloc before matching against a particular opcode. Handle elided 'A' constants. Allow 'A' constants to use relocation operators. gas/testsuite/ * gas/mips/ldstla-32.d: Avoid "lui at,0x0" sequences for truncated constants. * gas/mips/ldstla-32-shared.d: Likewise. * gas/mips/mcu.d: Use ADDIU in preference to LI+ADDU when adding 16-bit constants to the base. * gas/mips/micromips@mcu.d: Likewise. * gas/mips/micromips@cache.d: Likewise. * gas/mips/micromips@pref.d: Likewise. * gas/mips/micromips.d, gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d: Likewise. Allow the full 16-bit offset range to be used for SB, LB and LBU in USH and ULH sequences. Fix the expected output for LD and SD when the two LW and SW offsets need different high parts. * gas/mips/eva.s: Test PREFE with relocation operators. * gas/mips/eva.d: Use ADDIU in preference to LI+ADDU for 16-bit constants. Update after eva.s change. * gas/mips/micromips@eva.d: Likewise. * gas/mips/ld-reloc.s, gas/mips/ld-reloc.d, gas/mips/l_d-reloc.s, gas/mips/l_d-reloc.d, gas/mips/ulw-reloc.s, gas/mips/ulw-reloc.d, gas/mips/micromips@ulw-reloc.d, gas/mips/ulh-reloc.s, gas/mips/ulh-reloc.d: New tests. * gas/mips/mips.exp: Run them.
2013-07-07include/opcode/Richard Sandiford1-1/+1
* mips.h: Document "+i". opcodes/ * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for "jalx". * mips16-opc.c (mips16_opcodes): Likewise. * micromips-opc.c (micromips_opcodes): Likewise. * mips-dis.c (print_insn_args, print_mips16_insn_arg) (print_insn_mips16): Handle "+i". (print_insn_micromips): Likewise. Conditionally preserve the ISA bit for "a" but not for "+i". gas/ * config/tc-mips.c (validate_mips_insn, validate_micromips_insn): (mips_ip, mips16_ip): Handle "+i".
2013-07-07include/opcode/Richard Sandiford1-3/+3
* mips.h: Remove "mi" documentation. Update "mh" documentation. (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI): Delete. (INSN2_WRITE_GPR_MHI): Rename to... (INSN2_WRITE_GPR_MH): ...this. opcodes/ * micromips-opc.c (WR_mhi): Rename to.. (WR_mh): ...this. (micromips_opcodes): Update "movep" entry accordingly. Replace "mh,mi" with "mh". * mips-dis.c (micromips_to_32_reg_h_map): Rename to... (micromips_to_32_reg_h_map1): ...this. (micromips_to_32_reg_i_map): Rename to... (micromips_to_32_reg_h_map2): ...this. (print_micromips_insn): Remove "mi" case. Print both registers in the pair for "mh". gas/ * config/tc-mips.c (mips32_to_micromips_reg_h_map): Delete. (micromips_to_32_reg_h_map): Rename to... (micromips_to_32_reg_h_map1): ...this. (micromips_to_32_reg_i_map): Rename to... (micromips_to_32_reg_h_map2): ...this. (mips_lookup_reg_pair): New function. (gpr_write_mask, macro): Adjust after above renaming. (validate_micromips_insn): Remove "mi" handling. (mips_ip): Likewise. Parse both registers in a pair for "mh".
2013-07-07include/opcode/Richard Sandiford1-8/+0
* mips.h: Remove documentation of "+D" and "+T". opcodes/ * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries. * micromips-opc.c (micromips_opcodes): Likewise. * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D" and "+T" handling. Check for a "0" suffix when deciding whether to use coprocessor 0 names. In that case, also check for ",H" selectors. gas/ * config/tc-mips.c (validate_mips_insn, validate_micromips_insn) (mips_ip): Remove "+D" and "+T" handling. gas/testsuite/ * gas/mips/lb.d, gas/mips/sb.d: Use coprocessor register names for LWC0 and SWC0.
2013-06-25 bfd/Maciej W. Rozycki1-0/+9
* elfxx-mips.h (_bfd_mips_elf_insn32): New prototype. * elfxx-mips.c (mips_elf_link_hash_table): Add insn32 member. (STUB_MOVE32_MICROMIPS, STUB_JALR32_MICROMIPS): New macros. (MICROMIPS_INSN32_FUNCTION_STUB_NORMAL_SIZE): Likewise. (MICROMIPS_INSN32_FUNCTION_STUB_BIG_SIZE): Likewise. (micromips_insn32_o32_exec_plt0_entry): New variable. (micromips_insn32_o32_exec_plt_entry): Likewise. (_bfd_mips_elf_adjust_dynamic_symbol): Handle insn32 mode. (mips_elf_estimate_stub_size): Likewise. (_bfd_mips_elf_size_dynamic_sections): Likewise. (_bfd_mips_elf_finish_dynamic_symbol): Likewise. (mips_finish_exec_plt): Likewise. (_bfd_mips_elf_relax_section): Likewise. (_bfd_mips_elf_insn32): New function. (_bfd_mips_elf_get_synthetic_symtab): Handle insn32 PLT. gas/ * config/tc-mips.c (mips_set_options): Add insn32 member. (mips_opts): Initialize it. (NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode. (options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values. (md_longopts): Add "minsn32" and "mno-insn32" options. (is_size_valid): Handle insn32 mode. (md_assemble): Pass instruction string down to macro. (brk_fmt): Add second dimension and insn32 mode initializers. (mfhl_fmt): Likewise. (BRK_FMT, MFHL_FMT): Handle insn32 mode. (macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding. (macro_build_jalr, move_register): Handle insn32 mode. (macro_build_branch_rs): Likewise. (macro): Handle insn32 mode. <M_JRADDIUSP>, <M_JRC>, <M_MOVEP>: New cases. (mips_ip): Handle insn32 mode. (md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32. (s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops. (mips_handle_align): Handle insn32 mode. (md_show_usage): Add -minsn32 and -mno-insn32. * doc/as.texinfo (Target MIPS options): Add -minsn32 and -mno-insn32 options. (-minsn32, -mno-insn32): New options. * doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32 options. (MIPS assembly options): New node. Document .set insn32 and .set noinsn32. (MIPS-Dependent): List the new node. gas/testsuite/ * gas/mips/micromips-insn32.d: New test. * gas/mips/micromips-noinsn32.d: Likewise. * gas/mips/micromips.l: Rename to... * gas/mips/micromips-warn.l: ... this. * gas/mips/micromips.d: Update accordingly. * gas/mips/micromips-trap.d: Likewise. * gas/mips/micromips.l: New list test. * gas/mips/micromips.s: Add conditionals. * gas/mips/mips.exp: Run the new tests. include/opcode/ * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum values. ld/ * emultempl/mipself.em (insn32): New variable. (mips_create_output_section_statements): Handle insn32 mode. (PARSE_AND_LIST_PROLOGUE): New macro. (PARSE_AND_LIST_LONGOPTS): Likewise. (PARSE_AND_LIST_OPTIONS): Likewise. * gen-doc.texi: Set MIPS. * ld.texinfo: Likewise. (Options specific to MIPS targets): New section. (ld and MIPS family): New node. (Top, Machine Dependent): List the new node. opcodes/ * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc" and "movep" macros.
2013-06-172013-06-17 Catherine Moore <clm@codesourcery.com>Catherine Moore1-0/+57
Maciej W. Rozycki <macro@codesourcery.com> Chao-Ying Fu <fu@mips.com> gas/testsuite/ * gas/mips/mips.exp: Run new tests. * gas/mips/eva.d: New. * gas/mips/eva.s: New. * gas/mips/micromips@eva.d: New. gas/ * config/tc-mips.c (mips_set_options): Add ase_eva. (mips_set_options mips_opts): Add ase_eva. (file_ase_eva): Declare. (ISA_SUPPORTS_EVA_ASE): Define. (IS_SEXT_9BIT_NUM): Define. (MIPS_CPU_ASE_EVA): Define. (is_opcode_valid): Add support for ase_eva. (macro_build): Likewise. (macro): Likewise. (validate_mips_insn): Likewise. (validate_micromips_insn): Likewise. (mips_ip): Likewise. (options): Add OPTION_EVA and OPTION_NO_EVA. (md_longopts): Add -meva and -mno-eva. (md_parse_option): Process new options. (mips_after_parse_args): Check for valid EVA combinations. (s_mipsset): Likewise. include/ * opcode/mips.h (OP_SH_EVAOFFSET): Define. (OP_MASK_EVAOFFSET): Define. (INSN_ASE_MASK): Delete. (ASE_EVA): Define. (M_CACHEE_AB, M_CACHEE_OB): New. (M_LBE_OB, M_LBE_AB): New. (M_LBUE_OB, M_LBUE_AB): New. (M_LHE_OB, M_LHE_AB): New. (M_LHUE_OB, M_LHUE_AB): New. (M_LLE_AB, M_LLE_OB): New. (M_LWE_OB, M_LWE_AB): New. (M_LWLE_AB, M_LWLE_OB): New. (M_LWRE_AB, M_LWRE_OB): New. (M_PREFE_AB, M_PREFE_OB): New. (M_SCE_AB, M_SCE_OB): New. (M_SBE_OB, M_SBE_AB): New. (M_SHE_OB, M_SHE_AB): New. (M_SWE_OB, M_SWE_AB): New. (M_SWLE_AB, M_SWLE_OB): New. (M_SWRE_AB, M_SWRE_OB): New. (MICROMIPSOP_SH_EVAOFFSET): Define. (MICROMIPSOP_MASK_EVAOFFSET): Define. opcodes/ * micromips-opc.c (EVA): Define. (TLBINV): Define. (micromips_opcodes): Add EVA opcodes. * mips-dis.c (mips_arch_choices): Update for ASE_EVA. (print_insn_args): Handle EVA offsets. (print_insn_micromips): Likewise. * mips-opc.c (EVA): Define. (TLBINV): Define. (mips_builtin_opcodes): Add EVA opcodes.
2013-06-132013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>Chao-ying Fu1-0/+24
* micromips-opc.c (IVIRT): New define. (IVIRT64): New define. (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0, tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions. * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0, dmtgc0 to print cp0 names.
2013-06-08gas/Richard Sandiford1-173/+173
2013-06-08 Catherine Moore <clm@codesourcery.com> * config/tc-mips.c (is_opcode_valid): Build ASE mask. (is_opcode_valid_16): Pass ase value to opcode_is_member. (append_insn): Change INSN_xxxx to ASE_xxxx. include/ 2013-06-08 Catherine Moore <clm@codesourcery.com> * opcode/mips.h (mips_opcode): Add ase field. (INSN_ASE_MASK): Delete. (INSN_DSP): Rename to ASE_DSP. Provide new value. (INSN_DSPR2): Rename to ASE_DSPR2. Provide new value. (INSN_MCU): Rename to ASE_MCU. Provide new value. (INSN_MDMX): Rename to ASE_MDMX. Provide new value. (INSN_MIPS3d): Rename to ASE_MIPS3D. Provide new value. (INSN_MT): Rename to ASE_MT. Provide new value. (INSN_SMARTMIPS): Rename to ASE_SMARTMIPS. Provide new value. (INSN_VIRT): Rename to ASE_VIRT. Provide new value. (INSN_VIRT64): Rename to ASE_VIRT64. Provide new value. (opcode_is_member): Add ase argument. Check ase. opcodes/ 2013-06-08 Catherine Moore <clm@codesourcery.com> Richard Sandiford <rdsandiford@googlemail.com> * micromips-opc.c (D32, D33, MC): Update definitions. (micromips_opcodes): Initialize ase field. * mips-dis.c (mips_arch_choice): Add ase field. (mips_arch_choices): Initialize ase field. (set_default_mips_dis_options): Declare and setup mips_ase. * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64, MT32, MC): Update definitions. (mips_builtin_opcodes): Initialize ase field.
2012-09-18 opcodes/Maciej W. Rozycki1-1/+1
* micromips-opc.c (micromips_opcodes): Correct the encoding of the "swxc1" instruction. gas/testsuite/ * gas/mips/micromips.d: Correct the disassembly of SWXC1. * gas/mips/micromips-trap.d: Likewise. * gas/mips/micromips@24k-triple-stores-1.d: Likewise. * gas/mips/micromips@mips4-fp.d: Likewise.
2012-08-13 include/opcode/Maciej W. Rozycki1-1/+1
* mips.h (mips_opcode): Add the exclusions field. (OPCODE_IS_MEMBER): Remove macro. (cpu_is_member): New inline function. (opcode_is_member): Likewise. opcodes/ * micromips-opc.c (micromips_opcodes): Update comment. * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor instructions for IOCT as appropriate. * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with opcode_is_member. * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with the result of a check for the -Wno-missing-field-initializers GCC option. * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable. (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to compilation. (mips16-opc.lo): Likewise. (micromips-opc.lo): Likewise. * aclocal.m4: Regenerate. * configure: Regenerate. * Makefile.in: Regenerate. gas/ * config/tc-mips.c (NO_ISA_COP, COP_INSN): Remove macros. (is_opcode_valid): Remove coprocessor instruction exclusions. Replace OPCODE_IS_MEMBER with opcode_is_member. (is_opcode_valid_16): Replace OPCODE_IS_MEMBER with opcode_is_member. (macro): Remove coprocessor instruction exclusions.
2012-07-31 include/opcode/Maciej W. Rozycki1-0/+172
* mips.h: Document microMIPS DSP ASE usage. (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for microMIPS DSP ASE support. (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise. (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise. (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise. (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise. (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise. (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise. (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise. gas/ * config/tc-mips.c (macro_build) <'2'>: Handle microMIPS. (macro) <M_BALIGN>: Update error handling. (validate_micromips_insn) <'2', '3', '4', '5', '6'>: New cases. <'7', '8', '0', '@', '^'>: Likewise. (mips_ip) <'2', '3', '4', '5', '6', '7', '8'>: Handle microMIPS. <'9'>: Fix formatting. <'0', '@'>: Handle microMIPS. <'^'>: New case. gas/testsuite/ * gas/mips/micromips@mips32-dsp.d: New. * gas/mips/micromips@mips32-dspr2.d: New. * gas/mips/mips32-dsp.d: Remove -mips32r2. * gas/mips/mips32-dspr2.d: Likewise. * gas/mips/mips.exp: (mips_create_arch): Use -mips64r2 for micromips. Use run_dump_test_arches to run dsp tests. opcodes/ * micromips-opc.c (WR_a, RD_a, MOD_a): New macros. (DSP_VOLA): Likewise. (D32, D33): Likewise. (micromips_opcodes): Add DSP ASE instructions. * micromips-dis.c (print_insn_micromips) <'2', '3'>: New cases. <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
2012-05-17 PR 14072Nick Clifton1-2/+2
* configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * sysdep.h: Generate an error if included before config.h. * alpha-opc.c: Include sysdep.h before any other header file. * alpha-dis.c: Likewise. * avr-dis.c: Likewise. * cgen-opc.c: Likewise. * cr16-dis.c: Likewise. * cris-dis.c: Likewise. * crx-dis.c: Likewise. * d10v-dis.c: Likewise. * d10v-opc.c: Likewise. * d30v-dis.c: Likewise. * d30v-opc.c: Likewise. * h8500-dis.c: Likewise. * i370-dis.c: Likewise. * i370-opc.c: Likewise. * m10200-dis.c: Likewise. * m10300-dis.c: Likewise. * micromips-opc.c: Likewise. * mips-opc.c: Likewise. * mips61-opc.c: Likewise. * moxie-dis.c: Likewise. * or32-opc.c: Likewise. * pj-dis.c: Likewise. * ppc-dis.c: Likewise. * ppc-opc.c: Likewise. * s390-dis.c: Likewise. * sh-dis.c: Likewise. * sh64-dis.c: Likewise. * sparc-dis.c: Likewise. * sparc-opc.c: Likewise. * spu-dis.c: Likewise. * tic30-dis.c: Likewise. * tic54x-dis.c: Likewise. * tic80-dis.c: Likewise. * tic80-opc.c: Likewise. * tilegx-dis.c: Likewise. * tilepro-dis.c: Likewise. * v850-dis.c: Likewise. * v850-opc.c: Likewise. * vax-dis.c: Likewise. * w65-dis.c: Likewise. * xgate-dis.c: Likewise. * xtensa-dis.c: Likewise. * rl78-decode.opc: Likewise. * rl78-decode.c: Regenerate. * rx-decode.opc: Likewise. * rx-decode.c: Regenerate. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * sysdep.h: Generate an error if included before config.h. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * aclocal.m4: Regenerate. * bfd-in.h: Generate an error if included before config.h. * sysdep.h: Likewise. * bfd-in2.h: Regenerate. * compress.c: Remove #include "config.h". * plugin.c: Likewise. * elf32-m68hc1x.c: Include sysdep.h before alloca-conf.h. * elf64-hppa.c: Likewise. * som.c: Likewise. * xsymc.c: Likewise. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * aclocal.m4: Regenerate. * Makefile.am: Use wrappers around C files generated by flex. * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. * itbl-lex-wrapper.c: New file. * config/bfin-lex-wrapper.c: New file. * cgen.c: Include as.h before setjmp.h. * config/tc-dlx.c: Include as.h before any other header. * config/tc-h8300.c: Likewise. * config/tc-lm32.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mmix.c: Likewise. * config/tc-msp430.c: Likewise. * config/tc-or32.c: Likewise. * config/tc-tic4x.c: Likewise. * config/tc-tic54x.c: Likewise. * config/tc-xtensa.c: Likewise. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * unwind-ia64.h: Include config.h.
2011-11-16 * micromips-opc.c (micromips_opcodes): Use NODS rather than TRAPMaciej W. Rozycki1-2/+2
for "alnv.ps".
2011-08-09 gas/Maciej W. Rozycki1-0/+10
* config/tc-mips.c (mips_set_options): Add ase_mcu. (mips_opts): Initialise ase_mcu to -1. (ISA_SUPPORTS_MCU_ASE): New macro. (MIPS_CPU_ASE_MCU): Likewise. (is_opcode_valid): Handle MCU. (macro_build, macro): Likewise. (validate_mips_insn, validate_micromips_insn): Likewise. (mips_ip): Likewise. (options): Add OPTION_MCU and OPTION_NO_MCU. (md_longopts): Add mmcu and mno-mcu. (md_parse_option): Handle OPTION_MCU and OPTION_NO_MCU. (mips_after_parse_args): Handle MCU. (s_mipsset): Likewise. (md_show_usage): Handle MCU options. * doc/as.texinfo: Document -mmcu and -mno-mcu options. * doc/c-mips.texi: Likewise, and document ".set mcu" and ".set nomcu" directives. gas/testsuite/ * gas/mips/micromips@mcu.d: New test. * gas/mips/mcu.d: Likewise. * gas/mips/mcu.s: New test source. * gas/mips/mips.exp: Run the new tests. include/opcode/ * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros. (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine. (INSN_ASE_MASK): Add the MCU bit. (INSN_MCU): New macro. (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values. (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros. opcodes/ * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2" and "mips64r2". (print_insn_args, print_insn_micromips): Handle MCU. * micromips-opc.c (MC): New macro. (micromips_opcodes): Add "aclr", "aset" and "iret". * mips-opc.c (MC): New macro. (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
2011-08-09 include/opcode/Maciej W. Rozycki1-82/+86
* mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros. (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise. (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise. (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise. (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise. (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise. (INSN2_READ_GPR_MMN): Likewise. (INSN2_READ_FPR_D): Change the bit used. (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise. (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise. (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise. (INSN2_COND_BRANCH): Likewise. (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros. (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise. (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise. (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise. (INSN2_MOD_GPR_MN): Likewise. gas/ * config/tc-mips.c (gpr_mod_mask): Remove INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG, INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN, INSN2_MOD_GPR_MP and INSN2_MOD_GPR_MQ opcode register use checks. (gpr_read_mask): Add INSN2_READ_GPR_MC, INSN2_READ_GPR_ME INSN2_READ_GPR_MG, INSN2_READ_GPR_MJ, INSN2_READ_GPR_MMN, INSN2_READ_GPR_MP and INSN2_READ_GPR_MQ opcode register use checks. (gpr_write_mask): Replace INSN2_WRITE_GPR_S opcode register use flag with INSN_WRITE_GPR_S. Add INSN2_WRITE_GPR_MB, INSN2_WRITE_GPR_MHI, INSN2_WRITE_GPR_MJ and INSN2_WRITE_GPR_MP opcode register use checks. (can_swap_branch_p): Enable microMIPS branch swapping. (append_insn): Likewise. gas/testsuite/ * gas/mips/micromips.d: Update according to changes to enable microMIPS branch swapping. * gas/mips/micromips-trap.d: Likewise. * gas/mips/micromips@jal-svr4pic.d: Likewise. * gas/mips/micromips@loc-swap.d: Likewise. * gas/mips/micromips@loc-swap-dis.d: Likewise. opcodes/ * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros. (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise. (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise. (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros. (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise. (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise. (WR_s): Update macro. (micromips_opcodes): Update register use flags of: "addiu", "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu", "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j", "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li", "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not", "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw", "swm" and "xor" instructions.
generated by cgit v1.1 at 2025-01-09 05:38:09 +0000