aboutsummaryrefslogtreecommitdiff
path: root/opcodes/i386-tbl.h
AgeCommit message (Collapse)AuthorFilesLines
2019-11-14x86: drop redundant SYSCALL/SYSRET templatesJan Beulich1-24/+0
The Cpu64 forms are no different in their attributes except for the CPU flags; there's no need to key these off of anything other than CpuSYSCALL even for the 64-bit forms. Dropping these improves the diagnostic on SYSRETQ used in 32-bit code from "unsupported instruction `sysret'" to "invalid instruction suffix for `sysret'".
2019-11-14x86: fold individual Jump* attributes into a single Jump oneJan Beulich1-14843/+10922
..., taking just 3 bits instead of 5. No two of them are used together.
2019-11-14x86: make JumpAbsolute an insn attributeJan Beulich1-26403/+26403
... instead of an operand one: There's only ever one operand here anyway.
2019-11-14x86: make AnySize an insn attributeJan Beulich1-14458/+14458
... instead of an operand one. Which operand it applies to can be determined from other operand properties, but as it turns out the only place it is actually used at doesn't even need further qualification.
2019-11-12x86: fold EsSeg into IsStringJan Beulich1-11187/+11187
EsSeg (a per-operand bit) is used with IsString (a per-insn attribute) only. Extend the attribute to 2 bits, thus allowing to encode - not a string insn, - string insn with neither operand requiring use of %es:, - string insn with 1st operand requiring use of %es:, - string insn with 2nd operand requiring use of %es:, which covers all possible cases, allowing to drop EsSeg. The (transient) need to comment out the OTUnused #define did uncover an oversight in the earlier OTMax -> OTNum conversion, which is being taken care of here.
2019-11-12x86: eliminate ImmExt abuseJan Beulich1-65/+145
Drop the remaining instances left in place by commit c3949f432f ("x86: limit ImmExt abuse), now that we have a way to specify specific GPRs. Take the opportunity and also introduce proper 16-bit forms of applicable SVME insns as well as 1-operand forms of CLZERO.
2019-11-12x86: introduce operand type "instance"Jan Beulich1-14078/+14078
Special register "class" instances can't be combined with one another (neither in templates nor in register entries), and hence it is not a good use of resources (memory as well as execution time) to represent them as individual bits of a bit field. Furthermore the generalization becoming possible will allow improvements to the handling of insns accepting only individual registers as their operands.
2019-11-08i386: Only check suffix in instruction mnemonicH.J. Lu1-2/+2
We should check suffix in instruction mnemonic when matching instruction. In Intel syntax, normally we check for memory operand size. But the same mnemonic with 2 different encodings can have the same memory operand size and i.suffix is set to LONG_DOUBLE_MNEM_SUFFIX from memory operand size in Intel syntax to distinguish them. When there is no suffix in mnemonic, we check LONG_DOUBLE_MNEM_SUFFIX in i.suffix for mnemonic suffix. gas/ PR gas/25167 * config/tc-i386.c (match_template): Don't check instruction suffix set from operand. * testsuite/gas/i386/code16.d: New file. * testsuite/gas/i386/code16.s: Likewise. * testsuite/gas/i386/i386.exp: Run code16. * testsuite/gas/i386/x86-64-branch-4.l: Updated. opcodes/ PR gas/25167 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd. * i386-tbl.h: Regenerated.
2019-11-08x86: convert RegMask and RegBND from bitfield to enumeratorJan Beulich1-14449/+14449
This is to further shrink the operand type representation.
2019-11-08x86: convert RegSIMD and RegMMX from bitfield to enumeratorJan Beulich1-18968/+18968
This is to further shrink the operand type representation.
2019-11-08x86: convert Control/Debug/Test from bitfield to enumeratorJan Beulich1-13847/+13847
This is to further shrink the operand type representation.
2019-11-08x86: convert SReg from bitfield to enumeratorJan Beulich1-13720/+13720
This is to further shrink the operand type representation.
2019-11-07x86: support further AMD Zen2 instructionsJan Beulich1-3913/+3939
Both RDPRU and MCOMMIT have been publicly documented meanwhile: https://www.amd.com/system/files/TechDocs/24594.pdf.
2019-11-07x86/Intel: drop IgnoreSize from operand-less MOVSD/CMPSD againJan Beulich1-2/+2
These were mistakenly added by d241b91073 ("x86/Intel: correct MOVSD and CMPSD handling"). This addresses part of PR/gas 25167.
2019-10-30x86: slightly rearrange struct insn_templateJan Beulich1-3912/+3912
This avoids holes between the individual fields, (potentially) shrinking the overall template table size by 4 bytes per entry.
2019-10-30x86: drop stray WJan Beulich1-12/+12
The flag is used to indicate opcodes which can be switched between byte and word/dword/qword forms (in a "canonical" way). Obviously it's quite odd then to see it on insns not allowing for byte operands in the first place. As a result the opcode bytes need to be adjusted accordingly, which includes comparisons done in optimize_encoding(). To make re-introduction of such issues less likely have i386-gen diagnose it (in a generally non-fatal way for now).
2019-10-07x86/Intel: correct MOVSD and CMPSD handlingJan Beulich1-8/+8
First and foremost the EsSeg attribute was misplaced for CMPSD. Then both it and MOVSD were lacking Dword on both of their operands. Finally string insns with multiple operands and requiring use of ES: had the wrong operand number reported in the diagnostic.
2019-09-20x86-64: fix handling of PUSH/POP of segment registerJan Beulich1-2/+28
Commit 21df382b91 ("x86: fold SReg{2,3}") went too far: Folding 64-bit PUSH/POP templates into non-64-bit ones isn't correct, due to the different operand widths, and hence suffixes permitted. Restore the separate templates. Add tests of PUSH/POP with q suffix and %fs/%gs operands to the testsuite. While doing so also add PUSHF/POPF ones _without_ suffix.
2019-08-07x86: drop stray FloatMFJan Beulich1-7/+7
The flag is supposed to be used in templates which allow for both a "short" and a "long" format memory operand. Drop it from templates not matching this pattern. In the control/status word cases it was (ab)used in place of the intended IgnoreSize.
2019-07-16x86: make RegMem an opcode modifierJan Beulich1-16396/+20307
... instead of an operand type bit: It's an insn property, not an operand one. There's just one actual change to be made to the templates: Most are now required to have the (unswapped) destination go into ModR/M.rm, so VMOVD template needs its opcode adjusted accordingly and its operands swapped. {,V}MOVS{S,D}, otoh, are left alone in this regard, as otherwise generated code would differ from what we've been producing so far (which I don't think is wanted). Take the opportunity and add a missing IgnoreSize to pextrb (leading to an error in 16-bit mode), and take the liberty to once again drop stray IgnoreSize attributes from lines changed and neighboring related ones.
2019-07-16x86: fold SReg{2,3}Jan Beulich1-23782/+13834
They're the only exception to there generally being no mix of register kinds possible in an insn operand template, and there being two bits per operand for their representation is also quite wasteful, considering the low number of uses. Fold both bits and deal with the little bit of fallout. Also take the liberty and drop dead code trying to set REX_B: No segment register has RegRex set on it. Additionally I was quite surprised that PUSH/POP with the permitted segment registers is not covered by the test cases. Add the missing pieces.
2019-07-01x86: drop Vec_Imm4Jan Beulich1-9919/+9919
It is pretty wasteful to have a per-operand flag which is used in exactly 4 cases. It can be relatively easily replaced, and by doing so I've actually found some dead code to remove at the same time (there's no case of ImmExt set at the same time as Vec_Imm4).
2019-07-01x86: limit ImmExt abuseJan Beulich1-84/+84
In quite a few cases ImmExt gets used when there's not really any immediate, but rather a degenerate ModR/M byte. ENCL{S,U} show how this case is supposed to be dealt with. Eliminate most abuses, leaving in place (for now) only ones where process_immext() is involved.
2019-07-01x86: optimize AND/OR with twice the same registerJan Beulich1-2/+2
It seems to be not uncommon for people to use AND or OR in this form for just setting the status flags. TEST, which doesn't write to any register other than EFLAGS, ought to be preferred. Make the change only for -O2 and above though, at least for now.
2019-07-01x86-64: optimize certain commutative VEX-encoded insnsJan Beulich1-167/+167
When they're in the 0F opcode space, swapping their source operands may allow switching from 3-byte to 2-byte VEX prefix encoding. Note that NaN behavior precludes us doing so for many packed and scalar floating point insns; such an optimization would need to be done by the compiler instead in this case, when it knows that NaN-s have undefined behavior anyway. While for explicitly specified AVX/AVX2 insns the optimization (for now at least) gets done only for -O2 and -Os, it is utilized by default in SSE2AVX mode, as there we're re-writing the programmer's specified insns anyway. Rather than introducing a new attribute flag, the change re-uses one which so far was meaningful only for EVEX-encoded insns.
2019-07-01x86: optimize EVEX packed integer logical instructionsJan Beulich1-4/+4
As long as there's no write mask as well as no broadcast, and as long as the scaled Disp8 wouldn't result in a shorter EVEX encoding, encode VPAND{D,Q}, VPANDN{D,Q}, VPOR{D,Q}, and VPXOR{D,Q} acting on only the lower 16 XMM/YMM registers using their VEX equivalents with -O1. Also take the opportunity and avoid looping twice over all operands when dealing with memory-with-displacement ones.
2019-07-01x86: add missing pseudo ops for VPCLMULQDQ ISA extensionJan Beulich1-0/+152
While the ISA extensions doc suggests them to be made available just like the SDM does for the PCLMULQDQ ISA extension, these weren't added when supposrt for the new extension was introduced. Also make sure the 64-bit non-AVX512 test actually tests VEX encodings, not EVEX ones.
2019-07-01x86: drop bogus Disp8MemShift attributesJan Beulich1-3/+3
In commit dc821c5f9a ("x86: replace Reg8, Reg16, Reg32, and Reg64") I apparently blindly copied the original register/memory templates into separate ones, in particular without removing the Disp8MemShift which are applicable to templates with memory operands only.
2019-06-25x86: fix (dis)assembly of certain SSE2 insns in 16-bit modeJan Beulich1-1/+1
MOVNTI was wrongly assembled with a 66h prefix. Add IgnoreSize to address this. It and the scalar to/from integer conversion insns also were also wrongly using Ev / Gv, leading to 16-bit register names being printed when 32-bit ones were meant. Clone the 32-bit SSE2 test to cover both assembler and disassembler.
2019-06-25x86-64: also optimize ANDQ with immediate fitting in 7 bitsJan Beulich1-1/+1
The same reasoning applies here as did/does for immediates fitting in 31 bits.
2019-06-04Enable Intel AVX512_VP2INTERSECT insnH.J. Lu1-3956/+3994
This patch enables support for VP2INTERSECT in binutils. Please refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf for VP2INTERSECT details. Make check-gas is ok. gas/ 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_vp2intersect. (cpu_noarch): Likewise. * doc/c-i386.texi: Document avx512_vp2intersect. * testsuite/gas/i386/i386.exp: Run vp2intersect tests. * testsuite/gas/i386/vp2intersect-intel.d: New test. * testsuite/gas/i386/vp2intersect.d: Likewise. * testsuite/gas/i386/vp2intersect.s: Likewise. * testsuite/gas/i386/vp2intersect-inval-bcast.l: Likewise. * testsuite/gas/i386/vp2intersect-inval-bcast.s: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-intel.d: Likewise. * testsuite/gas/i386/x86-64-vp2intersect.d: Likewise. * testsuite/gas/i386/x86-64-vp2intersect.s: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.l: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.s: Likewise. opcodes/ 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3. * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT instructions. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS, CPU_ANY_AVX512_VP2INTERSECT_FLAGS. (cpu_flags): Add CpuAVX512_VP2INTERSECT. * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT. (i386_cpu_flags): Add cpuavx512_vp2intersect. * i386-opc.tbl: Add AVX512_VP2INTERSECT insns. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2019-06-04Add support for Intel ENQCMD[S] instructionsH.J. Lu1-3901/+3965
This patch enables support for ENQCMD[S] in binutils. Please refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf for ENQCMD[S] details. Make check-gas is ok. gas/ChangeLog: 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com> Lili Cui <lili.cui@intel.com> * doc/c-i386.texi: Document enqcmd. * testsuite/gas/i386/enqcmd-intel.d: New file. * testsuite/gas/i386/enqcmd-inval.l: Likewise. * testsuite/gas/i386/enqcmd-inval.s: Likewise. * testsuite/gas/i386/enqcmd.d: Likewise. * testsuite/gas/i386/enqcmd.s: Likewise. * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise. * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise. * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd.s: Likewise. * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval, enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval, and x86-64-enqcmd. opcodes/ChangeLog: 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (enum): Add MOD_0F38F8_PREFIX_1 and MOD_0F38F8_PREFIX_3. (prefix_table): New instructions (see prefix above). (mod_table): New instructions (see prefix above). * i386-gen.c (cpu_flag_init): Add entries for enqcmd. (cpu_flags): Add a bitfield for enqmcd. * i386-init.h: Regenerated. * i386-opc.h (enum): Add CpuENQCMD. (i386_cpu_flags): Add a bitfield for cpuenqcmd. * i386-opc.tbl: Add enqcmd and enqcmds instructions. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.
2019-05-28x86: Add CheckRegSize to AVX512_BF16 instructions with Disp8ShiftVLH.J. Lu1-2/+2
For AVX512 instructions with Disp8ShiftVL and Broadcast, we may need to add CheckRegSize to check if broadcast matches the destination register size. gas/ PR gas/24625 * testsuite/gas/i386/inval-avx512f.s: Add tests for AVX512_BF16 instructions with invalid broadcast. * testsuite/gas/i386/x86-64-inval-avx512f.s: Likewise. * testsuite/gas/i386/inval-avx512f.l: Updated. * testsuite/gas/i386/x86-64-inval-avx512f.l: Likewise. opcodes/ PR gas/24625 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with Disp8ShiftVL. * i386-tbl.h: Regenerated.
2019-04-08x86: Consolidate AVX512 BF16 entries in i386-opc.tblH.J. Lu1-260/+22
1. Use single entry for vcvtne2ps2bf16 and vdpbf16ps with Disp8ShiftVL. 2. Use 5 entries, instead of 8, for vcvtneps2bf16. * i386-opc.tbl: Consolidate AVX512 BF16 entries. * i386-init.h: Regenerated.
2019-04-05x86: Support Intel AVX512 BF16Xuepeng Guo1-3949/+4305
Add assembler and disassembler support Intel AVX512 BF16: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference gas/ 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_bf16. (cpu_noarch): Add noavx512_bf16. * doc/c-i386.texi: Document avx512_bf16. * testsuite/gas/i386/avx512_bf16.d: New file. * testsuite/gas/i386/avx512_bf16.s: Likewise. * testsuite/gas/i386/avx512_bf16_vl-inval.l: Likewise. * testsuite/gas/i386/avx512_bf16_vl-inval.s: Likewise. * testsuite/gas/i386/avx512_bf16_vl.d: Likewise. * testsuite/gas/i386/avx512_bf16_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16.d: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l: Likesie. * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Likewise. * testsuite/gas/i386/i386.exp: Add BF16 related tests. opcodes/ 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> * i386-dis-evex.h (evex_table): Updated to support BF16 instructions. * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1 and EVEX_W_0F3872_P_3. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS. (cpu_flags): Add bitfield for CpuAVX512_BF16. * i386-opc.h (enum): Add CpuAVX512_BF16. (i386_cpu_flags): Add bitfield for cpuavx512_bf16. * i386-opc.tbl: Add AVX512 BF16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2019-03-18x86: Optimize EVEX vector load/store instructionsH.J. Lu1-6/+6
When there is no write mask, we can encode lower 16 128-bit/256-bit EVEX vector register load and store instructions as VEX vector register load and store instructions with -O1. gas/ PR gas/24348 * config/tc-i386.c (optimize_encoding): Encode 128-bit and 256-bit EVEX vector register load/store instructions as VEX vector register load/store instructions for -O1. * doc/c-i386.texi: Update -O1 documentation. * testsuite/gas/i386/i386.exp: Run PR gas/24348 tests. * testsuite/gas/i386/optimize-1.s: Add tests for EVEX vector load/store instructions. * testsuite/gas/i386/optimize-2.s: Likewise. * testsuite/gas/i386/optimize-3.s: Likewise. * testsuite/gas/i386/optimize-5.s: Likewise. * testsuite/gas/i386/x86-64-optimize-2.s: Likewise. * testsuite/gas/i386/x86-64-optimize-3.s: Likewise. * testsuite/gas/i386/x86-64-optimize-4.s: Likewise. * testsuite/gas/i386/x86-64-optimize-5.s: Likewise. * testsuite/gas/i386/x86-64-optimize-6.s: Likewise. * testsuite/gas/i386/optimize-1.d: Updated. * testsuite/gas/i386/optimize-2.d: Likewise. * testsuite/gas/i386/optimize-3.d: Likewise. * testsuite/gas/i386/optimize-4.d: Likewise. * testsuite/gas/i386/optimize-5.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2.d: Likewise. * testsuite/gas/i386/x86-64-optimize-3.d: Likewise. * testsuite/gas/i386/x86-64-optimize-4.d: Likewise. * testsuite/gas/i386/x86-64-optimize-5.d: Likewise. * testsuite/gas/i386/x86-64-optimize-6.d: Likewise. * testsuite/gas/i386/optimize-7.d: New file. * testsuite/gas/i386/optimize-7.s: Likewise. * testsuite/gas/i386/x86-64-optimize-8.d: Likewise. * testsuite/gas/i386/x86-64-optimize-8.s: Likewise. opcodes/ PR gas/24348 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32 and vmovdqu64. * i386-tbl.h: Regenerated.
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-11-06x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*Jan Beulich1-9/+9
PEXTR{B,W} and PINSR{B,W}, just like for AVX512BW, are WIG, no matter that the SDM uses a nonstandard description of that fact. PEXTRD, even with EVEX.W set, ignores that bit outside of 64-bit mode, just like its AVX counterpart.
2018-11-06x86: adjust {,E}VEX.W handling outside of 64-bit modeJan Beulich1-16/+16
Many VEX-/EVEX-encoded instructions accessing GPRs become WIG outside of 64-bit mode. The respective templates should specify neither VexWIG nor VexW0, but instead the setting of the bit should be determined from - REX.W in 64-bit mode, - the setting established through -mvexwig= / -mevexwig= otherwise. This implies that the evex-wig2 testcase needs to go away, as being wrong altogether. A few test additions desirable here will only happen in later patches, as the disassembler needs adjustments first. Once again SSE2AVX templates are left alone, for it being unclear what the behavior there should be.
2018-11-06x86: fix various non-LIG templatesJan Beulich1-43/+43
Quite a few templates were marked LIG while really the insns aren't. Introduce descriptive shorthands once again, instead of continuing to use the less legible original forms.
2018-11-06x86: allow {store} to select alternative {,}PEXTRW encodingJan Beulich1-4/+4
The 0F C5 encoding is indeed a load type one (just that memory operands are not permitted), while the 0F 3A 15 encoding is obviously a store. Allow the pseudo prefixes to be used to select between them. Also move (without any change) the secondary AVX512BW templates next to the primary one.
2018-11-06x86: add more VexWIGJan Beulich1-142/+142
Commits 6865c0435a ("x86: Support VEX/EVEX WIG encoding") and 6fa52824c3 ("x86: Replace VexW=3 with VexWIG") omitted quite a few templates, oddly enough in some cases despite testcases getting added (which then were recorded with wrong expected output). Also adjust VPMAXUB's attributes in the AVX512BW case to match ordering of that of neighboring templates. For the moment SSE2AVX templates are left alone, as it isn't clear whether they were intentionally left untouched by the original commits (the descriptions don't say either way). In this context I question the decision in commit 0375113302 ("x86: Add -mvexwig=[0|1] option to assembler") to move the logic to determine the value of the W bit ahead of the decision whether to use 2-byte VEX: While I can see this as one possible interpretation of -mvexwig=, the other alternative (setting the value of the bit only if it actually exists in the encoding) looks as reasonable to me, and perhaps even more in line with us generally trying to pick the shortest encoding.
2018-11-06x86: XOP VPHADD* / VPHSUB* are VEX.W0Jan Beulich1-15/+15
Also avoid introducing further uses of VexW=1, by introducing and using VexW0 at this occasion. Move the marker past all #define-s.
2018-10-10x86: fold Size{16,32,64} template attributesJan Beulich1-15568/+11674
Only one of them can be set at a time, which means they can be expressed by a single 2-bit field instead of three 1-bit ones.
2018-10-05x86: Add Intel ENCLV to assembler and disassemblerH.J. Lu1-0/+14
gas/ * testsuite/gas/i386/se1.s: Add enclv. * testsuite/gas/i386/x86-64-se1.s: Likewise. * testsuite/gas/i386/se1.d: Updated. * testsuite/gas/i386/x86-64-se1.d: Likewise. opcodes/ * i386-dis.c (rm_table): Add enclv. * i386-opc.tbl: Add enclv. * i386-tbl.h: Regenerated.
2018-09-17x86: Set EVex=2 on EVEX.128 only vmovd and vmovqH.J. Lu1-4/+4
EVEX "VMOVD xmm1, r32/m32", "VMOVD r32/m32, xmm2", "VMOVQ xmm1, r64/m64", "VMOVD r64/m64, xmm2", "VMOVQ xmm1, xmm2/m64" and "VMOVQ xmm1/m64, xmm2" can only be encoded with EVEX.128. Set EVex=2 on EVEX.128 only vmovd and vmovq. gas/ PR gas/23670 * testsuite/gas/i386/evex-lig-2.d: New file. * testsuite/gas/i386/evex-lig-2.s: Likewise. * testsuite/gas/i386/x86-64-evex-lig-2.d: Likewise. * testsuite/gas/i386/x86-64-evex-lig-2.s: Likewise. * testsuite/gas/i386/i386.exp: Run evex-lig-2 and x86-64-evex-lig-2. opcodes/ PR gas/23670 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2, EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2. (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry. (EVEX_LEN_0F7E_P_1): Likewise. (EVEX_LEN_0F7E_P_2): Likewise. (EVEX_LEN_0FD6_P_2): Likewise. * i386-dis.c (USE_EVEX_LEN_TABLE): New. (EVEX_LEN_TABLE): Likewise. (EVEX_LEN_0F6E_P_2): New enum. (EVEX_LEN_0F7E_P_1): Likewise. (EVEX_LEN_0F7E_P_2): Likewise. (EVEX_LEN_0FD6_P_2): Likewise. (evex_len_table): New. (get_valid_dis386): Handle USE_EVEX_LEN_TABLE. * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq. * i386-tbl.h: Regenerated.
2018-09-17x86: Set Vex=1 on VEX.128 only vmovd and vmovqH.J. Lu1-8/+8
AVX "VMOVD xmm1, r32/m32", "VMOVD r32/m32, xmm2", "VMOVQ xmm1, r64/m64" and "VMOVD r64/m64, xmm2" can only be encoded with VEX.128. Set Vex=1 on VEX.128 only vmovd and vmovq. gas/ PR gas/23665 * testsuite/gas/i386/avx-scalar.s: Remove vmovq and vmovd tests. * testsuite/gas/i386/x86-64-avx-scalar.s: Likewise. * testsuite/gas/i386/avx-scalar-intel.d: Updated. * testsuite/gas/i386/avx-scalar.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar.d: Likewise. * testsuite/gas/i386/i386.exp: Run avx-scalar2 and x86-64-avx-scalar2. * testsuite/gas/i386/avx-scalar-2.d: New file. * testsuite/gas/i386/avx-scalar-2.s: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-2.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-2.s: Likewise. opcodes/ PR gas/23665 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and VEX_LEN_0F7E_P_2 entries. * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq. * i386-tbl.h: Regenerated.
2018-09-15x86: Set VexW=3 on AVX vrsqrtssH.J. Lu1-1/+1
AVX vrsqrtss is a VEX WIG instruction. * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss. * i386-tbl.h: Regenerated.
2018-09-15x86: Set Vex=1 on VEX.128 only vmovqH.J. Lu1-2/+2
AVX "VMOVQ xmm1, xmm2/m64" and "VMOVQ xmm1/m64, xmm2" can only be encoded with VEX.128. Set Vex=1 on VEX.128 only vmovq and update assembler tests. gas/ PR gas/23665 * testsuite/gas/i386/avx-scalar-intel.d: Updated. * testsuite/gas/i386/avx-scalar.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar.d: Likewise. opcodes/ PR gas/23665 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and VEX_LEN_0FD6_P_2 entries. * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq. * i386-tbl.h: Regenerated.
2018-09-14x86: Support VEX/EVEX WIG encodingH.J. Lu1-465/+465
Add VEXWIG, defined as 3, to indicate that the VEX.W/EVEX.W bit is ignored by such VEX/EVEX instructions, aka WIG instructions. Set VexW=3 on VEX/EVEX WIG instructions. Update assembler to check VEXWIG when setting the VEX.W bit. gas/ PR gas/23642 * config/tc-i386.c (build_vex_prefix): Check VEXWIG when setting the VEX.W bit. (build_evex_prefix): Check VEXWIG when setting the EVEX.W bit. opcodes/ PR gas/23642 * i386-opc.h (VEXWIG): New. * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions. * i386-tbl.h: Regenerated.
generated by cgit v1.1 at 2024-11-22 03:39:57 +0000