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path: root/opcodes/i386-tbl.h
AgeCommit message (Expand)AuthorFilesLines
2018-09-13x86: drop bogus IgnoreSize from SSE4.2 insnsJan Beulich1-10/+10
2018-09-13x86: drop bogus IgnoreSize from SSE4.1 insnsJan Beulich1-63/+63
2018-09-13x86: drop bogus IgnoreSize from SSSE3 insnsJan Beulich1-32/+32
2018-09-13x86: drop bogus IgnoreSize from SSE3 insnsJan Beulich1-18/+18
2018-09-13x86: drop bogus IgnoreSize from SSE2 insnsJan Beulich1-208/+208
2018-09-13x86: drop bogus IgnoreSize from SSE insnsJan Beulich1-59/+59
2018-09-13x86: drop unnecessary {,No}Rex64Jan Beulich1-5/+5
2018-09-13x86: also allow D on 3-operand insnsJan Beulich1-88/+8
2018-09-13x86: use D attribute also for SIMD templatesJan Beulich1-1143/+89
2018-08-11x86: Add CpuCMOV and CpuFXSRH.J. Lu1-7522/+7522
2018-08-06x86: fold RegEip/RegRip and RegEiz/RegRizJan Beulich1-8/+8
2018-08-03x86: drop NoRex64 from {,v}pmov{s,z}x*Jan Beulich1-24/+24
2018-08-03x86: drop "mem" operand type attributeJan Beulich1-17927/+17927
2018-07-31x86: also optimize KXOR{D,Q} and KANDN{D,Q}Jan Beulich1-4/+4
2018-07-31x86: fold various AVX512 templates with so far differing Masking attributesJan Beulich1-1286/+222
2018-07-31x86/Intel: correct permitted operand sizes for AVX512 scatter/gatherJan Beulich1-64/+64
2018-07-31x86: drop CpuVREXJan Beulich1-4129/+4129
2018-07-25x86: Expand Broadcast to 3 bitsH.J. Lu1-393/+393
2018-07-24x86-64: correct AVX512F vcvtsi2s{d,s} handlingJan Beulich1-24/+24
2018-07-19x86: fold narrowing VCVT* templatesJan Beulich1-247/+77
2018-07-19x86: fold VFPCLASSP{D,S} templatesJan Beulich1-92/+12
2018-07-19x86: fold various AVX512* templatesJan Beulich1-1604/+174
2018-07-19x86: fold various AVX512DQ templatesJan Beulich1-823/+87
2018-07-19x86: fold various AVX512BW templatesJan Beulich1-4354/+440
2018-07-19x86: fold various AVX512CD templatesJan Beulich1-152/+16
2018-07-19x86: fold various AVX512VL templates into their AVX512F counterpartsJan Beulich1-13519/+1378
2018-07-18x86: Split vcvtps2{,u}qq and vcvttps2{,u}qqH.J. Lu1-8/+76
2018-07-11x86: adjust monitor/mwait templatesJan Beulich1-43/+46
2018-07-11x86/Intel: accept memory operand size specifiers for CET insnsJan Beulich1-4/+4
2018-06-01x86: fold MOV to/from segment register templatesJan Beulich1-109/+7
2018-06-01x86: don't emit REX.W for SLDT and STRJan Beulich1-2/+2
2018-06-01x86/Intel: accept "oword ptr" for INVPCIDJan Beulich1-4/+4
2018-05-07Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu1-4962/+5013
2018-04-27Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist1-15010/+14942
2018-04-26Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist1-14942/+15010
2018-04-26x86: fold various non-memory operand AVX512VL templatesJan Beulich1-1800/+416
2018-04-26x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMaskJan Beulich1-5039/+5039
2018-04-26x86: drop VexImmExtJan Beulich1-8001/+8001
2018-04-25x86: drop redundant AVX512VL shift templatesJan Beulich1-120/+0
2018-04-17Enable Intel CLDEMOTE instruction.Igor Tsimbalist1-5044/+5058
2018-04-15x86: Allow 32-bit registers for tpause and umwaitH.J. Lu1-32/+4
2018-04-11Enable Intel WAITPKG instructions.Igor Tsimbalist1-5040/+5124
2018-03-28x86: drop VecESizeJan Beulich1-7385/+7385
2018-03-28x86: convert broadcast insn attribute to booleanJan Beulich1-885/+885
2018-03-28x86: fold to-scalar-int conversion insnsJan Beulich1-444/+56
2018-03-22x86: drop pointless VecESizeJan Beulich1-475/+475
2018-03-22x86: fix swapped operand handling for BNDMOVJan Beulich1-2/+2
2018-03-22x86/Intel: fix fallout from earlier template foldingJan Beulich1-15/+100
2018-03-22x86: fold a few XOP templatesJan Beulich1-220/+36
2018-03-08x86-64: Also optimize "clr reg64"H.J. Lu1-1/+1
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