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2019-04-05x86: Support Intel AVX512 BF16Xuepeng Guo1-3949/+4305
Add assembler and disassembler support Intel AVX512 BF16: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference gas/ 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_bf16. (cpu_noarch): Add noavx512_bf16. * doc/c-i386.texi: Document avx512_bf16. * testsuite/gas/i386/avx512_bf16.d: New file. * testsuite/gas/i386/avx512_bf16.s: Likewise. * testsuite/gas/i386/avx512_bf16_vl-inval.l: Likewise. * testsuite/gas/i386/avx512_bf16_vl-inval.s: Likewise. * testsuite/gas/i386/avx512_bf16_vl.d: Likewise. * testsuite/gas/i386/avx512_bf16_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16.d: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l: Likesie. * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Likewise. * testsuite/gas/i386/i386.exp: Add BF16 related tests. opcodes/ 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> * i386-dis-evex.h (evex_table): Updated to support BF16 instructions. * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1 and EVEX_W_0F3872_P_3. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS. (cpu_flags): Add bitfield for CpuAVX512_BF16. * i386-opc.h (enum): Add CpuAVX512_BF16. (i386_cpu_flags): Add bitfield for cpuavx512_bf16. * i386-opc.tbl: Add AVX512 BF16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2019-03-18x86: Optimize EVEX vector load/store instructionsH.J. Lu1-6/+6
When there is no write mask, we can encode lower 16 128-bit/256-bit EVEX vector register load and store instructions as VEX vector register load and store instructions with -O1. gas/ PR gas/24348 * config/tc-i386.c (optimize_encoding): Encode 128-bit and 256-bit EVEX vector register load/store instructions as VEX vector register load/store instructions for -O1. * doc/c-i386.texi: Update -O1 documentation. * testsuite/gas/i386/i386.exp: Run PR gas/24348 tests. * testsuite/gas/i386/optimize-1.s: Add tests for EVEX vector load/store instructions. * testsuite/gas/i386/optimize-2.s: Likewise. * testsuite/gas/i386/optimize-3.s: Likewise. * testsuite/gas/i386/optimize-5.s: Likewise. * testsuite/gas/i386/x86-64-optimize-2.s: Likewise. * testsuite/gas/i386/x86-64-optimize-3.s: Likewise. * testsuite/gas/i386/x86-64-optimize-4.s: Likewise. * testsuite/gas/i386/x86-64-optimize-5.s: Likewise. * testsuite/gas/i386/x86-64-optimize-6.s: Likewise. * testsuite/gas/i386/optimize-1.d: Updated. * testsuite/gas/i386/optimize-2.d: Likewise. * testsuite/gas/i386/optimize-3.d: Likewise. * testsuite/gas/i386/optimize-4.d: Likewise. * testsuite/gas/i386/optimize-5.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2.d: Likewise. * testsuite/gas/i386/x86-64-optimize-3.d: Likewise. * testsuite/gas/i386/x86-64-optimize-4.d: Likewise. * testsuite/gas/i386/x86-64-optimize-5.d: Likewise. * testsuite/gas/i386/x86-64-optimize-6.d: Likewise. * testsuite/gas/i386/optimize-7.d: New file. * testsuite/gas/i386/optimize-7.s: Likewise. * testsuite/gas/i386/x86-64-optimize-8.d: Likewise. * testsuite/gas/i386/x86-64-optimize-8.s: Likewise. opcodes/ PR gas/24348 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32 and vmovdqu64. * i386-tbl.h: Regenerated.
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-11-06x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*Jan Beulich1-9/+9
PEXTR{B,W} and PINSR{B,W}, just like for AVX512BW, are WIG, no matter that the SDM uses a nonstandard description of that fact. PEXTRD, even with EVEX.W set, ignores that bit outside of 64-bit mode, just like its AVX counterpart.
2018-11-06x86: adjust {,E}VEX.W handling outside of 64-bit modeJan Beulich1-16/+16
Many VEX-/EVEX-encoded instructions accessing GPRs become WIG outside of 64-bit mode. The respective templates should specify neither VexWIG nor VexW0, but instead the setting of the bit should be determined from - REX.W in 64-bit mode, - the setting established through -mvexwig= / -mevexwig= otherwise. This implies that the evex-wig2 testcase needs to go away, as being wrong altogether. A few test additions desirable here will only happen in later patches, as the disassembler needs adjustments first. Once again SSE2AVX templates are left alone, for it being unclear what the behavior there should be.
2018-11-06x86: fix various non-LIG templatesJan Beulich1-43/+43
Quite a few templates were marked LIG while really the insns aren't. Introduce descriptive shorthands once again, instead of continuing to use the less legible original forms.
2018-11-06x86: allow {store} to select alternative {,}PEXTRW encodingJan Beulich1-4/+4
The 0F C5 encoding is indeed a load type one (just that memory operands are not permitted), while the 0F 3A 15 encoding is obviously a store. Allow the pseudo prefixes to be used to select between them. Also move (without any change) the secondary AVX512BW templates next to the primary one.
2018-11-06x86: add more VexWIGJan Beulich1-142/+142
Commits 6865c0435a ("x86: Support VEX/EVEX WIG encoding") and 6fa52824c3 ("x86: Replace VexW=3 with VexWIG") omitted quite a few templates, oddly enough in some cases despite testcases getting added (which then were recorded with wrong expected output). Also adjust VPMAXUB's attributes in the AVX512BW case to match ordering of that of neighboring templates. For the moment SSE2AVX templates are left alone, as it isn't clear whether they were intentionally left untouched by the original commits (the descriptions don't say either way). In this context I question the decision in commit 0375113302 ("x86: Add -mvexwig=[0|1] option to assembler") to move the logic to determine the value of the W bit ahead of the decision whether to use 2-byte VEX: While I can see this as one possible interpretation of -mvexwig=, the other alternative (setting the value of the bit only if it actually exists in the encoding) looks as reasonable to me, and perhaps even more in line with us generally trying to pick the shortest encoding.
2018-11-06x86: XOP VPHADD* / VPHSUB* are VEX.W0Jan Beulich1-15/+15
Also avoid introducing further uses of VexW=1, by introducing and using VexW0 at this occasion. Move the marker past all #define-s.
2018-10-10x86: fold Size{16,32,64} template attributesJan Beulich1-15568/+11674
Only one of them can be set at a time, which means they can be expressed by a single 2-bit field instead of three 1-bit ones.
2018-10-05x86: Add Intel ENCLV to assembler and disassemblerH.J. Lu1-0/+14
gas/ * testsuite/gas/i386/se1.s: Add enclv. * testsuite/gas/i386/x86-64-se1.s: Likewise. * testsuite/gas/i386/se1.d: Updated. * testsuite/gas/i386/x86-64-se1.d: Likewise. opcodes/ * i386-dis.c (rm_table): Add enclv. * i386-opc.tbl: Add enclv. * i386-tbl.h: Regenerated.
2018-09-17x86: Set EVex=2 on EVEX.128 only vmovd and vmovqH.J. Lu1-4/+4
EVEX "VMOVD xmm1, r32/m32", "VMOVD r32/m32, xmm2", "VMOVQ xmm1, r64/m64", "VMOVD r64/m64, xmm2", "VMOVQ xmm1, xmm2/m64" and "VMOVQ xmm1/m64, xmm2" can only be encoded with EVEX.128. Set EVex=2 on EVEX.128 only vmovd and vmovq. gas/ PR gas/23670 * testsuite/gas/i386/evex-lig-2.d: New file. * testsuite/gas/i386/evex-lig-2.s: Likewise. * testsuite/gas/i386/x86-64-evex-lig-2.d: Likewise. * testsuite/gas/i386/x86-64-evex-lig-2.s: Likewise. * testsuite/gas/i386/i386.exp: Run evex-lig-2 and x86-64-evex-lig-2. opcodes/ PR gas/23670 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2, EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2. (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry. (EVEX_LEN_0F7E_P_1): Likewise. (EVEX_LEN_0F7E_P_2): Likewise. (EVEX_LEN_0FD6_P_2): Likewise. * i386-dis.c (USE_EVEX_LEN_TABLE): New. (EVEX_LEN_TABLE): Likewise. (EVEX_LEN_0F6E_P_2): New enum. (EVEX_LEN_0F7E_P_1): Likewise. (EVEX_LEN_0F7E_P_2): Likewise. (EVEX_LEN_0FD6_P_2): Likewise. (evex_len_table): New. (get_valid_dis386): Handle USE_EVEX_LEN_TABLE. * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq. * i386-tbl.h: Regenerated.
2018-09-17x86: Set Vex=1 on VEX.128 only vmovd and vmovqH.J. Lu1-8/+8
AVX "VMOVD xmm1, r32/m32", "VMOVD r32/m32, xmm2", "VMOVQ xmm1, r64/m64" and "VMOVD r64/m64, xmm2" can only be encoded with VEX.128. Set Vex=1 on VEX.128 only vmovd and vmovq. gas/ PR gas/23665 * testsuite/gas/i386/avx-scalar.s: Remove vmovq and vmovd tests. * testsuite/gas/i386/x86-64-avx-scalar.s: Likewise. * testsuite/gas/i386/avx-scalar-intel.d: Updated. * testsuite/gas/i386/avx-scalar.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar.d: Likewise. * testsuite/gas/i386/i386.exp: Run avx-scalar2 and x86-64-avx-scalar2. * testsuite/gas/i386/avx-scalar-2.d: New file. * testsuite/gas/i386/avx-scalar-2.s: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-2.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-2.s: Likewise. opcodes/ PR gas/23665 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and VEX_LEN_0F7E_P_2 entries. * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq. * i386-tbl.h: Regenerated.
2018-09-15x86: Set VexW=3 on AVX vrsqrtssH.J. Lu1-1/+1
AVX vrsqrtss is a VEX WIG instruction. * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss. * i386-tbl.h: Regenerated.
2018-09-15x86: Set Vex=1 on VEX.128 only vmovqH.J. Lu1-2/+2
AVX "VMOVQ xmm1, xmm2/m64" and "VMOVQ xmm1/m64, xmm2" can only be encoded with VEX.128. Set Vex=1 on VEX.128 only vmovq and update assembler tests. gas/ PR gas/23665 * testsuite/gas/i386/avx-scalar-intel.d: Updated. * testsuite/gas/i386/avx-scalar.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar.d: Likewise. opcodes/ PR gas/23665 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and VEX_LEN_0FD6_P_2 entries. * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq. * i386-tbl.h: Regenerated.
2018-09-14x86: Support VEX/EVEX WIG encodingH.J. Lu1-465/+465
Add VEXWIG, defined as 3, to indicate that the VEX.W/EVEX.W bit is ignored by such VEX/EVEX instructions, aka WIG instructions. Set VexW=3 on VEX/EVEX WIG instructions. Update assembler to check VEXWIG when setting the VEX.W bit. gas/ PR gas/23642 * config/tc-i386.c (build_vex_prefix): Check VEXWIG when setting the VEX.W bit. (build_evex_prefix): Check VEXWIG when setting the EVEX.W bit. opcodes/ PR gas/23642 * i386-opc.h (VEXWIG): New. * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions. * i386-tbl.h: Regenerated.
2018-09-14x86: fold CRC32 templatesJan Beulich1-39/+5
Just like other insns having byte and word forms, these can also make use of the W modifier, which at the same time allows simplifying some other code a little bit.
2018-09-13x86: Remove VexW=1 from WIG VEX movq and vmovqH.J. Lu1-4/+4
Put back changes lost in commit 41d1ab6a6d96937fd0db04e53746f93f53687807.
2018-09-13i386: Update VexW field for VEX instructionsH.J. Lu1-18/+18
1. Mark VEX.W0 VEX instructions with VexW=1. 2. Mark VEX.W1 VEX instructions with VexW=2. 3. Remove VexW=1 from WIG VEX instructions. * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd, pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd. Add VexW=2 to VEX.W1 VEX movd, movq, pextrq, pinsrq, vmod, vmovq, vpextrq and vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq. * i386-tbl.h: Regenerated.
2018-09-13x86: drop bogus IgnoreSize from a few further insnsJan Beulich1-26/+26
2018-09-13x86: drop bogus IgnoreSize from AVX512_4* insnsJan Beulich1-6/+6
2018-09-13x86: drop bogus IgnoreSize from AVX512DQ insnsJan Beulich1-48/+48
2018-09-13x86: drop bogus IgnoreSize from AVX512BW insnsJan Beulich1-38/+38
2018-09-13x86: drop bogus IgnoreSize from AVX512VL insnsJan Beulich1-13/+13
2018-09-13x86: drop bogus IgnoreSize from AVX512ER insnsJan Beulich1-16/+16
2018-09-13x86: drop bogus IgnoreSize from AVX512F insnsJan Beulich1-371/+371
2018-09-13x86: drop bogus IgnoreSize from SHA insnsJan Beulich1-8/+8
2018-09-13x86: drop bogus IgnoreSize from XOP and SSE4a insnsJan Beulich1-133/+133
2018-09-13x86: drop bogus IgnoreSize from AVX2 insnsJan Beulich1-119/+119
2018-09-13x86: drop bogus IgnoreSize from AVX insnsJan Beulich1-128/+128
2018-09-13x86: drop bogus IgnoreSize from GNFI insnsJan Beulich1-6/+6
2018-09-13x86: drop bogus IgnoreSize from PCLMUL/VPCLMUL insnsJan Beulich1-16/+16
2018-09-13x86: drop bogus IgnoreSize from AES/VAES insnsJan Beulich1-22/+22
2018-09-13x86: drop bogus IgnoreSize from SSE4.2 insnsJan Beulich1-10/+10
2018-09-13x86: drop bogus IgnoreSize from SSE4.1 insnsJan Beulich1-63/+63
2018-09-13x86: drop bogus IgnoreSize from SSSE3 insnsJan Beulich1-32/+32
2018-09-13x86: drop bogus IgnoreSize from SSE3 insnsJan Beulich1-18/+18
2018-09-13x86: drop bogus IgnoreSize from SSE2 insnsJan Beulich1-208/+208
2018-09-13x86: drop bogus IgnoreSize from SSE insnsJan Beulich1-59/+59
2018-09-13x86: drop unnecessary {,No}Rex64Jan Beulich1-5/+5
2018-09-13x86: also allow D on 3-operand insnsJan Beulich1-88/+8
For now this is just for VMOVS{D,S}.
2018-09-13x86: use D attribute also for SIMD templatesJan Beulich1-1143/+89
Various moves come in load and store forms, and just like on the GPR and FPU sides there would better be only one pattern. In some cases this is not feasible because the opcodes are too different, but quite a few cases follow a similar standard scheme. Introduce Opcode_SIMD_FloatD and Opcode_SIMD_IntD, generalize handling in operand_size_match() (reverse operand handling there simply needs to match "straight" operand one), and fix a long standing, but so far only latent bug with when to zap found_reverse_match. Also once again drop IgnoreSize where pointlessly applied to templates touched anyway as well as *word when redundant with Reg*.
2018-08-11x86: Add CpuCMOV and CpuFXSRH.J. Lu1-7522/+7522
There are separate CPUID feature bits for fxsave/fxrstor and cmovCC instructions. This patch adds CpuCMOV and CpuFXSR to replace Cpu686 on corresponding instructions. gas/ * config/tc-i386.c (cpu_arch): Add .cmov and .fxsr. (cpu_noarch): Add nocmov and nofxsr. * doc/c-i386.texi: Document cmov and fxsr. opcodes/ * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS, CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS. (cpu_flags): Add CpuCMOV and CpuFXSR. * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64, fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2018-08-06x86: fold RegEip/RegRip and RegEiz/RegRizJan Beulich1-8/+8
This allows to simplify the code in a number of places.
2018-08-03x86: drop NoRex64 from {,v}pmov{s,z}x*Jan Beulich1-24/+24
They're pointless with IgnoreSize also specified, and even more so when no Qword operand exists.
2018-08-03x86: drop "mem" operand type attributeJan Beulich1-17927/+17927
No template specifies this bit, so there's no point recording it in the templates. Use a flags[] bit instead.
2018-07-31x86: also optimize KXOR{D,Q} and KANDN{D,Q}Jan Beulich1-4/+4
These can be converted to 2-byte VEX encoding when both source registers are the same, by using KXORW / KANDNW as replacement.
2018-07-31x86: fold various AVX512 templates with so far differing Masking attributesJan Beulich1-1286/+222
There's no insn allowing ZEROING_MASKING alone. Re-purpose its value for handling the not uncommon case of insns allowing either form of masking with register operands, but only merging masking with a memory operand.
2018-07-31x86/Intel: correct permitted operand sizes for AVX512 scatter/gatherJan Beulich1-64/+64
AVX gather insns correctly allow the element size to be specified rather than the full vector size. Make AVX512 ones match.
2018-07-31x86: drop CpuVREXJan Beulich1-4129/+4129
It is fully redundant with CpuAVX512F.
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