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path: root/opcodes/i386-tbl.h
AgeCommit message (Expand)AuthorFilesLines
2021-08-05[PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili1-15911/+23504
2021-07-14x86: Add int1 as one byte opcode 0xf1H.J. Lu1-0/+13
2021-04-26x86: optimize LEAJan Beulich1-1/+1
2021-03-30x86: adjust st(<N>) parsingJan Beulich1-5/+1
2021-03-29x86: move some opcode table entriesJan Beulich1-459/+459
2021-03-29x86: VPSADBW's source operands are also commutativeJan Beulich1-3/+3
2021-03-29x86: fold SSE2AVX and their base MMX/SSE templatesJan Beulich1-356/+356
2021-03-29x86: derive opcode encoding space attribute from base opcodeJan Beulich1-1596/+1596
2021-03-26x86-64: don't accept supposedly disabled MOVQ formsJan Beulich1-2/+2
2021-03-25x86: fix AMD Zen3 insnsJan Beulich1-1/+52
2021-03-24x86: derive opcode length from opcode valueJan Beulich1-4034/+4034
2021-03-24x86: derive mandatory prefix attribute from base opcodeJan Beulich1-4974/+4974
2021-03-24x86: don't use opcode_length to identify pseudo prefixesJan Beulich1-11/+11
2021-03-23x86: re-number PREFIX_0X<nn>Jan Beulich1-148/+148
2021-03-23x86: re-order two fields of struct insn_templateJan Beulich1-12099/+12099
2021-03-23x86: split opcode prefix and opcode space representationJan Beulich1-7156/+7156
2021-03-09x86: fold some prefix related attributes into a single oneJan Beulich1-7438/+7438
2021-03-09x86-64: make SYSEXIT handling similar to SYSRET'sJan Beulich1-1/+1
2021-02-16x86: CVTPI2PD has special behaviorJan Beulich1-1/+31
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian1-4020/+4165
2020-10-16Enhancement for avx-vnni patchCui,Lili1-11177/+11177
2020-10-14x86: Support Intel AVX VNNIH.J. Lu1-4292/+4360
2020-10-14x86: Add support for Intel HRESET instructionLili Cui1-4274/+4287
2020-10-14x86: Support Intel UINTRLili Cui1-4010/+8085
2020-10-14x86: Remove the prefix byte from non-VEX/EVEX base_opcodeH.J. Lu1-730/+730
2020-10-13x86: Rename VexOpcode to OpcodePrefixH.J. Lu1-6/+6
2020-09-24Add support for Intel TDX instructions.Cui,Lili1-4058/+4106
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo1-3995/+4141
2020-07-30x86: Add {disp16} pseudo prefixH.J. Lu1-10/+22
2020-07-10x86: Add support for Intel AMX instructionsLili Cui1-14093/+14295
2020-07-08x86: FMA4 scalar insns ignore VEX.LJan Beulich1-16/+16
2020-07-02x86: Add SwapSourcesH.J. Lu1-3982/+3982
2020-06-14x86: Correct xsusldtrk mnemonicH.J. Lu1-1/+1
2020-04-07Add support for intel TSXLDTRK instructions$Cui,Lili1-3980/+4004
2020-04-02Add support for intel SERIALIZE instructionLiliCui1-3979/+3991
2020-03-09x86: use template for AVX512 integer comparison insnsJan Beulich1-32/+32
2020-03-09x86: use template for XOP integer comparison, shift, and rotate insnsJan Beulich1-168/+168
2020-03-09x86: use template for AVX/AVX512 floating point comparison insnsJan Beulich1-3381/+4277
2020-03-09x86: use template for SSE floating point comparison insnsJan Beulich1-144/+144
2020-03-09x86: allow opcode templates to be templatedJan Beulich1-15/+15
2020-03-06x86: reduce amount of various VCVT* templatesJan Beulich1-207/+65
2020-03-06x86: drop/replace IgnoreSizeJan Beulich1-903/+903
2020-03-06x86: don't accept FI{LD,STP,STTP}LL in Intel syntax modeJan Beulich1-6/+6
2020-03-06x86: replace NoRex64 on VEX-encoded insnsJan Beulich1-25/+25
2020-03-06x86: drop Rex64 attributeJan Beulich1-6576/+6576
2020-03-06x86: add missing IgnoreSizeJan Beulich1-18/+30
2020-03-06x86: refine TPAUSE and UMWAITJan Beulich1-6/+38
2020-03-04x86: support VMGEXITJan Beulich1-3929/+3941
2020-03-03x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu1-10851/+10851
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