| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2013-10-12 | Only allow 32-bit/64-bit registers for bndcl/bndcu/bndcn | H.J. Lu | 1 | -14/+59 |
| 2013-10-08 | opcodes/ | Jan Beulich | 1 | -17/+17 |
| 2013-09-30 | Add Size64 to movq/vmovq with Reg64 operand | H.J. Lu | 1 | -8/+8 |
| 2013-07-26 | Add Intel AVX-512 support | H.J. Lu | 1 | -14774/+37062 |
| 2013-07-25 | Support Intel SHA | H.J. Lu | 1 | -2690/+2808 |
| 2013-07-24 | Support Intel MPX | H.J. Lu | 1 | -9818/+9961 |
| 2013-07-08 | Replace Xmmword with Qword on cvttps2pi | H.J. Lu | 1 | -2/+2 |
| 2013-04-08 | gas/testsuite/ | Jan Beulich | 1 | -13/+2 |
| 2013-03-02 | Add RegRex64 to riz | H.J. Lu | 1 | -4/+4 |
| 2013-02-19 | Implement Intel SMAP instructions | H.J. Lu | 1 | -2680/+2702 |
| 2013-01-16 | Add OPERAND_TYPE_IMM32_64 | H.J. Lu | 1 | -1/+1 |
| 2012-11-20 | Fix opcode for 64-bit jecxz | H.J. Lu | 1 | -1/+1 |
| 2012-09-20 | Replace CpuSSE3 with CpuCX16 for cmpxchg16b | H.J. Lu | 1 | -2846/+2846 |
| 2012-08-17 | Add AMD btver1 and btver2 support | H.J. Lu | 1 | -1/+1 |
| 2012-07-31 | VMOVNTDQA was both misplaced and improperly tagged as being an AVX | Jan Beulich | 1 | -1/+1 |
| 2012-07-16 | Implement RDRSEED, ADX and PRFCHW instructions | H.J. Lu | 1 | -2677/+5393 |
| 2012-07-02 | gas/testsuite/ | Roland McGrath | 1 | -1/+1 |
| 2012-06-22 | gas/ | Roland McGrath | 1 | -4/+4 |
| 2012-06-22 | gas/ | Roland McGrath | 1 | -4414/+4414 |
| 2012-02-08 | Implement Intel Transactional Synchronization Extensions | H.J. Lu | 1 | -7078/+7138 |
| 2012-01-13 | Add vmfunc | H.J. Lu | 1 | -2670/+2680 |
| 2011-08-01 | Add Disp32S to 64bit call. | H.J. Lu | 1 | -1/+1 |
| 2011-07-22 | Add initial Intel K1OM support. | H.J. Lu | 1 | -3026/+3026 |
| 2011-06-30 | Fix rorx in BMI2. | H.J. Lu | 1 | -5/+2 |
| 2011-06-10 | Support AVX Programming Reference (June, 2011). | H.J. Lu | 1 | -5340/+8170 |
| 2011-01-18 | opcodes/ | Jan Kratochvil | 1 | -2479/+2612 |
| 2011-01-05 | Implement BMI instructions. | H.J. Lu | 1 | -2476/+2560 |
| 2010-10-14 | Remove CheckRegSize from movq. | H.J. Lu | 1 | -2/+2 |
| 2010-10-14 | Remove CheckRegSize from instructions with 0, 1 or fixed operands. | H.J. Lu | 1 | -34/+34 |
| 2010-10-14 | Add CheckRegSize to instructions which require register size check. | H.J. Lu | 1 | -7417/+7417 |
| 2010-08-06 | Don't generate multi-byte NOPs for i686. | H.J. Lu | 1 | -4443/+4443 |
| 2010-08-06 | Add Cpu186 to ud1/ud2/ud2a/ud2b. | H.J. Lu | 1 | -4/+4 |
| 2010-08-06 | Add ud1 to x86. | H.J. Lu | 1 | -3/+13 |
| 2010-07-05 | Replace rdrnd with rdrand. | H.J. Lu | 1 | -1/+1 |
| 2010-07-01 | Support AVX Programming Reference (June, 2010) | H.J. Lu | 1 | -2816/+2944 |
| 2010-03-23 | 2010-03-22 Sebastian Pop <sebastian.pop@amd.com> | Sebastian Pop | 1 | -53/+1 |
| 2010-02-11 | 2010-02-10 Quentin Neill <quentin.neill@amd.com> | Sebastian Pop | 1 | -5543/+5719 |
| 2010-01-24 | Replace "Vex" with "Vex=3" on AVX scalar instructions. | H.J. Lu | 1 | -208/+208 |
| 2010-01-21 | Add xsave64 and xrstor64. | H.J. Lu | 1 | -0/+20 |
| 2010-01-15 | 2010-01-15 Sebastian Pop <sebastian.pop@amd.com> | Sebastian Pop | 1 | -0/+1024 |
| 2009-12-19 | Replace VexNDS, VexNDD and VexLWP with VexVVVV. | H.J. Lu | 1 | -3492/+3492 |
| 2009-12-16 | Remove ByteOkIntel. | H.J. Lu | 1 | -3816/+3816 |
| 2009-12-16 | Replace Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A with VexOpcode. | H.J. Lu | 1 | -2391/+2391 |
| 2009-12-16 | Replace Vex2Sources and Vex3Sources with VexSources. | H.J. Lu | 1 | -2391/+2391 |
| 2009-12-16 | Remove VexW0 and VexW1. Add VexW. | H.J. Lu | 1 | -2391/+2391 |
| 2009-12-15 | Add USE_VEX_W_TABLE, VEX_W_TABLE and VEX_W_XXX. | H.J. Lu | 1 | -869/+869 |
| 2009-12-04 | Support fxsave64 and fxrstor64. | H.J. Lu | 1 | -0/+20 |
| 2009-11-19 | Allow lock on cmpxch16b. | H.J. Lu | 1 | -1/+1 |
| 2009-11-18 | 2009-11-18 Sebastian Pop <sebastian.pop@amd.com> | Sebastian Pop | 1 | -2472/+2408 |
| 2009-11-18 | 2009-11-17 Sebastian Pop <sebastian.pop@amd.com> | Sebastian Pop | 1 | -4647/+5926 |
