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path: root/opcodes/i386-tbl.h
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2017-06-21x86: CET v2.0: Update incssp and setssbsyH.J. Lu1-11/+11
2017-06-21x86: CET v2.0: Rename savessp to saveprevsspH.J. Lu1-1/+1
2017-05-22x86: Add NOTRACK prefix supportH.J. Lu1-10643/+10656
2017-03-09X86: Add pseudo prefixes to control encodingH.J. Lu1-0/+91
2017-03-09Use CpuCET on rdsspqH.J. Lu1-1/+1
2017-03-06Add support for Intel CET instructionsH.J. Lu1-268/+462
2017-02-28x86: fix handling of 64-bit operand size VPCMPESTR{I,M}Jan Beulich1-6/+120
2017-01-12Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist1-5209/+5241
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-11-09X86: Remove the .s suffix from EVEX vpextrwH.J. Lu1-1/+1
2016-11-09X86: Merge AVX512F vmovqH.J. Lu1-73/+9
2016-11-02Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist1-5207/+5321
2016-11-02Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist1-10432/+10584
2016-10-21X86: Remove pcommit instructionH.J. Lu1-5230/+5217
2016-08-24X86: Add ptwrite instructionH.J. Lu1-5199/+5212
2016-07-01x86: allow suffix-less movzw and 64-bit movzbJan Beulich1-68/+4
2016-07-01x86: remove stray instruction attributesJan Beulich1-44/+44
2016-07-01x86/Intel: fix operand checking for MOVSDJan Beulich1-2/+2
2016-06-03Handle indirect branches for AMD64 and Intel64H.J. Lu1-2/+28
2016-05-27Update x86 CPU_XXX_FLAGS handlingH.J. Lu1-5201/+5201
2016-05-27Replace CpuAMD64/CpuIntel64 with AMD64/Intel64H.J. Lu1-10402/+10402
2016-05-27Correct CpuMax in i386-opc.hH.J. Lu1-2/+2
2016-05-10Enable Intel RDPID instruction.Alexander Fomin1-5199/+5225
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-12-09Implement Intel OSPKE instructionsH.J. Lu1-5197/+5223
2015-06-30Add support for monitorx/mwaitx instructionsAmit Pawar1-5191/+5293
2015-06-01x86/Intel: fix i386_optab[] for vcvt{,u}si2s{d,s}Jan Beulich1-6/+6
2015-06-01x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s}Jan Beulich1-0/+132
2015-05-18Remove Disp32 from AMD64 direct call/jmpH.J. Lu1-2/+2
2015-05-15Support AMD64/Intel ISAs in assembler/disassemblerH.J. Lu1-5183/+5209
2015-05-11Remove Disp16|Disp32 from 64-bit direct branchesH.J. Lu1-3/+16
2015-05-11Add Intel MCU support to opcodesH.J. Lu1-5647/+5647
2015-03-17Add znver1 processorGanesh Gopalasubramanian1-5181/+5194
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-11-17Add AVX512VBMI instructionsIlya Tocar1-5337/+5565
2014-11-17Add AVX512IFMA instructionsIlya Tocar1-5407/+5521
2014-11-17Add pcommit instructionIlya Tocar1-5162/+10337
2014-11-17Add clwb instructionIlya Tocar1-5161/+5173
2014-07-22Add AVX512DQ instructions and their AVX512VL variants.Ilya Tocar1-5726/+8831
2014-07-22Add support for AVX512BW instructions and their AVX512VL versions.Ilya Tocar1-5048/+10952
2014-07-22Add support for AVX512VL versions of AVX512CD instructions.Ilya Tocar1-0/+180
2014-07-22Add support for AVX512VL. Add AVX512VL versions of AVX512F instructions.Ilya Tocar1-4178/+19085
2014-04-04Add support for Intel SGX instructionsIlya Tocar1-3757/+3781
2014-03-20Fix memory size for gather/scatter instructionsIlya Tocar1-8/+8
2014-03-05Update copyright yearsAlan Modra1-2/+1
2014-02-25Remove bogus vcvtps2ph variant.Ilya Tocar1-18/+0
2014-02-21Add support for CPUID PREFETCHWT1Ilya Tocar1-3759/+3759
2014-02-20Change cpu for vptestnmd and vptestnmq instructions.Ilya Tocar1-32/+32
2014-02-19Don't output trailing spaceH.J. Lu1-41582/+41582
2014-02-12Add clflushopt, xsaves, xsavec, xrstorsIlya Tocar1-3752/+3836
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