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path: root/opcodes/i386-tbl.h
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2024-04-07Support APX NFCui, Lili1-290/+663
2024-04-06Revert "x86: Restore APX shift-double instructions with omitted shift count"H.J. Lu1-308/+284
2024-04-04x86: Restore APX shift-double instructions with omitted shift countH.J. Lu1-284/+308
2024-04-03x86: add missing No_qSuf to non-64-bit PTWRITEJan Beulich1-1/+1
2024-04-03x86: drop stray Size64 from WRSSQJan Beulich1-2/+2
2024-04-03x86/APX: Remove KEYLOCKER and SHA promotions from EVEX MAP4Cui, Lili1-239/+63
2024-03-28x86: templatize shift-double insnsJan Beulich1-318/+294
2024-03-28x86: templatize shift/rotate insnsJan Beulich1-193/+357
2024-03-28x86: templatize binary ALU insnsJan Beulich1-390/+450
2024-03-28x86: templatize unary ALU insnsJan Beulich1-6/+6
2024-03-28x86: templatize INC/DECJan Beulich1-54/+54
2024-03-01x86/APX: optimize certain XOR and SUB formsJan Beulich1-2/+2
2024-02-23x86: also permit YMM/ZMM use in CFI directivesJan Beulich1-64/+64
2024-02-23x86/APX: INV{EPT,PCID,VPID} are WIGJan Beulich1-3/+3
2024-02-16x86/APX: drop stray IgnoreSizeJan Beulich1-11/+11
2024-02-16x86: don't use VexWIG in SSE2AVX templatesJan Beulich1-4/+4
2024-02-09x86/APX: V{BROADCAST,EXTRACT,INSERT}{F,I}128 can also be expressedJan Beulich1-197/+269
2024-02-09x86/APX: VROUND{P,S}{S,D} encodings require AVX512{F,VL}Jan Beulich1-4/+4
2024-01-26x86/APX: optimize MOVBEJan Beulich1-34/+34
2024-01-19x86-64: Dwarf2 register numbers for %bnd<N>Jan Beulich1-4/+4
2024-01-19x86/APX: VROUND{P,S}{S,D} can generally be encodedJan Beulich1-147/+199
2024-01-19x86: support APX forms of U{RD,WR}MSRJan Beulich1-6/+26
2024-01-15opcodes: x86: new marker for insns that implicitly update stack pointerIndu Bhagat1-52/+52
2024-01-15opcodes: gas: x86: define and use Rex2 as attribute not constraintIndu Bhagat1-3887/+7772
2024-01-04Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2023-12-28Support APX pushp/poppCui, Lili1-182/+198
2023-12-28Support APX Push2/Pop2Mo, Zewei1-1/+42
2023-12-28Support APX NDDkonglin11-285/+1348
2023-12-28Support APX GPR32 with extend evex prefixCui, Lili1-4087/+4407
2023-12-28Support APX GPR32 with rex2 prefixCui, Lili1-11373/+11637
2023-12-19x86: Remove the restriction for size of the mask register in AVX10Haochen Jiang1-3743/+3743
2023-12-15revert "x86: allow 32-bit reg to be used with U{RD,WR}MSR"Jan Beulich1-2/+2
2023-12-15x86: fold assembly dialect attributesJan Beulich1-7486/+3743
2023-12-15x86: Intel syntax implies Intel mnemonicsJan Beulich1-308/+276
2023-12-01x86: allow 32-bit reg to be used with U{RD,WR}MSRJan Beulich1-2/+2
2023-11-24x86: shrink opcode sets tableJan Beulich1-2343/+295
2023-11-17x86: CPU-qualify {disp16} / {disp32}Jan Beulich1-2/+2
2023-11-09x86: rework UWRMSR operand swappingJan Beulich1-2/+2
2023-11-09x86: do away with is_evex_encoding()Jan Beulich1-575/+575
2023-11-09x86: split insn templates' CPU fieldJan Beulich1-161/+3908
2023-10-31Support Intel USER_MSRHu, Lin11-117/+155
2023-09-27x86: fold FMA VEX and EVEX templatesJan Beulich1-1157/+497
2023-09-27x86: fold VAES/VPCLMULQDQ VEX and EVEX templatesJan Beulich1-299/+198
2023-09-27x86: fold certain VEX and EVEX templatesJan Beulich1-955/+621
2023-09-15x86: fold CpuLM and Cpu64Jan Beulich1-2188/+2188
2023-09-14x86: support AVX10.1 vector size restrictionsJan Beulich1-3846/+7692
2023-09-14x86: make AES/PCMULQDQ respectively prereqs of VAES/VPCMULQDQJan Beulich1-290/+290
2023-09-01x86: drop Size64 from VMOVQJan Beulich1-1/+1
2023-08-11x86: pack CPU flags in opcode tableJan Beulich1-30768/+3846
2023-08-02Revert "2.41 Release sources"Sam James1-4415/+8525