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path: root/opcodes/i386-tbl.h
AgeCommit message (Expand)AuthorFilesLines
2018-01-23Enable Intel PCONFIG instruction.Igor Tsimbalist1-5280/+5294
2018-01-23Enable Intel WBNOINVD instruction.Igor Tsimbalist1-5279/+5293
2018-01-17Replace CET bit with IBT and SHSTK bits.Igor Tsimbalist1-5332/+5332
2018-01-11Remove VL variants for 4FMAPS and 4VNNIW insns.Igor Tsimbalist1-160/+0
2018-01-10x86: fix Disp8 handling for scalar AVX512_4FMAPS insnsJan Beulich1-2/+2
2018-01-10x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variantsJan Beulich1-48/+48
2018-01-08x86: Properly encode vmovd with 64-bit memeoryH.J. Lu1-38/+4
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-12-18x86: fold certain AVX and AVX2 templatesJan Beulich1-3773/+586
2017-12-18x86: fold RegXMM/RegYMM/RegZMM into RegSIMDJan Beulich1-46173/+46173
2017-12-18x86: drop FloatReg and FloatAccJan Beulich1-32462/+32462
2017-12-18x86: replace Reg8, Reg16, Reg32, and Reg64Jan Beulich1-32604/+33036
2017-12-15x86: drop stray CheckRegSize usesJan Beulich1-74/+74
2017-11-30x86: derive DispN from BaseIndexJan Beulich1-18/+18
2017-11-30x86: drop Vec_Disp8Jan Beulich1-14130/+14130
2017-11-23Add Disp8MemShift for AVX512 VAES instructions.Igor Tsimbalist1-12/+12
2017-11-23x86: correct UDnJan Beulich1-8/+31
2017-11-22Remove Vec_Disp8 field for vgf2p8mulb for AVX flavor.Igor Tsimbalist1-2/+2
2017-11-22Remove Vec_Disp8 from vpcompressb and vpexpandb.Igor Tsimbalist1-6/+6
2017-11-15x86-64: don't allow use of %axl as accumulatorJan Beulich1-1/+1
2017-11-14x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich1-6/+1446
2017-11-14x86: string insns don't allow displacementsJan Beulich1-23/+23
2017-11-13x86: {f,}xsave64 / {f,}xrstor64 / xsaveopt64 should not allow q suffixJan Beulich1-5/+5
2017-10-23Fix the master due to bad regenerated filesIgor Tsimbalist1-5330/+11222
2017-10-23Enable Intel VAES instructions.Igor Tsimbalist1-5386/+5690
2017-10-23Enable Intel GFNI instructions.Igor Tsimbalist1-5293/+5716
2017-10-23Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist1-5239/+6265
2017-06-21x86: CET v2.0: Update incssp and setssbsyH.J. Lu1-11/+11
2017-06-21x86: CET v2.0: Rename savessp to saveprevsspH.J. Lu1-1/+1
2017-05-22x86: Add NOTRACK prefix supportH.J. Lu1-10643/+10656
2017-03-09X86: Add pseudo prefixes to control encodingH.J. Lu1-0/+91
2017-03-09Use CpuCET on rdsspqH.J. Lu1-1/+1
2017-03-06Add support for Intel CET instructionsH.J. Lu1-268/+462
2017-02-28x86: fix handling of 64-bit operand size VPCMPESTR{I,M}Jan Beulich1-6/+120
2017-01-12Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist1-5209/+5241
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-11-09X86: Remove the .s suffix from EVEX vpextrwH.J. Lu1-1/+1
2016-11-09X86: Merge AVX512F vmovqH.J. Lu1-73/+9
2016-11-02Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist1-5207/+5321
2016-11-02Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist1-10432/+10584
2016-10-21X86: Remove pcommit instructionH.J. Lu1-5230/+5217
2016-08-24X86: Add ptwrite instructionH.J. Lu1-5199/+5212
2016-07-01x86: allow suffix-less movzw and 64-bit movzbJan Beulich1-68/+4
2016-07-01x86: remove stray instruction attributesJan Beulich1-44/+44
2016-07-01x86/Intel: fix operand checking for MOVSDJan Beulich1-2/+2
2016-06-03Handle indirect branches for AMD64 and Intel64H.J. Lu1-2/+28
2016-05-27Update x86 CPU_XXX_FLAGS handlingH.J. Lu1-5201/+5201
2016-05-27Replace CpuAMD64/CpuIntel64 with AMD64/Intel64H.J. Lu1-10402/+10402
2016-05-27Correct CpuMax in i386-opc.hH.J. Lu1-2/+2
2016-05-10Enable Intel RDPID instruction.Alexander Fomin1-5199/+5225
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