aboutsummaryrefslogtreecommitdiff
path: root/opcodes/i386-opc.tbl
AgeCommit message (Collapse)AuthorFilesLines
2024-05-29x86/Intel: warn about undue mnemonic suffixesJan Beulich1-87/+87
Except for very few insns mnemonic suffixes aren't permitted in Intel syntax. Warn about such for now, indicating that they will be outright refused down the road. While fiddling with testcases to address fallout, drop a few things which should never have been tested as valid Intel syntax. Also add a previously missing line to simd-suffix.d.
2024-05-24x86: correct VCVT{,U}SI2SDJan Beulich1-8/+8
Properly reject inappropriate suffixes (No_lSuf / No_qSuf mistakenly omitted by cf665fee1d6c ["x86: re-work AVX512 embedded rounding / SAE"]), to avoid emitting bad or arbitrarily guessed instructions. Interestingly check_{long,qword}_suffix() don't help here, which perhaps is another indication that the way they work right now isn't quite appropriate. Sadly correcting just the templates breaks operand ambiguity detection, since so far that worked from a single template permitting more than one suffix. Here we have ambiguity though which can now be noticed only when taking all (matching) templates together. Therefore we need to determine further matching templates (see code comments for constraints), to then accumulate permitted suffixes across all of them.
2024-05-22Support APX zero-upperCui, Lili1-0/+6
This patch is to enable ZU for IMUL (opcodes 0x69 and 0x6B) and SETcc. Since the spec only recommends one form of setzu, I won't be adding set<cc>reg32/reg64 support in this patch. gas/ChangeLog: * config/tc-i386.c (build_apx_evex_prefix): Handle ZU. * testsuite/gas/i386/x86-64.exp: Added new tests for ZU. * testsuite/gas/i386/x86-64.exp: Added new tests for ZU. * testsuite/gas/i386/x86-64-apx-zu-intel.d: New test. * testsuite/gas/i386/x86-64-apx-zu-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-zu-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-zu.d: Ditto. * testsuite/gas/i386/x86-64-apx-zu.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_MAP4_40 ~ PREFIX_EVEX_MAP4_4F. * i386-dis-evex.h: Ditto. * i386-dis.c (struct dis386): Add new micro 'ZU'. (putop): Handle %ZU. * i386-gen.c: Added ZU. * i386-opc.h: Ditto. * i386-opc.tbl: Added new templates to support ZU.
2024-05-06x86: Drop using extension_opcode to encode vvvv registerCui, Lili1-59/+61
gas/ChangeLog: * config/tc-i386.c (build_modrm_byte): Dropped the use of extension_opcode to encode the vvvv register. * testsuite/gas/i386/x86-64-sse2avx.d: Added new testcases. * testsuite/gas/i386/x86-64-sse2avx.s: Diito. opcodes/ChangeLog: * i386-opc.tbl: Added DstVVVV to some extension_opcode instructions. * i386-tbl.h: Regenerated.
2024-05-06x86: Drop SwapSourcesCui, Lili1-30/+30
gas/ChangeLog: * config/tc-i386.c (build_modrm_byte): Dropped the use of SWAP_SOURCES to encode the vvvv register. opcodes/ChangeLog: * i386-opc.h (SWAP_SOURCES): Dropped. (NO_DEFAULT_MASK): Adjusted the value. (ADDR_PREFIX_OP_REG): Ditto. (DISTINCT_DEST): Ditto. (IMPLICIT_STACK_OP): Ditto. (VexVVVV_SRC2): New. * i386-opc.tbl: Dropped SwapSources and replaced its VexVVVV with Src1VVVV. * i386-tbl.h: Regenerated.
2024-05-06x86: Use vexvvvv as the switch state to encode the vvvv registerCui, Lili1-565/+566
Use vexvvvv as the switch state, and replace VexVVVV with Src1VVVV. Src1VVVV means using VEX.vvvv encodes the first source register operand. The old logic did not check vexvvvv first, which made the logic here very complicated. gas/ChangeLog: * config/tc-i386.c (optimize_encoding): Replaced 1 with Src1VVVV. (build_modrm_byte): Used vexvvvv to encode the vvvv register. (s_insn): Replaced 1 with Src1VVVV. opcodes/ChangeLog: * i386-opc.h (VexVVVV_DST): Adjusted the value. (Src1VVVV): New. * i386-opc.tbl: Replaced part VexVVVV with Src1VVVV. * i386-tbl.h: Regenerated.
2024-05-03x86: tidy <sse*> templatesJan Beulich1-20/+20
Some of them no longer need a separate vvvv attribute, thus allowing them to be simplified. For <aes> the situation is slightly different: None of the remaining uses make use of vvvv anymore.
2024-05-03x86/APX: further extend SSE2AVX coverageJan Beulich1-5/+6
Since {vex}/{vex3} are respected on legacy mnemonics when -msse2avx is in use, {evex} should be respected, too. So far this is the case only for insns where eGPR-s can come into play. Extend coverage to insns with only %xmm register and possibly immediate operands.
2024-05-03x86/APX: extend SSE2AVX coverageJan Beulich1-201/+303
Legacy encoded SIMD insns are converted to AVX ones in that mode. When eGPR-s are in use, i.e. with APX, convert to AVX10 insns (where available; there are quite a few which can't be converted). Note that LDDQU is represented as VMOVDQU32 (and the prior use of the sse3 template there needs dropping, to get the order right). Note further that in a few cases, due to the use of templates, AVX512VL is used when AVX512F would suffice. Since AVX10 is the main reference, this shouldn't be too much of a problem.
2024-04-17Add W table for USER_MSR under MAP4.Hu, Lin11-1/+1
opcodes/ChangeLog: * i386-dis-evex-mod.h: Modify MOD_EVEX_MAP4_F8_P1, MOD_EVEX_MAP4_F8_P3. * i386-dis-evex-w.h (EVEX_W_MAP4_F8_P1_M_1): New. (EVEX_W_MAP4_F8_P3_M_1): Ditto. * i386-dis.c (vex_w_table): Add EVEX_W_MAP4_F8_P1_M_1, EVEX_W_MAP4_F8_P3_M_1. * i386-opc.tbl: Remove redundant '|'.
2024-04-07Support APX NFCui, Lili1-2/+21
For the case when NDD and NF are both 0 in evex-promoted format, we will fully support and test it in another patch. gas/ChangeLog: * NEWS: Support Intel APX NF. * config/tc-i386.c (enum i386_error): Add unsupported_nf. (struct _i386_insn): Add has_nf. (is_apx_evex_encoding): Ditto. (build_apx_evex_prefix): Encode the NF bit. (md_assemble): Handle unsupported_nf. (parse_insn): Handle Prefix_NF and report bad for illegal combination. (can_convert_NDD_to_legacy): Replace i.tm.opcode_modifier.nf with i.has_nf. (match_template): Support D for APX_F insns and check NF support. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add apx nf tests. * testsuite/gas/i386/x86-64-apx-nf-intel.d: New test. * testsuite/gas/i386/x86-64-apx-nf.d: Ditto. * testsuite/gas/i386/x86-64-apx-nf.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Add %NF to the instructions that support APX NF and add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table. * i386-dis-evex-reg.h: Ditto. * i386-dis.c (struct instr_info): Add nf. (struct dis386): Add "NF" for EVEX.NF. (get_valid_dis386): Set ins->vex.nf and report bad-nf for illegal case. (print_insn): Handle ins.vex.nf. (putop): Handle "%NF". * i386-opc.h (Prefix_NF): New. * i386-opc.tbl: Added new entries to support full APX NF instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Regenerated.
2024-04-06Revert "x86: Restore APX shift-double instructions with omitted shift count"H.J. Lu1-1/+0
This reverts commit c2d698fe03a6092d58a07de96068b87836daced0. GCC 14 has been changed to use explicit shift count in shift-double instructions by the commit: 06a7e7514af x86: Use explicit shift count in double-precision shifts gas/ PR gas/31606 * testsuite/gas/i386/x86-64-apx-ndd-wig.d: Updated. * testsuite/gas/i386/x86-64-apx-ndd.d: Likewise. * testsuite/gas/i386/x86-64-apx-ndd.s: Remove tests for APX shift-double instructions with omitted shift count. opcodes/ PR gas/31606 * i386-opc.tbl: Remove APX shift-double instructions with omitted shift count. * i386-tbl.h: Regenerated.
2024-04-04x86: Restore APX shift-double instructions with omitted shift countH.J. Lu1-0/+1
Restore APX shift-double instructions with omitted shift count since they are generated by GCC as shown in: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114590 gas/ PR gas/31606 * testsuite/gas/i386/x86-64-apx-ndd-wig.d: Updated. * testsuite/gas/i386/x86-64-apx-ndd.d: Likewise. * testsuite/gas/i386/x86-64-apx-ndd.s: Add tests for APX shift-double instructions with omitted shift count. opcodes/ PR gas/31606 * i386-opc.tbl: Restore APX shift-double instructions with omitted shift count. * i386-tbl.h: Regenerated.
2024-04-03x86: add missing No_qSuf to non-64-bit PTWRITEJan Beulich1-1/+1
While largely benign, it still should have been put there when the original single template was split (commit a04973848dc5).
2024-04-03x86: drop stray Size64 from WRSSQJan Beulich1-2/+2
Like for WRUSSQ it's not needed here. The legacy insn had gained it in the course of zapping Rex64, but that attribute wasn't needed here either. The APX insn then simply gained it by copy-and-paste, I suppose.
2024-04-03x86/APX: Remove KEYLOCKER and SHA promotions from EVEX MAP4Cui, Lili1-18/+0
APX spec removed KEYLOCKER and SHA promotions from EVEX MAP4. https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html gas/ChangeLog: * NEWS: Mention that remove KEYLOCKER and SHA promotions from EVEX * MAP4. * config/tc-i386.c (process_operands): Removed special handling of * KEYLOCKER and SHA. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l: Removed KEYLOCKER * and SHA instructions. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Removed KEYLOCKER and SHA instructions. * i386-dis-evex.h: Ditto. * i386-opc.tbl: Ditto. * i386-dis.c (print_vector_reg): Removed special handling of KEYLOCKER * and SHA.
2024-03-28x86: templatize RAO-INT insnsJan Beulich1-8/+4
It's only four of them, but still better to reduce redundancy.
2024-03-28x86: templatize ADX insnsJan Beulich1-6/+5
It's only two of them, but still better to reduce redundancy.
2024-03-28x86: templatize shift-double insnsJan Beulich1-13/+9
With the multitude of new APX templates, it finally becomes desirable to further remove redundancy by also templatizing basic arithmetic insns. Continue with the shift-double ones. While there also drop the APX form with ShiftCount omitted. Other shift and rotate insns were deliberately left without this form as well. Note that there's also no testsuite adjustment needed for this, indicating that the form wasn't tested either.
2024-03-28x86: templatize shift/rotate insnsJan Beulich1-71/+22
With the multitude of new APX templates, it finally becomes desirable to further remove redundancy by also templatizing basic arithmetic insns. Continue with the "ordinary" shift and rotate ones. While there also drop the APX form of RCL/RCR with Imm1 omitted. Other shift insns as well as ROR/ROL were deliberately left without this form as well. Note that there's also no testsuite adjustment needed for this, indicating that the form wasn't tested either. Furthermore since RCL/RCR already had non-NDD APX forms, those end up being added for the other 6 mnemonics, too.
2024-03-28x86: templatize binary ALU insnsJan Beulich1-59/+23
With the multitude of new APX templates, it finally becomes desirable to further remove redundancy by also templatizing basic arithmetic insns. Continue with a the more complex binary (two source) cases. Note how this adds a missing CheckOperandSize to one of the APX sub forms. Furthermore since SBB already had a non-NDD APX form, one ends up being added for the other 6 mnemonics, too.
2024-03-28x86: templatize unary ALU insnsJan Beulich1-10/+16
With the multitude of new APX templates, it finally becomes desirable to further remove redundancy by also templatizing basic arithmetic insns. Continue with a few simple unary (single source) cases.
2024-03-28x86: templatize INC/DECJan Beulich1-8/+8
With the multitude of new APX templates, it finally becomes desirable to further remove redundancy by also templatizing basic arithmetic insns. Start with the simplest case, accompanied by a necessary adjustment to i386-gen (such that template uses can also be at the start of a line). While there also drop a bogus (meaningless / unreachable) "break" as well as a unused variable (which I'm surprised compilers didn't warn about).
2024-03-01x86/APX: optimize certain XOR and SUB formsJan Beulich1-2/+2
While most logic in optimize_encoding() is already covering APX by way of the earlier NDD->REX2 conversion, there's a remaining set of cases which wants handling separately.
2024-02-23x86/APX: INV{EPT,PCID,VPID} are WIGJan Beulich1-3/+3
While various other entries in version 003 of the spec aren't quite as explicit (due to simply leaving the respective field blank), all three have a clear IGNORED there. IOW they ought to be emitted with EVEX.W=0 by default (and respect -mevexwig=).
2024-02-16x86/APX: drop stray IgnoreSizeJan Beulich1-11/+11
While necessary on the legacy encodings, the EVEX ones don't need it. Even more so when they're available for 64-bit mode only, when the legacy encodings have the attribute only for correctly handling things in 16-bit mode.
2024-02-16x86: don't use VexWIG in SSE2AVX templatesJan Beulich1-4/+4
Several years ago it was decided that SSE2AVX templates should not be sensitive to -mvexwig= (upon my suggestion to consistently make all sensitive as long as they don't require a specific setting of VEX.W). Adjust the four that still are, switching to use of Vex128 at the same time.
2024-02-16x86: drop redundant XmmwordJan Beulich1-8/+8
While e20298da05f2 ("Remove redundant Byte, Word, Dword and Qword from insn templates") did so for Byte/Word/Dword/Qword, the same kind of redundancy was left in place for a few 128-bit SIMD operands.
2024-02-09x86/APX: V{BROADCAST,EXTRACT,INSERT}{F,I}128 can also be expressedJan Beulich1-4/+16
Interestingly unlike VROUND{P,S}{S,D} and VPERM{F,I}128 they weren't even present in the x86-64-apx-egpr-inval testcase, hence why I overlooked that these can actually be encoded, (again) using suitable AVX512 counterparts. While there also "modernize" the adjacent AVX/AVX2 entries.
2024-02-09x86/APX: VROUND{P,S}{S,D} encodings require AVX512{F,VL}Jan Beulich1-2/+2
In eea4357967b6 ("x86/APX: VROUND{P,S}{S,D} can generally be encoded") I failed to add the AVX512* ISA dependency of the two new entries.
2024-01-26x86/APX: optimize MOVBEJan Beulich1-2/+4
With identical source and destination it can be covered by the NDD-to- legacy conversion logic as well, even if in this case the original insn doesn't use an NDD encoding. The size savings are even better here, for the replacement (BSWAP) not having a ModR/M byte.
2024-01-19x86/APX: VROUND{P,S}{S,D} can generally be encodedJan Beulich1-0/+4
VRNDSCALE{P,S}{S,D} is the AVX512 generalization of these AVX insns. As long as the immediate has the top 4 bits clear, they are equivalent to the earlier VEX-encoded insns, and hence can be used to permit use of eGPR-s in the memory operand. Since this is the normal way of using these insns, also alter the resulting diagnostic to complain about the immediate, not the eGPR use.
2024-01-19x86: drop redundant EVex128 from PUSH2/POP2Jan Beulich1-4/+4
EVexMap4 already covers that.
2024-01-19x86: support APX forms of U{RD,WR}MSRJan Beulich1-2/+4
This was missed in 6177c84d5edc ("Support APX GPR32 with extend evex prefix").
2024-01-15opcodes: x86: new marker for insns that implicitly update stack pointerIndu Bhagat1-52/+53
Some x86 instructions affect the stack pointer implicitly. Add a new operand constraint to reflect this. This will be useful for SCFI implmentation to ensure its correctness. Mark all push, pop, call, ret, enter, leave, INT, iret instructions. opcodes/ * i386-gen.c: Update opcode_modifiers. * i386-opc.h: Add a new constraint. * i386-opc.tbl: Update the affected instructions. * i386-tbl.h: Regenerated.
2024-01-15opcodes: gas: x86: define and use Rex2 as attribute not constraintIndu Bhagat1-1/+0
Rex2 is currently an operand constraint. For the upcoming SCFI implementation in GAS, we need to identify operations which implicitly update the stack pointer. An operand constraint enumerator for implicit stack op seems more appropriate than an attribute. However, two opcodes currently necessitate both Rex2 and an implicit stack op marker; this prompts revisiting the current representations a bit. Make Rex2 a standalone attribute, so that later a new operand constraint may be added for IMPLICIT_STACK_OP. ChangeLog: * gas/config/tc-i386.c (is_apx_rex2_encoding): Update the check. * opcodes/i386-gen.c: Add a new BITFIELD for Rex2. * opcodes/i386-opc.h (REX2_REQUIRED): Remove. * opcodes/i386-opc.tbl: Remove Rex2 operand constraint. * opcodes/i386-tbl.h: Regenerated.
2024-01-09x86: add missing APX logic to cpu_flags_match()Jan Beulich1-1/+7
As already indicated during review, we can't get away without certain adjustments here: Without these, respective {evex}-prefixed insns are assembled to APX encodings even when APX_F is turned off. While there also extend the respective comment in the opcode table, to explain why this construct is used.
2024-01-04Update year range in copyright notice of binutils filesAlan Modra1-1/+1
Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out */po/*.pot which we don't update frequently.
2023-12-28Support APX pushp/poppCui, Lili1-0/+3
gas/ChangeLog: * config/tc-i386.c (process_operands): Handle "PUSHP/POPP requires rex2.w == 1." * testsuite/gas/i386/x86-64.exp: Add new test for PUSHP/POPP. * testsuite/gas/i386/x86-64-apx-pushp-popp-intel.d: New test. * testsuite/gas/i386/x86-64-apx-pushp-popp-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-pushp-popp-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-pushp-popp.d: Ditto. * testsuite/gas/i386/x86-64-apx-pushp-popp.s: Ditto. opcodes/ChangeLog: * i386-dis.c (putop): print pushp and popp. * i386-opc.tbl: Added new insns. * i386-init.h : Regenerated. * i386-mnem.h : Regenerated. * i386-tbl.h: Regenerated.
2023-12-28Support APX Push2/Pop2Mo, Zewei1-0/+9
PPX functionality for PUSH/POP is not implemented in this patch and will be implemented separately. gas/ChangeLog: 2023-12-28 Zewei Mo <zewei.mo@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c: (enum i386_error): New unsupported_rsp_register and invalid_src_register_set. (md_assemble): Add handler for unsupported_rsp_register and invalid_src_register_set. (check_APX_operands): Add invalid check for push2/pop2. (match_template): Handle check_APX_operands. * testsuite/gas/i386/i386.exp: Add apx-push2pop2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2.d: New test. * testsuite/gas/i386/x86-64-apx-push2pop2.s: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-inval.s: Ditto. * testsuite/gas/i386/apx-push2pop2-inval.s: Ditto. * testsuite/gas/i386/apx-push2pop2-inval.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Added bad testcases for POP2. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-reg.h: Add REG_EVEX_MAP4_8F. * i386-dis-evex-w.h: Add EVEX_W_MAP4_8F_R_0 and EVEX_W_MAP4_FF_R_6 * i386-dis-evex.h: Add REG_EVEX_MAP4_8F. * i386-dis.c (PUSH2_POP2_Fixup): Add special handling for PUSH2/POP2. (get_valid_dis386): Add handler for vector length and address_mode for APX-Push2/Pop2 insn. (nd): define nd as b for EVEX-promoted instrutions. (OP_VEX): Add handler of 64-bit vvvv register for APX-Push2/Pop2 insn. * i386-gen.c: Add Push2Pop2 bitfield. * i386-opc.h: Regenerated. * i386-opc.tbl: Regenerated.
2023-12-28Support APX NDDkonglin11-0/+75
opcodes/ChangeLog: * opcodes/i386-dis-evex-reg.h: Handle for REG_EVEX_MAP4_80, REG_EVEX_MAP4_81, REG_EVEX_MAP4_83, REG_EVEX_MAP4_F6, REG_EVEX_MAP4_F7, REG_EVEX_MAP4_FE, REG_EVEX_MAP4_FF. * opcodes/i386-dis-evex.h: Add NDD insn. * opcodes/i386-dis.c (nd): New define. (VexGb): Ditto. (VexGv): Ditto. (get_valid_dis386): Change for NDD decode. (print_insn): Ditto. (putop): Ditto. (intel_operand_size): Ditto. (OP_E_memory): Ditto. (OP_VEX): Ditto. * opcodes/i386-opc.h (VexVVVV_DST): New. * opcodes/i386-opc.tbl: Add APX NDD instructions and adjust VexVVVV. * opcodes/i386-tbl.h: Regenerated. gas/ChangeLog: * gas/config/tc-i386.c (operand_size_match): Support APX NDD that the number of operands is 3. (build_apx_evex_prefix): Change for ndd encode. (process_operands): Ditto. (build_modrm_byte): Ditto. (match_template): Support swap the first two operands for APX NDD. * testsuite/gas/i386/x86-64.exp: Add x86-64-apx-ndd. * testsuite/gas/i386/x86-64-apx-ndd.d: New test. * testsuite/gas/i386/x86-64-apx-ndd.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d : Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s : Ditto.
2023-12-28Support APX GPR32 with extend evex prefixCui, Lili1-25/+65
This patch adds non-ND, non-NF forms of EVEX promotion insn. EVEX extension of legacy instructions: All promoted legacy instructions are placed in EVEX map 4, which is currently reserved. EVEX extension of EVEX instructions: All existing EVEX instructions are extended by APX using the extended EVEX prefix, so that they can access all 32 GPRs. EVEX extension of VEX instructions: Promoting a VEX instruction into the EVEX space does not change the map id, the opcode, or the operand encoding of the VEX instruction. Note: The promoted versions of MOVBE will be extended to include the “MOVBE reg1, reg2”. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (struct _i386_insn): Add has_egpr. (need_evex_encoding): Adjusted for apx. (cpu_flags_match): Ditto. (install_template): Handled APX combines. (is_apx_evex_encoding): Test apx evex encoding. (build_apx_evex_prefix): Enabe APX evex prefix. (md_assemble): Handle apx with evex encoding. (process_suffix): Handle apx map4 prefix. (check_register): Assign i.vec_encoding for APX evex instructions. * testsuite/gas/i386/x86-64-evex.d: Adjust test cases. * testsuite/gas/i386/x86-64.exp: Adjust x86-64-inval-movbe. opcodes/ChangeLog: * i386-dis-evex-len.h: Handle EVEX_LEN_0F38F2, EVEX_LEN_0F38F3. * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_0F38F2_L_0, PREFIX_EVEX_0F38F3_L_0, PREFIX_EVEX_MAP4_D8, PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB, PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD, PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF, PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1, PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8. * i386-dis-evex-reg.h: Handle REG_EVEX_0F38F3_L_0_P_0. * i386-dis-evex.h: Add EVEX_MAP4_ for legacy insn promote to apx to use gpr32 * opcodes/i386-dis-evex-x86-64.h: Handle Add X86_64_EVEX_0F90, X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F38F2, X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6, X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0, X86_64_EVEX_0F91. * i386-dis.c (struct instr_info): Deleted bool r. (PREFIX_NP_OR_DATA): New. (NO_PREFIX): New. (putop): Ditto. (X86_64_EVEX_FROM_VEX_TABLE): Diito. (get_valid_dis386): Decode insn erex in extend evex prefix. Handle EVEX_MAP4 (print_insn): Handle PREFIX_DATA_AND_NP_ONLY. (print_register): Handle apx instructions decode. (OP_E_memory): Diito. (OP_G): Diito. (OP_XMM): Diito. (DistinctDest_Fixup): Diito. * i386-gen.c (process_i386_opcode_modifier): Add EVEXMAP4. * i386-opc.h (SPACE_EVEXMAP4): Add legacy insn promote to evex. * i386-opc.tbl: Handle some legacy and vex insns don't support gpr32. And add some legacy insn (map2 / 3) promote to evex.
2023-12-28Support APX GPR32 with rex2 prefixCui, Lili1-13/+14
APX uses the REX2 prefix to support EGPR for map0 and map1 of legacy instructions. We added the NoEgpr flag in i386-gen.c for instructions that do not support EGPR. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (enum i386_error): Add unsupported_EGPR_for_addressing and invalid_pseudo_prefix. (struct _i386_insn): Add rex2 and rex2_encoding for gpr32. (cpu_arch): Add apx_f. (is_cpu): Ditto. (register_number): Handle RegRex2 for gpr32. (is_apx_rex2_encoding): New func. Test rex2 prefix encoding. (build_rex2_prefix): New func. Build legacy insn in opcode 0/1 use gpr32 with rex2 prefix. (establish_rex): Handle rex2 and rex2_encoding. (optimize_encoding): Handel add r16-r31 for registers. (md_assemble): Handle apx encoding. (parse_insn): Handle Prefix_REX2. (check_EgprOperands): New func. Check if Egprs operands are valid for the instruction (match_template): Handle Egpr operands check. (set_rex_rex2): New func. set i.rex and i.rex2. (build_modrm_byte): Ditto. (output_insn): Handle rex2 2-byte prefix output. (check_register): Handle check egpr illegal without target apx, 64-bit mode and with rex_prefix. * doc/c-i386.texi: Document .apx. * testsuite/gas/i386/ilp32/x86-64-opcode-inval-intel.d: D5 valid in 64-bit mode. * testsuite/gas/i386/ilp32/x86-64-opcode-inval.d: Ditto. * testsuite/gas/i386/rex-bad: Adjust rex testcase. * testsuite/gas/i386/x86-64-opcode-inval-intel.d: Ditto. * testsuite/gas/i386/x86-64-opcode-inval.d: Ditto. * testsuite/gas/i386/x86-64-opcode-inval.s: Ditto. * testsuite/gas/i386/x86-64-pseudos-bad.l: Add illegal rex2 test. * testsuite/gas/i386/x86-64-pseudos-bad.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add rex2 test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64.exp: Run APX tests. * testsuite/gas/i386/x86-64-apx-egpr-inval.l: New test. * testsuite/gas/i386/x86-64-apx-egpr-inval.s: New test. * testsuite/gas/i386/x86-64-apx-rex2.d: New test. * testsuite/gas/i386/x86-64-apx-rex2.s: New test. include/ChangeLog: * opcode/i386.h (REX2_OPCODE): New. (REX2_M): Ditto. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Add erex for gpr32. Add last_erex_prefix for rex2 prefix. (REX2_M): Extend for gpr32. (PREFIX_REX2): Ditto. (PREFIX_REX2_ILLEGAL): Ditto. (ckprefix): Ditto. (prefix_name): Ditto. (print_insn): Ditto. (print_register): Ditto. (OP_E_memory): Ditto. (OP_REG): Ditto. (OP_EX): Ditto. * i386-gen.c (rex2_disallowed): Some instructions are not allowed rex2 prefix. (process_i386_opcode_modifier): Set NoEgpr for VEX and some special instructions. (output_i386_opcode): Handle if_entry_needs_special_handle. * i386-init.h : Regenerated. * i386-mnem.h : Regenerated. * i386-opc.h (enum i386_cpu): Add CpuAPX_F. (NoEgpr): New. (Prefix_NoOptimize): Ditto. (Prefix_REX2): Ditto. (RegRex2): Ditto. * i386-opc.tbl: Add rex2 prefix. * i386-reg.tbl: Add egprs (r16-r31). * i386-tbl.h: Regenerated.
2023-12-19x86: Remove the restriction for size of the mask register in AVX10Haochen Jiang1-22/+19
Since AVX10.1/256 will also allow 64 bit mask register, we will remove the restriction for size of the mask register in AVX10. gas/ChangeLog: * config/tc-i386.c (VSZ128, VSZ256, VSZ512): New. (VEX_check_encoding): Remove opcode_modifier check for vsz. * testsuite/gas/i386/avx10-vsz.l: Remove testcases for mask registers since they are not needed. * testsuite/gas/i386/avx10-vsz.s: Ditto. opcodes/ChangeLog: * i386-gen.c: Remove Vsz. * i386-opc.h: Ditto. * i386-opc.tbl: Remove kvsz. * i386-tbl.h: Regenerated.
2023-12-15revert "x86: allow 32-bit reg to be used with U{RD,WR}MSR"Jan Beulich1-2/+2
This reverts commit 1f865bae65db9588f6994c02a92355bfb4e3d955. The specification is going to by updated in a way rendering this change wrong.
2023-12-15x86: fold assembly dialect attributesJan Beulich1-0/+4
Now that ATTSyntax and ATTMnemonic aren't use in combination anymore, fold them and IntelSyntax into a single, enum-like attribute. Note that this shrinks i386_opcode_modifier back to 2 32-bit words (albeit that's not for long, seeing in-flight additions for APX).
2023-12-15x86: Intel syntax implies Intel mnemonicsJan Beulich1-20/+16
As noted in the context of d53e6b98a259 ("x86/Intel: correct disassembly of fsub*/fdiv*") there's no such thing as Intel syntax without Intel mnemonics. Enforce this on the assembler side, and disentangle command line option handling on the disassembler side accordingly. As a result in the opcode table specifying ATTMnemonic|ATTSyntax becomes redundant with just ATTMnemonic. Drop the now meaningless ATTSyntax and remove the then no longer accessible templates.
2023-12-14Remove redundant Byte, Word, Dword and Qword from insn templates.Cui, Lili1-123/+123
opcodes/ChangeLog: * i386-opc.tbl: Remove redundant Byte, Word, Dword and Qword.
2023-12-01x86: allow 32-bit reg to be used with U{RD,WR}MSRJan Beulich1-2/+2
... as MSR index specifier: It is unreasonable to demand that people write less readable / understandable code, just because the present documentation mentions only Reg64. Whether to also adjust the disassembler is a separate question, perhaps indeed more tightly tied to what the spec says.
2023-11-24x86: also prefer VEX encoding over EVEX one for VCVTNEPS2BF16 when possibleJan Beulich1-0/+6
Deal with what 58bceb182740 ("x86: prefer VEX encodings over EVEX ones when possible") left out, for being slightly less straightforward.
generated by cgit v1.1 at 2024-11-24 23:31:03 +0000