Age | Commit message (Expand) | Author | Files | Lines |
2020-10-20 | Add AMD znver3 processor support | Ganesh Gopalasubramanian | 1 | -0/+26 |
2020-10-16 | Enhancement for avx-vnni patch | Cui,Lili | 1 | -4/+4 |
2020-10-14 | x86: Support Intel AVX VNNI | H.J. Lu | 1 | -0/+10 |
2020-10-14 | x86: Add support for Intel HRESET instruction | Lili Cui | 1 | -0/+6 |
2020-10-14 | x86: Support Intel UINTR | Lili Cui | 1 | -0/+10 |
2020-10-14 | x86: Remove the prefix byte from non-VEX/EVEX base_opcode | H.J. Lu | 1 | -344/+344 |
2020-10-13 | x86: Rename VexOpcode to OpcodePrefix | H.J. Lu | 1 | -2140/+2144 |
2020-09-24 | Add support for Intel TDX instructions. | Cui,Lili | 1 | -0/+9 |
2020-09-23 | Enable support to Intel Keylocker instructions | Terry Guo | 1 | -0/+16 |
2020-07-30 | x86: Add {disp16} pseudo prefix | H.J. Lu | 1 | -10/+11 |
2020-07-10 | x86: Add support for Intel AMX instructions | Lili Cui | 1 | -0/+23 |
2020-07-08 | x86: FMA4 scalar insns ignore VEX.L | Jan Beulich | 1 | -16/+16 |
2020-07-02 | x86: Add SwapSources | H.J. Lu | 1 | -5/+5 |
2020-06-26 | i386-opc.tbl: Add a blank line | H.J. Lu | 1 | -0/+1 |
2020-06-26 | x86: Correct VexSIB128 to VecSIB128 | H.J. Lu | 1 | -27/+27 |
2020-06-26 | x86: Rename VecSIB to SIB for Intel AMX | H.J. Lu | 1 | -78/+81 |
2020-06-14 | x86: Correct xsusldtrk mnemonic | H.J. Lu | 1 | -1/+1 |
2020-04-07 | Add support for intel TSXLDTRK instructions$ | Cui,Lili | 1 | -0/+7 |
2020-04-02 | Add support for intel SERIALIZE instruction | LiliCui | 1 | -0/+6 |
2020-03-09 | x86: use template for AVX512 integer comparison insns | Jan Beulich | 1 | -48/+10 |
2020-03-09 | x86: use template for XOP integer comparison, shift, and rotate insns | Jan Beulich | 1 | -100/+13 |
2020-03-09 | x86: use template for AVX/AVX512 floating point comparison insns | Jan Beulich | 1 | -496/+22 |
2020-03-09 | x86: use template for SSE floating point comparison insns | Jan Beulich | 1 | -64/+10 |
2020-03-09 | x86: allow opcode templates to be templated | Jan Beulich | 1 | -90/+6 |
2020-03-06 | x86: reduce amount of various VCVT* templates | Jan Beulich | 1 | -30/+20 |
2020-03-06 | x86: drop/replace IgnoreSize | Jan Beulich | 1 | -699/+699 |
2020-03-06 | x86: don't accept FI{LD,STP,STTP}LL in Intel syntax mode | Jan Beulich | 1 | -3/+3 |
2020-03-06 | x86: replace NoRex64 on VEX-encoded insns | Jan Beulich | 1 | -25/+25 |
2020-03-06 | x86: drop Rex64 attribute | Jan Beulich | 1 | -18/+18 |
2020-03-06 | x86: add missing IgnoreSize | Jan Beulich | 1 | -18/+18 |
2020-03-06 | x86: refine TPAUSE and UMWAIT | Jan Beulich | 1 | -4/+4 |
2020-03-04 | x86: support VMGEXIT | Jan Beulich | 1 | -0/+1 |
2020-03-03 | x86: Replace IgnoreSize/DefaultSize with MnemonicSize | H.J. Lu | 1 | -0/+3 |
2020-03-03 | x86: Allow integer conversion without suffix in AT&T syntax | H.J. Lu | 1 | -10/+20 |
2020-02-17 | x86: Remove CpuABM and add CpuPOPCNT | H.J. Lu | 1 | -3/+5 |
2020-02-17 | x86: fold certain VCVT{,U}SI2S{S,D} templates | Jan Beulich | 1 | -21/+15 |
2020-02-17 | x86: fold AddrPrefixOpReg templates | Jan Beulich | 1 | -24/+15 |
2020-02-17 | x86/Intel: improve diagnostics for ambiguous VCVT* operands | Jan Beulich | 1 | -13/+23 |
2020-02-14 | Remove Intel syntax comments on movsx and movzx | H.J. Lu | 1 | -3/+2 |
2020-02-14 | x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZX | Jan Beulich | 1 | -12/+5 |
2020-02-12 | x86: correct VFPCLASSP{S,D} operand size handling | Jan Beulich | 1 | -2/+4 |
2020-02-12 | x86: fold two JMP templates | Jan Beulich | 1 | -2/+1 |
2020-02-12 | x86-64: Intel64 adjustments for insns dealing with far pointers | Jan Beulich | 1 | -11/+16 |
2020-02-11 | x86: drop ShortForm attribute | Jan Beulich | 1 | -95/+95 |
2020-02-11 | x86: drop stray ShortForm attributes | Jan Beulich | 1 | -6/+6 |
2020-02-10 | x86: Accept Intel64 only instruction by default | H.J. Lu | 1 | -11/+15 |
2020-01-30 | x86-64: honor vendor specifics for near RET | Jan Beulich | 1 | -2/+4 |
2020-01-30 | x86: drop further pointless/bogus DefaultSize | Jan Beulich | 1 | -9/+9 |
2020-01-27 | x86-64: Properly encode and decode movsxd | H.J. Lu | 1 | -1/+3 |
2020-01-21 | x86: improve handling of insns with ambiguous operand sizes | Jan Beulich | 1 | -1/+1 |