| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2016-01-01 | Copyright update for binutils | Alan Modra | 1 | -1/+1 |
| 2015-12-09 | Implement Intel OSPKE instructions | H.J. Lu | 1 | -0/+7 |
| 2015-06-30 | Add support for monitorx/mwaitx instructions | Amit Pawar | 1 | -0/+13 |
| 2015-06-01 | x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s} | Jan Beulich | 1 | -0/+6 |
| 2015-05-18 | Remove Disp32 from AMD64 direct call/jmp | H.J. Lu | 1 | -2/+2 |
| 2015-05-15 | Support AMD64/Intel ISAs in assembler/disassembler | H.J. Lu | 1 | -2/+4 |
| 2015-05-11 | Remove Disp16|Disp32 from 64-bit direct branches | H.J. Lu | 1 | -2/+3 |
| 2015-03-17 | Add znver1 processor | Ganesh Gopalasubramanian | 1 | -0/+7 |
| 2015-01-02 | ChangeLog rotatation and copyright year update | Alan Modra | 1 | -1/+1 |
| 2014-11-17 | Add AVX512VBMI instructions | Ilya Tocar | 1 | -0/+17 |
| 2014-11-17 | Add AVX512IFMA instructions | Ilya Tocar | 1 | -0/+11 |
| 2014-11-17 | Add pcommit instruction | Ilya Tocar | 1 | -0/+6 |
| 2014-11-17 | Add clwb instruction | Ilya Tocar | 1 | -0/+6 |
| 2014-07-22 | Add AVX512DQ instructions and their AVX512VL variants. | Ilya Tocar | 1 | -0/+212 |
| 2014-07-22 | Add support for AVX512BW instructions and their AVX512VL versions. | Ilya Tocar | 1 | -0/+385 |
| 2014-07-22 | Add support for AVX512VL versions of AVX512CD instructions. | Ilya Tocar | 1 | -0/+20 |
| 2014-07-22 | Add support for AVX512VL. Add AVX512VL versions of AVX512F instructions. | Ilya Tocar | 1 | -0/+944 |
| 2014-04-04 | Add support for Intel SGX instructions | Ilya Tocar | 1 | -0/+7 |
| 2014-03-20 | Fix memory size for gather/scatter instructions | Ilya Tocar | 1 | -8/+8 |
| 2014-03-05 | Update copyright years | Alan Modra | 1 | -2/+1 |
| 2014-02-25 | Remove bogus vcvtps2ph variant. | Ilya Tocar | 1 | -1/+0 |
| 2014-02-21 | Add support for CPUID PREFETCHWT1 | Ilya Tocar | 1 | -2/+6 |
| 2014-02-20 | Change cpu for vptestnmd and vptestnmq instructions. | Ilya Tocar | 1 | -4/+3 |
| 2014-02-12 | Add clflushopt, xsaves, xsavec, xrstors | Ilya Tocar | 1 | -0/+22 |
| 2013-10-12 | Only allow 32-bit/64-bit registers for bndcl/bndcu/bndcn | H.J. Lu | 1 | -8/+11 |
| 2013-10-08 | opcodes/ | Jan Beulich | 1 | -9/+9 |
| 2013-09-30 | Add Size64 to movq/vmovq with Reg64 operand | H.J. Lu | 1 | -8/+8 |
| 2013-07-26 | Add Intel AVX-512 support | H.J. Lu | 1 | -0/+1209 |
| 2013-07-25 | Support Intel SHA | H.J. Lu | 1 | -0/+10 |
| 2013-07-24 | Support Intel MPX | H.J. Lu | 1 | -41/+54 |
| 2013-07-08 | Replace Xmmword with Qword on cvttps2pi | H.J. Lu | 1 | -1/+1 |
| 2013-04-08 | gas/testsuite/ | Jan Beulich | 1 | -2/+1 |
| 2013-02-19 | Implement Intel SMAP instructions | H.J. Lu | 1 | -0/+4 |
| 2012-11-20 | Fix opcode for 64-bit jecxz | H.J. Lu | 1 | -1/+1 |
| 2012-09-20 | Replace CpuSSE3 with CpuCX16 for cmpxchg16b | H.J. Lu | 1 | -1/+1 |
| 2012-08-17 | Add AMD btver1 and btver2 support | H.J. Lu | 1 | -1/+1 |
| 2012-08-07 | There were several cases where the registers in the REX encoded range | Jan Beulich | 1 | -5/+0 |
| 2012-07-31 | VMOVNTDQA was both misplaced and improperly tagged as being an AVX | Jan Beulich | 1 | -1/+1 |
| 2012-07-16 | Implement RDRSEED, ADX and PRFCHW instructions | H.J. Lu | 1 | -1/+6 |
| 2012-07-02 | gas/testsuite/ | Roland McGrath | 1 | -1/+1 |
| 2012-06-22 | gas/ | Roland McGrath | 1 | -4/+4 |
| 2012-06-22 | gas/ | Roland McGrath | 1 | -56/+56 |
| 2012-02-08 | Implement Intel Transactional Synchronization Extensions | H.J. Lu | 1 | -40/+51 |
| 2012-01-13 | Add vmfunc | H.J. Lu | 1 | -0/+4 |
| 2011-08-01 | Add Disp32S to 64bit call. | H.J. Lu | 1 | -1/+1 |
| 2011-06-30 | Fix rorx in BMI2. | H.J. Lu | 1 | -1/+1 |
| 2011-06-10 | Support AVX Programming Reference (June, 2011). | H.J. Lu | 1 | -1/+195 |
| 2011-01-17 | Add support for TBM instructions. | Quentin Neill | 1 | -0/+12 |
| 2011-01-05 | Implement BMI instructions. | H.J. Lu | 1 | -0/+9 |
| 2010-10-14 | Remove CheckRegSize from movq. | H.J. Lu | 1 | -2/+2 |
