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AgeCommit message (Expand)AuthorFilesLines
2017-11-23Add Disp8MemShift for AVX512 VAES instructions.Igor Tsimbalist1-12/+12
2017-11-23x86: correct UDnJan Beulich1-2/+4
2017-11-22Remove Vec_Disp8 field for vgf2p8mulb for AVX flavor.Igor Tsimbalist1-2/+2
2017-11-22Remove Vec_Disp8 from vpcompressb and vpexpandb.Igor Tsimbalist1-7/+6
2017-11-14x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich1-19/+91
2017-11-14x86: string insns don't allow displacementsJan Beulich1-19/+19
2017-11-13x86: {f,}xsave64 / {f,}xrstor64 / xsaveopt64 should not allow q suffixJan Beulich1-5/+5
2017-10-23Enable Intel AVX512_BITALG instructions.Igor Tsimbalist1-0/+20
2017-10-23Enable Intel AVX512_VNNI instructions.Igor Tsimbalist1-0/+20
2017-10-23Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist1-0/+14
2017-10-23Enable Intel VAES instructions.Igor Tsimbalist1-0/+24
2017-10-23Enable Intel GFNI instructions.Igor Tsimbalist1-0/+36
2017-10-23Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist1-0/+75
2017-06-21x86: CET v2.0: Update incssp and setssbsyH.J. Lu1-3/+3
2017-06-21x86: CET v2.0: Rename savessp to saveprevsspH.J. Lu1-1/+1
2017-05-22x86: Add NOTRACK prefix supportH.J. Lu1-6/+9
2017-03-09X86: Add pseudo prefixes to control encodingH.J. Lu1-68/+78
2017-03-09Use CpuCET on rdsspqH.J. Lu1-1/+1
2017-03-06Add support for Intel CET instructionsH.J. Lu1-0/+19
2017-02-28x86: fix handling of 64-bit operand size VPCMPESTR{I,M}Jan Beulich1-6/+12
2017-01-12Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist1-1/+9
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-11-09X86: Remove the .s suffix from EVEX vpextrwH.J. Lu1-1/+1
2016-11-09X86: Merge AVX512F vmovqH.J. Lu1-8/+4
2016-11-02Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist1-0/+12
2016-11-02Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist1-0/+16
2016-10-21X86: Remove pcommit instructionH.J. Lu1-6/+0
2016-08-24X86: Add ptwrite instructionH.J. Lu1-0/+6
2016-07-01x86: allow suffix-less movzw and 64-bit movzbJan Beulich1-12/+3
2016-07-01x86: remove stray instruction attributesJan Beulich1-44/+44
2016-07-01x86/Intel: fix operand checking for MOVSDJan Beulich1-2/+2
2016-06-03Handle indirect branches for AMD64 and Intel64H.J. Lu1-2/+4
2016-05-27Replace CpuAMD64/CpuIntel64 with AMD64/Intel64H.J. Lu1-4/+4
2016-05-10Enable Intel RDPID instruction.Alexander Fomin1-0/+7
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-12-09Implement Intel OSPKE instructionsH.J. Lu1-0/+7
2015-06-30Add support for monitorx/mwaitx instructionsAmit Pawar1-0/+13
2015-06-01x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s}Jan Beulich1-0/+6
2015-05-18Remove Disp32 from AMD64 direct call/jmpH.J. Lu1-2/+2
2015-05-15Support AMD64/Intel ISAs in assembler/disassemblerH.J. Lu1-2/+4
2015-05-11Remove Disp16|Disp32 from 64-bit direct branchesH.J. Lu1-2/+3
2015-03-17Add znver1 processorGanesh Gopalasubramanian1-0/+7
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-11-17Add AVX512VBMI instructionsIlya Tocar1-0/+17
2014-11-17Add AVX512IFMA instructionsIlya Tocar1-0/+11
2014-11-17Add pcommit instructionIlya Tocar1-0/+6
2014-11-17Add clwb instructionIlya Tocar1-0/+6
2014-07-22Add AVX512DQ instructions and their AVX512VL variants.Ilya Tocar1-0/+212
2014-07-22Add support for AVX512BW instructions and their AVX512VL versions.Ilya Tocar1-0/+385
2014-07-22Add support for AVX512VL versions of AVX512CD instructions.Ilya Tocar1-0/+20
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