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2008-08-28gas/testsuite/Jan Beulich1-0/+4
2008-08-28 Jan Beulich <jbeulich@novell.com> * gas/i386/intel.s: Add retf. * gas/i386/intel.{d,e}: Adjust. * gas/i386/opcode-intel.d: Replace lret with retf. opcodes/ 2008-08-28 Jan Beulich <jbeulich@novell.com> * i386-dis.c (dis386): Adjust far return mnemonics. * i386-opc.tbl: Add retf. * i386-tbl.h: Re-generate.
2008-08-27gas/testsuite/H.J. Lu1-1/+1
2008-08-27 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/intel.s: Add tests for fidivr. * gas/i386/intel.d: Updated. opcodes/ 2008-08-27 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Correct fidivr operand size. * i386-tbl.h: Regenerated.
2008-08-20gas/H.J. Lu1-0/+15
2008-08-20 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (August, 2008) * config/tc-i386.c (CPU_FLAGS_AES_MATCH): New. (CPU_FLAGS_AVX_MATCH): Likewise. (CPU_FLAGS_32BIT_MATCH): Updated. (cpu_flags_match): Likewise. gas/testsuite/ 2008-08-20 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (August, 2008) * gas/i386/avx.s: Add AES + AVX tests. * gas/i386/arch-10.s: Likewise. * gas/i386/sse2avx.s: Likewise. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/x86-64-avx.s: Likewise. * gas/i386/x86-64-sse2avx.s: Likewise. * gas/i386/arch-10.d: Updated. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/avx.d: Likewise. * gas/i386/avx-intel.d: Likewise. * gas/i386/sse2avx.d: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. * gas/i386/x86-64-sse2avx.d: Likewise. * gas/i386/i386.exp: Run arch-avx-1, arch-avx-1-1 and arch-avx-1-2. * gas/i386/arch-avx-1.d: New. * gas/i386/arch-avx-1.s: Likewise. * gas/i386/arch-avx-1-1.l: Likewise. * gas/i386/arch-avx-1-1.s: Likewise. * gas/i386/arch-avx-1-2.l: Likewise. * gas/i386/arch-avx-1-2.s: Likewise. opcodes/ 2008-08-20 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (August, 2008) * i386-dis.c (PREFIX_VEX_38DB): New. (PREFIX_VEX_38DC): Likewise. (PREFIX_VEX_38DD): Likewise. (PREFIX_VEX_38DE): Likewise. (PREFIX_VEX_38DF): Likewise. (PREFIX_VEX_3ADF): Likewise. (VEX_LEN_38DB_P_2): Likewise. (VEX_LEN_38DC_P_2): Likewise. (VEX_LEN_38DD_P_2): Likewise. (VEX_LEN_38DE_P_2): Likewise. (VEX_LEN_38DF_P_2): Likewise. (VEX_LEN_3ADF_P_2): Likewise. (PREFIX_VEX_3A04): Updated. (VEX_LEN_3A06_P_2): Likewise. (prefix_table): Add PREFIX_VEX_38DB, PREFIX_VEX_38DC, PREFIX_VEX_38DD, PREFIX_VEX_38DE and PREFIX_VEX_3ADF. (x86_64_table): Likewise. (vex_len_table): Add VEX_LEN_38DB_P_2, VEX_LEN_38DC_P_2, VEX_LEN_38DD_P_2, VEX_LEN_38DE_P_2, VEX_LEN_38DF_P_2 and VEX_LEN_3ADF_P_2. * i386-opc.tbl: Add AES + AVX instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2008-08-12gas/testsuite/H.J. Lu1-0/+2
2008-08-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/amd.s: Add syscall and sysret. Remove padding. * gas/i386/amd.d: Updated. * gas/i386/x86-64-opcode.d: Likewise. * gas/i386/i386.exp: Run x86-64-intel64. * gas/i386/x86-64-intel64.d: New. * gas/i386/x86-64-intel64.s: Likewise. * gas/i386/x86-64-opcode.s: Add syscall and sysret. opcodes/ 2008-08-12 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add syscall and sysret for Cpu64. * i386-tbl.h: Regenerated.
2008-05-30gas/testsuite/H.J. Lu1-0/+7
2008-05-30 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/x86-64-avx.s: Add tests for vmovd on 64bit operands. * gas/i386/x86-64-sse2avx.s: Add tests for movd on 64bit operands. * gas/testsuite/gas/i386/x86-64-avx.d: Updated. * gas/testsuite/gas/i386/x86-64-avx-intel.d: Likewise. * gas/testsuite/gas/i386/x86-64-sse2avx.d: Likewise. opcodes/ 2008-05-30 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add vmovd with 64bit operand. * i386-tbl.h: Regenerated.
2008-05-23gas/testsuite/H.J. Lu1-3/+3
2008-05-22 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/sse-noavx.s: Add tests for cvtpd2pi, cvtpi2pd and cvttpd2pi. * gas/i386/x86-64-sse-noavx.s: Likewise. * gas/i386/sse-noavx.d: Updated. * gas/i386/x86-64-sse-noavx.d: Likewise. opcodes/ 2008-05-22 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi. * i386-tbl.h: Regenerated.
2008-05-22gas/testsuite/H.J. Lu1-6/+12
2008-05-22 H.J. Lu <hongjiu.lu@intel.com> PR gas/6517 * gas/i386/avx.s: Add tests for unspecified memory operand size in Intel syntax. * gas/i386/x86-64-avx.s: Likewise. * gas/i386/simd.s: Add tests for cvtsi2ss and cvtsi2sd with unspecified memory operand size in Intel syntax. * gas/i386/avx.d: Updated. * gas/i386/avx-intel.d: Likewise. * gas/i386/simd.d: Likewise. * gas/i386/simd-intel.d: Likewise. * gas/i386/simd-suffix.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. opcodes/ 2008-05-22 H.J. Lu <hongjiu.lu@intel.com> PR gas/6517 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss into 32bit and 64bit. Remove Reg64|Qword and add IgnoreSize|No_qSuf on 32bit version. * i386-tbl.h: Regenerated.
2008-05-21gas/testsuite/H.J. Lu1-2/+2
2008-05-21 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/sse-noavx.s: Add tests for movdq2q and movq2dq. * gas/i386/x86-64-sse-noavx.s: Likewise. * gas/i386/sse-noavx.d: Updated. * gas/i386/x86-64-sse-noavx.d: Likewise. opcodes/ 2008-05-21 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq. * i386-tbl.h: Regenerated.
2008-05-02gas/H.J. Lu1-0/+11
2008-05-02 H.J. Lu <hongjiu.lu@intel.com> * NEWS: Mention XSAVE, EPT and MOVBE. * config/tc-i386.c (cpu_arch): Add .movbe and .ept. (md_show_usage): Add .movbe and .ept. * doc/c-i386.texi: Add movbe and ept to -march=. Document .movbe and .ept. gas/testsuite/ 2008-05-02 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run movbe, movbe-intel, inval-movbe, ept, ept-intel, inval-ept, x86-64-movbe, x86-64-movbe-intel, x86-64-inval-movbe. x86-64-ept, x86-64-ept-intel and x86-64-inval-ept. * gas/i386/arch-10.s: Add movbe and invept. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/ept.d: New file * gas/i386/ept-intel.d: Likewise. * gas/i386/ept.s: Likewise. * gas/i386/inval-ept.l: Likewise. * gas/i386/inval-ept.s: Likewise. * gas/i386/inval-movbe.l: Likewise. * gas/i386/inval-movbe.s: Likewise. * gas/i386/movbe.d: Likewise. * gas/i386/movbe-intel.d: Likewise. * gas/i386/movbe.s: Likewise. * gas/i386/x86-64-inval-ept.l: Likewise. * gas/i386/x86-64-inval-ept.s: Likewise. * gas/i386/x86-64-inval-movbe.l: Likewise. * gas/i386/x86-64-inval-movbe.s: Likewise. * gas/i386/x86-64-ept.d: Likewise. * gas/i386/x86-64-ept-intel.d: Likewise. * gas/i386/x86-64-ept.s: Likewise. * gas/i386/x86-64-movbe.d: Likewise. * gas/i386/x86-64-movbe-intel.d: Likewise. * gas/i386/x86-64-movbe.s: Likewise. * gas/i386/arch-10.d: Updated. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. opcodes/ 2008-05-02 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (MOVBE_Fixup): New. (Mo): Likewise. (PREFIX_0F3880): Likewise. (PREFIX_0F3881): Likewise. (PREFIX_0F38F0): Updated. (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update PREFIX_0F38F0 and PREFIX_0F38F1 for movbe. (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881. * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and CPU_EPT_FLAGS. (cpu_flags): Add CpuMovbe and CpuEPT. * i386-opc.h (CpuMovbe): New. (CpuEPT): Likewise. (CpuLM): Updated. (i386_cpu_flags): Add cpumovbe and cpuept. * i386-opc.tbl: Add entries for movbe and EPT instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2008-04-22gas/H.J. Lu1-56/+56
2008-04-22 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (md_assemble): Don't check SSE instructions if noavx is 0. opcodes/ 2008-04-22 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Add NoAVX. * i386-opc.h (NoAVX): New. (OldGcc): Updated. (i386_opcode_modifier): Add noavx. * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3 instructions which don't have AVX equivalent. * i386-tbl.h: Regenerated.
2008-04-16<opcode changes>Dwarakanath Rajagopal1-4/+4
2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> Michael Meissner <michael.meissner@amd.com> * i386-opc.tbl: Fix protX to allow memory in the middle operand. * i386-tbl.h: Regenerate from i386-opc.tbl. <gas/testsuite changes> 2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> Michael Meissner <michael.meissner@amd.com> * gas/i386/x86-64-sse5.s: Add protX tests to allow memory in the middle operand. * gas/i386/x86-64-sse5.d: Likewise.
2008-04-072008-04-07 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu1-4/+0
* i386-opc.tbl: Remove 4 extra blank lines.
2008-04-04gas/H.J. Lu1-6/+6
2008-04-04 H.J. Lu <hongjiu.lu@intel.com> * NEWS: Mention XSAVE. Change CLMUL to PCLMUL. * config/tc-i386.c (cpu_arch): Add .pclmul. (md_show_usage): Replace clmul with pclmul. * doc/c-i386.texi: Likewise. gas/testsuite/ 2008-04-04 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-10-1.l: Replace CLMUL with PCLMUL. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/arch-10.s: Likewise. * gas/i386/clmul-intel.d: Likewise. * gas/i386/clmul.d: Likewise. * gas/i386/clmul.s: Likewise. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/x86-64-clmul-intel.d: Likewise. * gas/i386/x86-64-clmul.d: Likewise. * gas/i386/x86-64-clmul.s: Likewise. * gas/i386/arch-10.d: Replace clmul with pclmul. * gas/i386/x86-64-arch-2.d: Likewise. opcodes/ 2008-04-04 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL with CPU_PCLMUL_FLAGS/CpuPCLMUL. (cpu_flags): Replace CpuCLMUL with CpuPCLMUL. * i386-opc.tbl: Likewise. * i386-opc.h (CpuCLMUL): Renamed to ... (CpuPCLMUL): This. (CpuFMA): Updated. (i386_cpu_flags): Replace cpuclmul with cpupclmul. * i386-init.h: Regenerated.
2008-04-03binutils/H.J. Lu1-98/+1092
2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * dwarf.c (dwarf_regnames_i386): Add AVX registers. (dwarf_regnames_x86_64): Likewise. gas/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx. * doc/c-i386.texi: Add avx, aes, clmul and fma to -march=. Document -msse2avx, .avx, .aes, .clmul and .fma. * config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New. (vex_prefix): Likewise. (sse2avx): Likewise. (CPU_FLAGS_ARCH_MATCH): Likewise. (CPU_FLAGS_64BIT_MATCH): Likewise. (CPU_FLAGS_32BIT_MATCH): Likewise. (CPU_FLAGS_PERFECT_MATCH): Likewise. (regymm): Likewise. (vex_imm4): Likewise. (fits_in_imm4): Likewise. (build_vex_prefix): Likewise. (VEX_check_operands): Likewise. (bad_implicit_operand): Likewise. (OPTION_MSSE2AVX): Likewise. (T_YMMWORD): Likewise. (_i386_insn): Add vex. (cpu_arch): Add .avx, .aes, .clmul and .fma. (cpu_flags_match): Changed to take a pointer to const template. Enable encoding SSE instructions with VEX prefix for -msse2avx. (match_mem_size): Also check ymmword. (operand_type_match): Clear ymmword. (md_begin): Allow '_' in mnemonic. (type_names): Add OPERAND_TYPE_VEX_IMM4. (process_immext): Update assert. (md_assemble): Don't call process_immext if sse2avx and immext are true. Call build_vex_prefix if vex is true. (parse_insn): Updated for cpu_flags_match. (swap_operands): Handle 5 operands. (match_template): Handle 5 operands. Updated for cpu_flags_match. Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX. (process_suffix): Handle YMMWORD_MNEM_SUFFIX. (check_byte_reg): Check regymm. (process_operands): Duplicate the destination register for -msse2avx if needed. (build_modrm_byte): Updated for instructions with VEX encoding. (output_insn): Output VEX prefix if needed. (md_longopts): Add msse2avx. (md_parse_option): Handle OPTION_MSSE2AVX. (md_show_usage): Add avx, aes, clmul, fma and -msse2avx. (intel_e09): Support YMMWORD. (intel_e11): Likewise. (intel_get_token): Likewise. gas/testsuite/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes, x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx, x86-64-avx-intel and x86-64-inval-avx. * gas/cfi/cfi-i386.s: Add tests for AVX register maps. * gas/cfi/cfi-x86_64.s: Likewise. * gas/i386/aes.d: New. * gas/i386/aes.s: Likewise. * gas/i386/aes-intel.d: Likewise. * gas/i386/avx.d: Likewise. * gas/i386/avx.s: Likewise. * gas/i386/avx-intel.d: Likewise. * gas/i386/clmul.d: Likewise. * gas/i386/clmul-intel.d: Likewise. * gas/i386/clmul.s: Likewise. * gas/i386/i386.exp: Likewise. * gas/i386/inval-avx.l: Likewise. * gas/i386/inval-avx.s: Likewise. * gas/i386/sse2avx.d: Likewise. * gas/i386/sse2avx.s: Likewise. * gas/i386/x86-64-aes.d: Likewise. * gas/i386/x86-64-aes.s: Likewise. * gas/i386/x86-64-aes-intel.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx.s: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. * gas/i386/x86-64-clmul.d: Likewise. * gas/i386/x86-64-clmul-intel.d: Likewise. * gas/i386/x86-64-clmul.s: Likewise. * gas/i386/x86-64-inval-avx.l: Likewise. * gas/i386/x86-64-inval-avx.s: Likewise. * gas/i386/x86-64-sse2avx.d: Likewise. * gas/i386/x86-64-sse2avx.s: Likewise. * gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/rexw.s: Add AVX tests. * gas/i386/x86-64-opcode-inval.s: Remove lds/les test. * gas/cfi/cfi-i386.d: Updated. * gas/cfi/cfi-x86_64.d: Likewise. * gas/i386/arch-10.d: Likewise. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/rexw.d: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/x86-64-opcode-inval.d: Likewise. * gas/i386/x86-64-opcode-inval-intel.d: Likewise. include/opcode/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * i386.h (MAX_OPERANDS): Set to 5. (MAX_MNEM_SIZE): Changed to 20. opcodes/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_E_register): New. (OP_E_memory): Likewise. (OP_VEX): Likewise. (OP_EX_Vex): Likewise. (OP_EX_VexW): Likewise. (OP_XMM_Vex): Likewise. (OP_XMM_VexW): Likewise. (OP_REG_VexI4): Likewise. (PCLMUL_Fixup): Likewise. (VEXI4_Fixup): Likewise. (VZERO_Fixup): Likewise. (VCMP_Fixup): Likewise. (VPERMIL2_Fixup): Likewise. (rex_original): Likewise. (rex_ignored): Likewise. (Mxmm): Likewise. (XMM): Likewise. (EXxmm): Likewise. (EXxmmq): Likewise. (EXymmq): Likewise. (Vex): Likewise. (Vex128): Likewise. (Vex256): Likewise. (VexI4): Likewise. (EXdVex): Likewise. (EXqVex): Likewise. (EXVexW): Likewise. (EXdVexW): Likewise. (EXqVexW): Likewise. (XMVex): Likewise. (XMVexW): Likewise. (XMVexI4): Likewise. (PCLMUL): Likewise. (VZERO): Likewise. (VCMP): Likewise. (VPERMIL2): Likewise. (xmm_mode): Likewise. (xmmq_mode): Likewise. (ymmq_mode): Likewise. (vex_mode): Likewise. (vex128_mode): Likewise. (vex256_mode): Likewise. (USE_VEX_C4_TABLE): Likewise. (USE_VEX_C5_TABLE): Likewise. (USE_VEX_LEN_TABLE): Likewise. (VEX_C4_TABLE): Likewise. (VEX_C5_TABLE): Likewise. (VEX_LEN_TABLE): Likewise. (REG_VEX_XX): Likewise. (MOD_VEX_XXX): Likewise. (PREFIX_0F38DB..PREFIX_0F38DF): Likewise. (PREFIX_0F3A44): Likewise. (PREFIX_0F3ADF): Likewise. (PREFIX_VEX_XXX): Likewise. (VEX_OF): Likewise. (VEX_OF38): Likewise. (VEX_OF3A): Likewise. (VEX_LEN_XXX): Likewise. (vex): Likewise. (need_vex): Likewise. (need_vex_reg): Likewise. (vex_i4_done): Likewise. (vex_table): Likewise. (vex_len_table): Likewise. (OP_REG_VexI4): Likewise. (vex_cmp_op): Likewise. (pclmul_op): Likewise. (vpermil2_op): Likewise. (m_mode): Updated. (es_reg): Likewise. (PREFIX_0F38F0): Likewise. (PREFIX_0F3A60): Likewise. (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE. (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF and PREFIX_VEX_XXX entries. (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE. (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and PREFIX_0F3ADF. (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE. Add MOD_VEX_XXX entries. (ckprefix): Initialize rex_original and rex_ignored. Store the REX byte in rex_original. (get_valid_dis386): Handle the implicit prefix in VEX prefix bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE. (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before calling get_valid_dis386. Use rex_original and rex_ignored when printing out REX. (putop): Handle "XY". (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and ymmq_mode. (OP_E_extended): Updated to use OP_E_register and OP_E_memory. (OP_XMM): Handle VEX. (OP_EX): Likewise. (XMM_Fixup): Likewise. (CMP_Fixup): Use ARRAY_SIZE. * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS, CPU_FMA_FLAGS and CPU_AVX_FLAGS. (operand_type_init): Add OPERAND_TYPE_REGYMM and OPERAND_TYPE_VEX_IMM4. (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA. (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD, VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources, VexImmExt and SSE2AVX. (operand_types): Add RegYMM, Ymmword and Vex_Imm4. * i386-opc.h (CpuAVX): New. (CpuAES): Likewise. (CpuCLMUL): Likewise. (CpuFMA): Likewise. (Vex): Likewise. (Vex256): Likewise. (VexNDS): Likewise. (VexNDD): Likewise. (VexW0): Likewise. (VexW1): Likewise. (Vex0F): Likewise. (Vex0F38): Likewise. (Vex0F3A): Likewise. (Vex3Sources): Likewise. (VexImmExt): Likewise. (SSE2AVX): Likewise. (RegYMM): Likewise. (Ymmword): Likewise. (Vex_Imm4): Likewise. (Implicit1stXmm0): Likewise. (CpuXsave): Updated. (CpuLM): Likewise. (ByteOkIntel): Likewise. (OldGcc): Likewise. (Control): Likewise. (Unspecified): Likewise. (OTMax): Likewise. (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma. (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256, vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a, vex3sources, veximmext and sse2avx. (i386_operand_type): Add regymm, ymmword and vex_imm4. * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions. * i386-reg.tbl: Add AVX registers, ymm0..ymm15. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2008-03-01gas/testsuite/H.J. Lu1-2/+2
2008-03-01 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/x86-64-branch.s: Add tests for 16-bit near indirect branches. * gas/i386/x86-64-inval.s: Remove tests for 16-bit near indirect branches. * gas/i386/x86-64-branch.d: Updated. * gas/i386/x86-64-inval.l: Likewise. opcodes/ 2008-03-01 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64. * i386-tbl.h: Regenerated.
2008-02-23gas/testsuite/H.J. Lu1-2/+2
2008-02-23 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/jump.s: Add tests for far branches. * gas/i386/jump16.s: Likewise. * gas/i386/jump.d: Updated. * gas/i386/jump16.d: Likewise. * gas/i386/x86-64-inval.l: Likewise. * gas/i386/x86-64-inval.s: Add tests for 16-bit near indirect branches. opcodes/ 2008-02-23 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Disallow 16-bit near indirect branches for x86-64. * i386-tbl.h: Regenerated.
2008-02-21opcodes/Jan Beulich1-4/+4
2008-02-21 Jan Beulich <jbeulich@novell.com> * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword and Fword for far indirect jmp. Allow Reg16 and Word for near indirect jmp on x86-64. Disallow Fword for lcall. * i386-tbl.h: Re-generate.
2008-02-13gas/Jan Beulich1-1/+1
2008-02-13 Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (intel_e09): Also special-case 'bound'. gas/testsuite/ 2008-02-13 Jan Beulich <jbeulich@novell.com> * gas/i386/intelbad.s, gas/i386/intelok.s: Add 'bound' tests. * gas/i386/intelbad.l, gas/i386/intelok.l, gas/i386/intelok.e, gas/i386/opcode-intel.d: Adjust. opcodes/ 2008-02-13 Jan Beulich <jbeulich@novell.com> * i386-dis.c (a_mode): New. (cond_jump_mode): Adjust. (Ma): Change to a_mode. (intel_operand_size): Handle a_mode. * i386-opc.tbl: Allow Dword and Qword for bound. * i386-tbl.h: Re-generate.
2008-02-12gas/testsuite/H.J. Lu1-0/+7
2002-02-11 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run xsave, xsave-intel, x86-64-xsave and x86-64-xsave-intel. * gas/i386/x86-64-xsave-intel.d: New file. * gas/i386/x86-64-xsave.d: Likewise. * gas/i386/x86-64-xsave.s: Likewise. * gas/i386/xsave-intel.d: Likewise. * gas/i386/xsave.d: Likewise. * gas/i386/xsave.s: Likewise. opcodes/ 2008-02-11 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flags): Add CpuXsave. * i386-opc.h (CpuXsave): New. (Cpu64): Updated. (i386_cpu_flags): Add cpuxsave. * i386-dis.c (MOD_0FAE_REG_4): New. (RM_0F01_REG_2): Likewise. (MOD_0FAE_REG_5): Updated. (RM_0F01_REG_3): Likewise. (reg_table): Use MOD_0FAE_REG_4. (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated for xrstor. (rm_table): Add RM_0F01_REG_2. * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2008-02-11opcodes/Jan Beulich1-61/+61
2008-02-11 Jan Beulich <jbeulich@novell.com> * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz). * i386-tbl.h: Re-generate.
2008-01-22gas/H.J. Lu1-19/+19
2008-01-22 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (i386_target_format): Remove cpummx2. gas/testsuite/ 2008-01-22 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-10.d: New. * gas/i386/arch-11.s: Likewise. * gas/i386/arch-12.d: Likewise. * gas/i386/arch-12.s: Likewise. * gas/i386/i386.exp: Run arch-11 and arch-12. opcodes/ 2008-01-22 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Remove CpuMMX2. (cpu_flags): Likewise. * i386-opc.h (CpuMMX2): Removed. (CpuSSE): Updated. * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2008-01-16gas/testsuite/H.J. Lu1-1/+1
2008-01-15 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/prescott.s: Add tests for movddup in Intel syntax. * gas/i386/x86-64-prescott.s: Likewise. * gas/i386/prescott.d: Updated. * gas/i386/x86-64-prescott.d: Likewise. opcodes/ 2008-01-15 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Use Qword on movddup. * i386-tbl.h: Regenerated.
2008-01-15gas/H.J. Lu1-0/+3
2008-01-15 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (md_assemble): Also zap movzx and movsx suffix for AT&T syntax. gas/testsuite/ 2008-01-15 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.s: Add more tests for movsx and movzx. * gas/i386/x86_64.s: Likewise. * gas/i386/inval.s: Remove tests for movsxw and movzxw. * gas/i386/x86-64-inval.s: Remove tests for movsxb, movsxw, movsxl, movzxb and movzxw. * gas/i386/i386.d: Updated. * gas/i386/inval.l: Likewise. * gas/i386/x86_64.d: Likewise. * gas/i386/x86-64-inval.l: Likewise. opcodes/ 2008-01-15 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax. * i386-tbl.h: Regenerated.
2008-01-15gas/H.J. Lu1-127/+134
2008-01-14 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (match_reg_size): New. (match_mem_size): Likewise. (operand_size_match): Likewise. (operand_type_match): Also clear all size fields. (match_template): Skip Intel syntax when in AT&T syntax. Call operand_size_match to check operand size. (i386_att_operand): Set the mem field to 1 for memory operand. (i386_intel_operand): Likewise. gas/testsuite/ 2008-01-14 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.s: Add tests for movsx, movzx and movnti. * gas/i386/inval.s: Likewise. * gas/i386/x86_64.s: Likewise. * gas/i386/x86-64-inval.s: Likewise. * gas/i386/i386.d: Updated. * gas/i386/inval.l: Likewise. * gas/i386/x86_64.d: Likewise. * gas/i386/x86-64-inval.l: Likewise. opcodes/ 2008-01-14 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Add IntelSyntax. (operand_types): Add Mem. * i386-opc.h (IntelSyntax): New. * i386-opc.h (Mem): New. (Byte): Updated. (Opcode_Modifier_Max): Updated. (i386_opcode_modifier): Add intelsyntax. (i386_operand_type): Add mem. * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more instructions. * i386-reg.tbl: Add size for accumulator. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2008-01-12gas/testsuite/H.J. Lu1-1003/+1000
2008-01-12 H.J. Lu <hongjiu.lu@intel.com> PR gas/5534 * gas/i386/i386.s: Add tests for fnstsw and fstsw. * gas/i386/inval.s: Likewise. * gas/i386/x86_64.s: Likewise. * gas/i386/intel.s: Use word instead of dword on ss. * gas/i386/x86-64-inval.s: Add tests for fnstsw, fstsw, in and out. * gas/i386/prefix.s: Remove invalid fstsw. * gas/i386/inval.l: Updated. * gas/i386/intelbad.l: Likewise. * gas/i386/i386.d: Likewise. * gas/i386/x86_64.d: Likewise. * gas/i386/x86-64-inval.l: Likewise. * gas/i386/prefix.d: Updated. gas/ 2008-01-12 H.J. Lu <hongjiu.lu@intel.com> PR gas/5534 * config/tc-i386.c (_i386_insn): Update comment. (operand_type_match): Also clear unspecified. (operand_type_register_match): Likewise. (parse_operands): Initialize unspecified. (i386_intel_operand): Likewise. (match_template): Check memory and accumulator operand size. (i386_att_operand): Clear unspecified on register operand. (intel_e11): Likewise. (intel_e09): Set operand size and clean unspecified for "XXX PTR". opcodes/ 2008-01-12 H.J. Lu <hongjiu.lu@intel.com> PR gas/5534 * i386-gen.c (operand_type_init): Add Dword to OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64. (opcode_modifiers): Remove CheckSize, Byte, Word, Dword, Qword and Xmmword. (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte, Xmmword, Unspecified and Anysize. (set_bitfield): Make Mmword an alias of Qword. Make Oword an alias of Xmmword. * i386-opc.h (CheckSize): Removed. (Byte): Updated. (Word): Likewise. (Dword): Likewise. (Qword): Likewise. (Xmmword): Likewise. (FWait): Updated. (OTMax): Likewise. (i386_opcode_modifier): Remove checksize, byte, word, dword, qword and xmmword. (Fword): New. (TBYTE): Likewise. (Unspecified): Likewise. (Anysize): Likewise. (i386_operand_type): Add byte, word, dword, fword, qword, tbyte xmmword, unspecified and anysize. * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword, Tbyte, Xmmword, Unspecified and Anysize. * i386-reg.tbl: Add size for accumulator. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2008-01-05gas/H.J. Lu1-40/+48
2008-01-05 H.J. Lu <hongjiu.lu@intel.com> * doc/c-i386.texi: Update .att_mnemonic and .intel_mnemonic. * config/tc-i386.c (set_intel_mnemonic): Set intel_mnemonic only. (md_assemble): Remove Intel mode workaround. (match_template): Check support for old gcc, AT&T mnemonic and Intel Syntax. (md_parse_option): Don't set intel_mnemonic to 0 for OPTION_MOLD_GCC. gas/testsuite/ 2008-01-05 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/intel.s: Add tests for fadd, faddp, fdiv, fdivp, fdivr, fdivrp, fmul, fmulp, fsub, fsubp, fsubr and fsubrp. * gas/i386/intel.d: Updated. * gas/i386/intel.e: Likewise. opcodes/ 2008-01-05 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to ATTSyntax. * i386-opc.h (IntelMnemonic): Renamed to .. (ATTSyntax): This (Opcode_Modifier_Max): Updated. (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax and intelsyntax. * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp. * i386-tbl.h: Regenerated.
2008-01-042008-01-04 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu1-1/+1
* i386-gen.c: Update copyright to 2008. * i386-opc.h: Likewise. * i386-opc.tbl: Likewise. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2008-01-04gas/testsuite/H.J. Lu1-12/+12
2008-01-04 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/rexw.d: New. * gas/i386/rexw.s: Likewise. * gas/i386/x86-64-sse4_1-intel.d: Updated. * gas/i386/x86-64-sse4_1.d: Likewise. opcodes/ 2008-01-04 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps, pextrb, pextrw, pinsrb, pinsrw and pmovmskb. * i386-tbl.h: Regenerated.
2008-01-04gas/H.J. Lu1-22/+22
2008-01-03 H.J. Lu <hongjiu.lu@intel.com> * gas/config/tc-i386.c (cpu_arch_flags_not): Removed. (cpu_flags_not): Likewise. (cpu_flags_match): Updated to check 64bit and arch. (set_code_flag): Remove cpu_arch_flags_not. (set_16bit_gcc_code_flag): Likewise. (set_cpu_arch): Likewise. (md_begin): Likewise. (parse_insn): Call cpu_flags_match to check 64bit and arch. (match_template): Likewise. gas/testsuite/ 2008-01-03 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-9.d: New file. * gas/i386/arch-9.s: Likewise. * gas/i386/i386.exp: Run arch-9. opcodes/ 2008-01-03 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and CpuSSE4_2_Or_ABM. (cpu_flags): Likewise. * i386-opc.h (CpuSSE4_1_Or_5): Removed. (CpuSSE4_2_Or_ABM): Likewise. (CpuLM): Updated. (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm. * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2 and CpuPadLock, respectively. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2008-01-03gas/testsuite/H.J. Lu1-1/+1
2008-01-02 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-5.d: New file. * gas/i386/arch-5.s: Likewise. * gas/i386/arch-6.d: Likewise. * gas/i386/arch-6.s: Likewise. * gas/i386/arch-7.d: Likewise. * gas/i386/arch-7.s: Likewise. * gas/i386/arch-8.d: Likewise. * gas/i386/arch-8.s: Likewise. * gas/i386/i386.exp: Run arch-5, arch-6, arch-7 and arch-8. opcodes/ 2008-01-02 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and CPU_SSE5_FLAGS. (cpu_flags): Add CpuSSE4_2_Or_ABM. * i386-opc.h (CpuSSE4_2_Or_ABM): New. (CpuLM): Updated. (i386_cpu_flags): Add cpusse4_2_or_abm. * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of CpuABM|CpuSSE4_2 on popcnt. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2008-01-03Fix a typo.H.J. Lu1-1/+1
2008-01-022008-01-02 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu1-8/+8
* i386-gen.c (opcode_modifiers): Use Qword instead of QWord. * i386-opc.h: Likewise. * i386-opc.tbl: Likewise.
2008-01-02gas/H.J. Lu1-8/+8
2008-01-02 H.J. Lu <hongjiu.lu@intel.com> PR gas/5534 * config/tc-i386.c (match_template): Handle XMMWORD_MNEM_SUFFIX. Check memory size in Intel mode. (process_suffix): Handle XMMWORD_MNEM_SUFFIX. (intel_e09): Likewise. * config/tc-i386.h (XMMWORD_MNEM_SUFFIX): New. gas/testsuite/ 2008-01-02 H.J. Lu <hongjiu.lu@intel.com> PR gas/5534 * gas/i386/intel.s: Use QWORD on movq instead of DWORD. * gas/i386/inval.s: Add tests for movq. * gas/i386/x86-64-inval.s: Likewise. * gas/i386/inval.l: Updated. * gas/i386/x86-64-inval.l: Likewise. opcodes/ 2008-01-02 H.J. Lu <hongjiu.lu@intel.com> PR gas/5534 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize, Byte, Word, Dword, QWord and Xmmword. * i386-opc.h (No_xSuf): New. (CheckSize): Likewise. (Byte): Likewise. (Word): Likewise. (Dword): Likewise. (QWord): Likewise. (Xmmword): Likewise. (FWait): Updated. (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word, Dword, QWord and Xmmword. * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is used. * i386-tbl.h: Regenerated.
2007-12-31gas/testsuite/H.J. Lu1-2/+2
2007-12-31 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/inval.s: Add test for cvtsi2ss/cvtsi2sd. * gas/i386/simd.s: Likewise. * gas/i386/x86-64-simd.s: Likewise. * gas/i386/inval.l: Updated. * gas/i386/simd-intel.d: Likewise. * gas/i386/simd-suffix.d: Likewise. * gas/i386/simd.d: Likewise. * gas/i386/sse2.d: Likewise. * gas/i386/x86-64-opcode.d: Likewise. * gas/i386/x86-64-simd-intel.d: Likewise. * gas/i386/x86-64-simd-suffix.d: Likewise. * gas/i386/x86-64-simd.d: Likewise. opcodes/ 2007-12-31 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (prefix_table): Use "%LQ" on cvtpi2ps/cvtsi2sd. (putop): Handle '%' and "LQ". * i386-opc.tbl: Remove IgnoreSize from cvtpi2ps/cvtsi2sd. * i386-tbl.h: Regenerated.
2007-12-28gas/testsuite/H.J. Lu1-5/+5
2007-12-28 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-1.d: New file. * gas/i386/arch-1.s: Likewise. * gas/i386/arch-2.d: Likewise. * gas/i386/arch-2.s: Likewise. * gas/i386/arch-3.d: Likewise. * gas/i386/arch-3.s: Likewise. * gas/i386/arch-4.d: Likewise. * gas/i386/arch-4.s: Likewise. * gas/i386/i386.exp: Run arch-1, arch-2, arch-3 and arch-4. opcodes/ 2007-12-28 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Add CpuSSE4_1_Or_5 to CPU_SSE4_1_FLAGS, CPU_SSE4_2_FLAGS and CPU_SSE5_FLAGS. (cpu_flags): Add CpuSSE4_1_Or_5. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. * i386-opc.h (CpuSSE4_1_Or_5): New. (CpuLM): Updated. (i386_cpu_flags): Add cpusse4_1_or_5. * i386-opc.tbl: Use CpuSSE4_1_Or_5 instead of CpuSSE4_1|CpuSSE5 on ptest roundpd, roundps, roundsd and roundss.
2007-12-24gas/H.J. Lu1-78/+42
2007-12-23 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (set_intel_mnemonic): New. (intel_mnemonic): Likewise. (old_gcc): Likewise. (OPTION_MMNEMONIC): Likewise. (OPTION_MSYNTAX): Likewise. (OPTION_MINDEX_REG): Likewise. (OPTION_MNAKED_REG): Likewise. (OPTION_MOLD_GCC): Likewise. (md_pseudo_table): Add .intel_mnemonic and .att_mnemonic. (match_template): Don't allow AT&T/Intel mnemonic if Intel/AT&T mnemonic is specified. Don't allow old gcc support if old_gcc is 0. (md_longopts): Add -mmnemonic, -msyntax, -mindex-reg, -mmnaked-reg and -mold-gcc. (md_parse_option): Handle OPTION_MMNEMONIC, OPTION_MSYNTAX, OPTION_MINDEX_REG, OPTION_MNAKED_REG and OPTION_MOLD_GCC. * doc/c-i386.texi: Docoument -mmnemonic, -msyntax, --mnaked-reg and AT&T mnemonic vs. Intel mnemonic. gas/testsuite/ 2007-12-23 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/compat-intel.d: Pass -mmnemonic=att to assembler. * gas/i386/compat.d: Likewise. * gas/i386/i386.exp: Pass -mmnemonic=att to assembler for "float". Pass -mold-gcc to assembler for "general". opcodes/ 2007-12-23 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Add OldGcc, ATTMnemonic and IntelMnemonic. * i386-opc.h (OldGcc): New. (ATTMnemonic): Likewise. (IntelMnemonic): Likewise. (Opcode_Modifier_Max): Updated. (i386_opcode_modifier): Add oldgcc, attmnemonic and intelmnemonic. * i386-opc.tbl: Update fadd, fdiv, fdivp, fdivr, fdivrp, fmul, fsub, fsubp, fsubr and fsubrp with OldGcc, ATTMnemonic and IntelMnemonic. * i386-tbl.h: Regeneratd.
2007-11-01gas/H.J. Lu1-1455/+1455
2007-11-01 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (md_assemble): Replace no_xsuf with no_ldsuf. (match_template): Likewise. opcodes/ 2007-11-01 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Replace No_xSuf with No_ldSuf. * i386-opc.tbl: Likewise. * i386-opc.h (No_xSuf): Renamed to ... (No_ldSuf): This. (FWait): Updated.
2007-11-01gas/H.J. Lu1-12/+12
2007-11-01 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_suffix): Check addrprefixop0 to see if the address size override prefix changes the size of the first operand. (check_byte_reg): Don't warn if byteokintel is set. (check_long_reg): Set i.suffix to QWORD_MNEM_SUFFIX if toqword is set. (check_qword_reg): Set i.suffix to LONG_MNEM_SUFFIX if todword is set. gas/testsuite/ 2007-11-01 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.d: New. * gas/i386/i386.s: Likewise. * gas/i386/i386.exp: Run i386. * gas/i386/x86_64.s: Add tests for movsx, movsbl, movsbq, movsbw, movswl, movswq, movzx, movzb, movzbl, movzbq, movzbw, movzwl and movzwq. * gas/i386/x86_64.d: Updated. opcodes/ 2007-11-01 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Add ByteOkIntel, ToDword, ToQword and AddrPrefixOp0. * i386-opc.h (ByteOkIntel): New. (ToDword): Likewise. (ToQword): Likewise. (AddrPrefixOp0): Likewise. (IsPrefix): Updated. (i386_opcode_modifier): Add byteokintel, todword, toqword and addrprefixop0. * i386-opc.tbl (cvtss2si): Add ToQword. (cvttss2si): Likewise. (cvtsd2si): Add ToDword. (cvttsd2si): Likewise. (monitor): Add AddrPrefixOp0. (invlpga): Likewise. (vmload): Likewise. (vmrun): Likewise. (vmsave): Likewise. (pextrb): Add ByteOkIntel. (pinsrb): Likewise. * i386-tbl.h: Regenerated.
2007-10-12gas/H.J. Lu1-3/+3
2007-10-12 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_operands): Check the firstxmm0 field in opcode_modifier for instruction with a implicit xmm0 as the first operand. opcodes/ 2007-10-12 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Add FirstXmm0. * i386-opc.h (FirstXmm0): New. (IsPrefix): Updated. (i386_opcode_modifier): Add firstxmm0. * i386-opc.tbl (blendvpd): Replace RegKludge with FirstXmm0. (blendvps): Likewise. (pblendvb): Likewise. * i386-tbl.h: Regenerated.
2007-10-05gas/testsuite/H.J. Lu1-0/+5
2007-10-05 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run smx. * gas/i386/smx.d: New. * gas/i386/smx.s: Likewise. opcodes/ 2007-10-05 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (dis386_twobyte): Add getsec. * i386-gen.c (cpu_flags): Add CpuSMX. * i386-opc.h (CpuSMX): New. (CpuSSSE3): Updated. (i386_cpu_flags): Add cpusmx. * i386-opc.tbl: Add getsec. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2007-10-032007-10-03 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu1-6/+6
* i386-opc.tbl: Update SSE comments.
2007-09-26gas/H.J. Lu1-1460/+1460
2007-09-25 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (output_insn): Use i.tm.opcode_length to check opcode length. opcodes/ 2007-09-25 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (process_i386_opcodes): Process opcode_length. * i386-opc.h (template): Add opcode_length. * 386-opc.tbl: Likewise. * i386-tbl.h: Regenerated.
2007-09-14Add AMD SSE5 supportMichael Meissner1-5/+263
2007-09-12gas/testsuite/Jan Beulich1-0/+3
2007-09-12 Jan Beulich <jbeulich@novell.com> * gas/i386/sse4_1.s, gas/i386/x86-64-sse4_1.s: Add two-operand forms of blendvps, blendvpd, and pblendvb. * gas/i386/sse4_1.d, gas/i386/sse4_1-intel.d, gas/i386/x86-64-sse4_1.d, gas/i386/x86-64-sse4_1-intel.d: Adjust, making last/first operand of blendvps, blendvpd, and pblendvb optional. opcodes/ 2007-09-12 Jan Beulich <jbeulich@novell.com> * i386-opc.tbl: Add two-operand forms of blendvps, blendvpd, and pblendvb. * i386-tbl.h: Regenerate.
2007-09-06gas/H.J. Lu1-16/+8
2007-09-06 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (match_template): Handle invlpga, vmload, vmrun and vmsave in SVME. (process_suffix): Likewise. gas/testsuite/ 2007-09-06 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/svme.s: Updated to allow eax in 64bit. * gas/i386/svme.d: Updated. * gas/i386/svme64.d: Likewise. opcodes/ 2007-09-06 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Correct SVME instructions to allow 32bit register operand in 64bit mode. * i386-tbl.h: Regenerated.
2007-08-31gas/testsuite/H.J. Lu1-6/+18
2007-08-31 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/svme.s: Updated to accept eax in 32bit and rax in 64bit. * gas/i386/svme.d: Updated. * gas/i386/svme64.d: Likewise. opcodes/ 2007-08-31 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (SVME_Fixup): Removed. (OPC_EXT_39): New. (OPC_EXT_RM_6): Likewise. (grps): Use OPC_EXT_39. (opc_ext_table): Add OPC_EXT_39. (opc_ext_rm_table): Add OPC_EXT_RM_6. * i386-opc.tbl: Correct SVME instructions to take register operand only. * i386-tbl.h: Regenerated.
2007-08-09gas/H.J. Lu1-7/+7
2007-08-09 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (check_byte_reg): Support pextrb and pinsrb. gas/testsuite/ 2007-08-09 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run sse4_1-intel, sse4_2-intel, x86-64-sse4_1-intel and x86-64-sse4_2-intel. * gas/i386/sse4_1-intel.d: New file. * gas/i386/sse4_2-intel.d: Likewise. * gas/i386/x86-64-sse4_1-intel.d: Likewise. * gas/i386/x86-64-sse4_2-intel.d: Likewise. * gas/i386/sse4_1.s: Add tests for Intel syntax. * gas/i386/sse4_2.s: Likewise. * gas/i386/x86-64-sse4_1.s: Likewise. * gas/i386/x86-64-sse4_2.s: Likewise. * gas/i386/sse4_1.d: Updated. * gas/i386/sse4_2.d: Likewise. * gas/i386/x86-64-sse4_1.d: Likewise. * gas/i386/x86-64-sse4_2.d: Likewise. opcodes/ 2007-08-09 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add NoRex64 to pmovsxbw, pmovsxwd, pmovsxdq, pmovzxbw, pmovzxwd, pmovzxdq and roundsd. * i386-tbl.h: Regenerated.
2007-07-05Change source files over to GPLv3.Nick Clifton1-0/+19
2007-06-282007-06-28 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu1-0/+1489
* Makefile.am (HFILES): Add i386-opc.h and i386-tbl.h. (CFILES): Add i386-gen.c. (i386-gen): New rule. (i386-gen.o): Likewise. (i386-tbl.h): Likewise. Run "make dep-am". * Makefile.in: Regenerated. * i386-gen.c: New file. * i386-opc.tbl: Likewise. * i386-reg.tbl: Likewise. * i386-tbl.h: Likewise. * i386-opc.c: Include "i386-tbl.h". (i386_optab): Removed. (i386_regtab): Likewise. (i386_regtab_size): Likewise.
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