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AgeCommit message (Expand)AuthorFilesLines
2013-10-12Only allow 32-bit/64-bit registers for bndcl/bndcu/bndcnH.J. Lu1-8/+11
2013-10-08opcodes/Jan Beulich1-9/+9
2013-09-30Add Size64 to movq/vmovq with Reg64 operandH.J. Lu1-8/+8
2013-07-26Add Intel AVX-512 supportH.J. Lu1-0/+1209
2013-07-25Support Intel SHAH.J. Lu1-0/+10
2013-07-24Support Intel MPXH.J. Lu1-41/+54
2013-07-08Replace Xmmword with Qword on cvttps2piH.J. Lu1-1/+1
2013-04-08gas/testsuite/Jan Beulich1-2/+1
2013-02-19Implement Intel SMAP instructionsH.J. Lu1-0/+4
2012-11-20Fix opcode for 64-bit jecxzH.J. Lu1-1/+1
2012-09-20Replace CpuSSE3 with CpuCX16 for cmpxchg16bH.J. Lu1-1/+1
2012-08-17Add AMD btver1 and btver2 supportH.J. Lu1-1/+1
2012-08-07There were several cases where the registers in the REX encoded rangeJan Beulich1-5/+0
2012-07-31VMOVNTDQA was both misplaced and improperly tagged as being an AVXJan Beulich1-1/+1
2012-07-16Implement RDRSEED, ADX and PRFCHW instructionsH.J. Lu1-1/+6
2012-07-02gas/testsuite/Roland McGrath1-1/+1
2012-06-22gas/Roland McGrath1-4/+4
2012-06-22gas/Roland McGrath1-56/+56
2012-02-08Implement Intel Transactional Synchronization ExtensionsH.J. Lu1-40/+51
2012-01-13Add vmfuncH.J. Lu1-0/+4
2011-08-01Add Disp32S to 64bit call.H.J. Lu1-1/+1
2011-06-30Fix rorx in BMI2.H.J. Lu1-1/+1
2011-06-10Support AVX Programming Reference (June, 2011).H.J. Lu1-1/+195
2011-01-17Add support for TBM instructions.Quentin Neill1-0/+12
2011-01-05Implement BMI instructions.H.J. Lu1-0/+9
2010-10-14Remove CheckRegSize from movq.H.J. Lu1-2/+2
2010-10-14Remove CheckRegSize from instructions with 0, 1 or fixed operands.H.J. Lu1-34/+34
2010-10-14Add CheckRegSize to instructions which require register size check.H.J. Lu1-184/+184
2010-08-06Don't generate multi-byte NOPs for i686.H.J. Lu1-1/+1
2010-08-06Add Cpu186 to ud1/ud2/ud2a/ud2b.H.J. Lu1-4/+4
2010-08-06Add ud1 to x86.H.J. Lu1-3/+5
2010-07-05Replace rdrnd with rdrand.H.J. Lu1-1/+1
2010-07-01Support AVX Programming Reference (June, 2010)H.J. Lu1-0/+16
2010-03-232010-03-22 Sebastian Pop <sebastian.pop@amd.com>Sebastian Pop1-8/+4
2010-02-11Update copyright.H.J. Lu1-1/+1
2010-02-112010-02-10 Quentin Neill <quentin.neill@amd.com>Sebastian Pop1-0/+10
2010-01-24Replace "Vex" with "Vex=3" on AVX scalar instructions.H.J. Lu1-208/+208
2010-01-21Add xsave64 and xrstor64.H.J. Lu1-0/+2
2010-01-152010-01-15 Sebastian Pop <sebastian.pop@amd.com>Sebastian Pop1-0/+64
2009-12-19Replace VexNDS, VexNDD and VexLWP with VexVVVV.H.J. Lu1-844/+844
2009-12-16Remove ByteOkIntel.H.J. Lu1-6/+6
2009-12-16Replace Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A with VexOpcode.H.J. Lu1-1154/+1154
2009-12-16Replace Vex2Sources and Vex3Sources with VexSources.H.J. Lu1-121/+121
2009-12-16Remove VexW0 and VexW1. Add VexW.H.J. Lu1-1101/+1101
2009-12-15Add USE_VEX_W_TABLE, VEX_W_TABLE and VEX_W_XXX.H.J. Lu1-869/+869
2009-12-04Support fxsave64 and fxrstor64.H.J. Lu1-0/+2
2009-11-19Allow lock on cmpxch16b.H.J. Lu1-1/+1
2009-11-182009-11-18 Sebastian Pop <sebastian.pop@amd.com>Sebastian Pop1-7/+0
2009-11-182009-11-17 Sebastian Pop <sebastian.pop@amd.com>Sebastian Pop1-0/+85
2009-11-122009-11-12 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu1-11/+11
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