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AgeCommit message (Expand)AuthorFilesLines
2018-03-08x86-64: Also optimize "clr reg64"H.J. Lu1-1/+1
2018-03-08x86: Remove support for old (<= 2.8.1) versions of gccH.J. Lu1-8/+0
2018-03-08x86: fold several AVX512VL templatesJan Beulich1-185/+90
2018-03-08x86: fold certain AVX512 rotate and shift templatesJan Beulich1-84/+45
2018-03-08x86: fold VEX-encoded GFNI templatesJan Beulich1-8/+3
2018-03-08x86: fold a few AVX512F templatesJan Beulich1-24/+12
2018-03-08x86: fold LWP templatesJan Beulich1-8/+4
2018-03-08x86: fold FMA and FMA4 templatesJan Beulich1-120/+60
2018-03-08x86: drop {X,Y,Z}MMWORD_MNEM_SUFFIXJan Beulich1-1/+1
2018-03-08x86: drop bogus NoAVXJan Beulich1-7/+7
2018-03-08x86: avoid SSE check for LDMXCSR/STMXCSRJan Beulich1-2/+2
2018-03-08x86: drop FloatDJan Beulich1-10/+10
2018-03-08x86: bogus VMOVD with 64-bit operands should only allow for registersJan Beulich1-2/+2
2018-03-08x86: fold AVX vcvtpd2ps memory formsJan Beulich1-2/+1
2018-03-01x86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128H.J. Lu1-12/+12
2018-02-27x86: Add -O[2|s] assembler command-line optionsH.J. Lu1-32/+33
2018-02-22x86: Add {rex} pseudo prefixH.J. Lu1-0/+1
2018-01-23Enable Intel PCONFIG instruction.Igor Tsimbalist1-0/+6
2018-01-23Enable Intel WBNOINVD instruction.Igor Tsimbalist1-0/+6
2018-01-17Replace CET bit with IBT and SHSTK bits.Igor Tsimbalist1-15/+15
2018-01-11Remove VL variants for 4FMAPS and 4VNNIW insns.Igor Tsimbalist1-12/+0
2018-01-10x86: fix Disp8 handling for scalar AVX512_4FMAPS insnsJan Beulich1-2/+2
2018-01-10x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variantsJan Beulich1-48/+48
2018-01-08x86: Properly encode vmovd with 64-bit memeoryH.J. Lu1-4/+2
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-12-18x86: fold certain AVX and AVX2 templatesJan Beulich1-328/+164
2017-12-18x86: fold RegXMM/RegYMM/RegZMM into RegSIMDJan Beulich1-7/+7
2017-12-18x86: replace Reg8, Reg16, Reg32, and Reg64Jan Beulich1-21/+42
2017-12-15x86: drop stray CheckRegSize usesJan Beulich1-81/+81
2017-11-30x86: derive DispN from BaseIndexJan Beulich1-4113/+4113
2017-11-30x86: drop Vec_Disp8Jan Beulich1-2034/+2034
2017-11-23Add Disp8MemShift for AVX512 VAES instructions.Igor Tsimbalist1-12/+12
2017-11-23x86: correct UDnJan Beulich1-2/+4
2017-11-22Remove Vec_Disp8 field for vgf2p8mulb for AVX flavor.Igor Tsimbalist1-2/+2
2017-11-22Remove Vec_Disp8 from vpcompressb and vpexpandb.Igor Tsimbalist1-7/+6
2017-11-14x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich1-19/+91
2017-11-14x86: string insns don't allow displacementsJan Beulich1-19/+19
2017-11-13x86: {f,}xsave64 / {f,}xrstor64 / xsaveopt64 should not allow q suffixJan Beulich1-5/+5
2017-10-23Enable Intel AVX512_BITALG instructions.Igor Tsimbalist1-0/+20
2017-10-23Enable Intel AVX512_VNNI instructions.Igor Tsimbalist1-0/+20
2017-10-23Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist1-0/+14
2017-10-23Enable Intel VAES instructions.Igor Tsimbalist1-0/+24
2017-10-23Enable Intel GFNI instructions.Igor Tsimbalist1-0/+36
2017-10-23Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist1-0/+75
2017-06-21x86: CET v2.0: Update incssp and setssbsyH.J. Lu1-3/+3
2017-06-21x86: CET v2.0: Rename savessp to saveprevsspH.J. Lu1-1/+1
2017-05-22x86: Add NOTRACK prefix supportH.J. Lu1-6/+9
2017-03-09X86: Add pseudo prefixes to control encodingH.J. Lu1-68/+78
2017-03-09Use CpuCET on rdsspqH.J. Lu1-1/+1
2017-03-06Add support for Intel CET instructionsH.J. Lu1-0/+19
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