| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2014-02-25 | Remove bogus vcvtps2ph variant. | Ilya Tocar | 1 | -1/+0 |
| 2014-02-21 | Add support for CPUID PREFETCHWT1 | Ilya Tocar | 1 | -2/+6 |
| 2014-02-20 | Change cpu for vptestnmd and vptestnmq instructions. | Ilya Tocar | 1 | -4/+3 |
| 2014-02-12 | Add clflushopt, xsaves, xsavec, xrstors | Ilya Tocar | 1 | -0/+22 |
| 2013-10-12 | Only allow 32-bit/64-bit registers for bndcl/bndcu/bndcn | H.J. Lu | 1 | -8/+11 |
| 2013-10-08 | opcodes/ | Jan Beulich | 1 | -9/+9 |
| 2013-09-30 | Add Size64 to movq/vmovq with Reg64 operand | H.J. Lu | 1 | -8/+8 |
| 2013-07-26 | Add Intel AVX-512 support | H.J. Lu | 1 | -0/+1209 |
| 2013-07-25 | Support Intel SHA | H.J. Lu | 1 | -0/+10 |
| 2013-07-24 | Support Intel MPX | H.J. Lu | 1 | -41/+54 |
| 2013-07-08 | Replace Xmmword with Qword on cvttps2pi | H.J. Lu | 1 | -1/+1 |
| 2013-04-08 | gas/testsuite/ | Jan Beulich | 1 | -2/+1 |
| 2013-02-19 | Implement Intel SMAP instructions | H.J. Lu | 1 | -0/+4 |
| 2012-11-20 | Fix opcode for 64-bit jecxz | H.J. Lu | 1 | -1/+1 |
| 2012-09-20 | Replace CpuSSE3 with CpuCX16 for cmpxchg16b | H.J. Lu | 1 | -1/+1 |
| 2012-08-17 | Add AMD btver1 and btver2 support | H.J. Lu | 1 | -1/+1 |
| 2012-08-07 | There were several cases where the registers in the REX encoded range | Jan Beulich | 1 | -5/+0 |
| 2012-07-31 | VMOVNTDQA was both misplaced and improperly tagged as being an AVX | Jan Beulich | 1 | -1/+1 |
| 2012-07-16 | Implement RDRSEED, ADX and PRFCHW instructions | H.J. Lu | 1 | -1/+6 |
| 2012-07-02 | gas/testsuite/ | Roland McGrath | 1 | -1/+1 |
| 2012-06-22 | gas/ | Roland McGrath | 1 | -4/+4 |
| 2012-06-22 | gas/ | Roland McGrath | 1 | -56/+56 |
| 2012-02-08 | Implement Intel Transactional Synchronization Extensions | H.J. Lu | 1 | -40/+51 |
| 2012-01-13 | Add vmfunc | H.J. Lu | 1 | -0/+4 |
| 2011-08-01 | Add Disp32S to 64bit call. | H.J. Lu | 1 | -1/+1 |
| 2011-06-30 | Fix rorx in BMI2. | H.J. Lu | 1 | -1/+1 |
| 2011-06-10 | Support AVX Programming Reference (June, 2011). | H.J. Lu | 1 | -1/+195 |
| 2011-01-17 | Add support for TBM instructions. | Quentin Neill | 1 | -0/+12 |
| 2011-01-05 | Implement BMI instructions. | H.J. Lu | 1 | -0/+9 |
| 2010-10-14 | Remove CheckRegSize from movq. | H.J. Lu | 1 | -2/+2 |
| 2010-10-14 | Remove CheckRegSize from instructions with 0, 1 or fixed operands. | H.J. Lu | 1 | -34/+34 |
| 2010-10-14 | Add CheckRegSize to instructions which require register size check. | H.J. Lu | 1 | -184/+184 |
| 2010-08-06 | Don't generate multi-byte NOPs for i686. | H.J. Lu | 1 | -1/+1 |
| 2010-08-06 | Add Cpu186 to ud1/ud2/ud2a/ud2b. | H.J. Lu | 1 | -4/+4 |
| 2010-08-06 | Add ud1 to x86. | H.J. Lu | 1 | -3/+5 |
| 2010-07-05 | Replace rdrnd with rdrand. | H.J. Lu | 1 | -1/+1 |
| 2010-07-01 | Support AVX Programming Reference (June, 2010) | H.J. Lu | 1 | -0/+16 |
| 2010-03-23 | 2010-03-22 Sebastian Pop <sebastian.pop@amd.com> | Sebastian Pop | 1 | -8/+4 |
| 2010-02-11 | Update copyright. | H.J. Lu | 1 | -1/+1 |
| 2010-02-11 | 2010-02-10 Quentin Neill <quentin.neill@amd.com> | Sebastian Pop | 1 | -0/+10 |
| 2010-01-24 | Replace "Vex" with "Vex=3" on AVX scalar instructions. | H.J. Lu | 1 | -208/+208 |
| 2010-01-21 | Add xsave64 and xrstor64. | H.J. Lu | 1 | -0/+2 |
| 2010-01-15 | 2010-01-15 Sebastian Pop <sebastian.pop@amd.com> | Sebastian Pop | 1 | -0/+64 |
| 2009-12-19 | Replace VexNDS, VexNDD and VexLWP with VexVVVV. | H.J. Lu | 1 | -844/+844 |
| 2009-12-16 | Remove ByteOkIntel. | H.J. Lu | 1 | -6/+6 |
| 2009-12-16 | Replace Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A with VexOpcode. | H.J. Lu | 1 | -1154/+1154 |
| 2009-12-16 | Replace Vex2Sources and Vex3Sources with VexSources. | H.J. Lu | 1 | -121/+121 |
| 2009-12-16 | Remove VexW0 and VexW1. Add VexW. | H.J. Lu | 1 | -1101/+1101 |
| 2009-12-15 | Add USE_VEX_W_TABLE, VEX_W_TABLE and VEX_W_XXX. | H.J. Lu | 1 | -869/+869 |
| 2009-12-04 | Support fxsave64 and fxrstor64. | H.J. Lu | 1 | -0/+2 |
