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path: root/opcodes/i386-opc.tbl
AgeCommit message (Expand)AuthorFilesLines
2023-08-02Revert "2.41 Release sources"Sam James1-9/+48
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton1-48/+9
2023-07-27Support Intel PBNDKBHu, Lin11-0/+6
2023-07-27Support Intel SM4Haochen Jiang1-0/+7
2023-07-27Support Intel SM3Haochen Jiang1-0/+7
2023-07-27Support Intel SHA512Haochen Jiang1-0/+8
2023-07-27Support Intel AVX-VNNI-INT16konglin11-0/+11
2023-07-04x86: optimize 128-bit VPBROADCASTQ to VPUNPCKLQDQJan Beulich1-1/+1
2023-07-04x86: optimize pre-AVX512 {,V}PCMPGT* with identical sourcesJan Beulich1-6/+6
2023-07-04x86: optimize pre-AVX512 {,V}PCMPEQQ with identical sourcesJan Beulich1-2/+2
2023-06-16x86: shrink Masking insn attribute to a single bit (boolean)Jan Beulich1-569/+568
2023-05-23Support Intel FRED LKGSZhang, Jun1-0/+14
2023-05-23Revert "Support Intel FRED LKGS"liuhongt1-14/+0
2023-05-23Support Intel FRED LKGSZhang, Jun1-0/+14
2023-04-07Support Intel AMX-COMPLEXHaochen Jiang1-0/+3
2023-03-20x86: drop "shimm" special case template expansionsJan Beulich1-15/+15
2023-03-20x86: VexVVVV is now merely a booleanJan Beulich1-194/+196
2023-03-20x86: re-work build_modrm_byte()'s register assignmentJan Beulich1-13/+13
2023-02-24x86: MONITOR/MWAIT are not SSE3 insnsJan Beulich1-5/+5
2023-02-24x86-64: don't permit LAHF/SAHF with "generic64"Jan Beulich1-2/+4
2023-02-24x86: have insns acting on segment selector values allow for consistent operandsJan Beulich1-5/+10
2023-02-24x86: restrict insn templates accepting negative 8-bit immediatesJan Beulich1-58/+58
2023-02-22x86-64: LAR and LSL don't need REX.WJan Beulich1-4/+4
2023-02-22x86: optimize BT{,C,R,S} $imm,%regJan Beulich1-4/+4
2023-02-14x86: {LD,ST}TILECFG use an extension opcodeJan Beulich1-2/+2
2023-02-13PR30120: fix x87 fucomp misassembledMichael Matz1-1/+1
2023-02-10x86: drop use of VEX3SOURCESJan Beulich1-32/+32
2023-02-10x86: drop use of XOP2SOURCESJan Beulich1-3/+3
2023-02-10x86: limit use of XOP2SOURCESJan Beulich1-1/+1
2023-01-27x86: use ModR/M for FPU insns with operandsJan Beulich1-72/+72
2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2022-12-21x86: rename CheckRegSize to CheckOperandSizeJan Beulich1-507/+507
2022-12-19x86: omit Cpu prefixes from opcode tableJan Beulich1-1874/+1889
2022-12-16x86: change representation of extension opcodeJan Beulich1-2281/+2280
2022-12-12x86: further re-work insn/suffix recognition to also cover MOVSXJan Beulich1-8/+3
2022-12-12x86: drop (now) stray IsStringJan Beulich1-13/+13
2022-12-12x86: re-work insn/suffix recognitionJan Beulich1-15/+4
2022-12-03x86: Allow 16-bit register source for LAR and LSLH.J. Lu1-2/+2
2022-12-02x86: also use D for XCHG and TESTJan Beulich1-6/+3
2022-12-01x86: drop No_ldSufJan Beulich1-445/+445
2022-12-01x86/Intel: drop LONG_DOUBLE_MNEM_SUFFIXJan Beulich1-2/+2
2022-12-01x86/Intel: restrict use of LONG_DOUBLE_MNEM_SUFFIXJan Beulich1-4/+4
2022-11-30x86: clean up after removal of support for gcc <= 2.8.1Jan Beulich1-4/+3
2022-11-30x86: drop FloatRJan Beulich1-8/+4
2022-11-24x86: widen applicability and use of CheckRegSizeJan Beulich1-7/+7
2022-11-24x86: add missing CheckRegSizeJan Beulich1-3/+3
2022-11-24x86: correct handling of LAR and LSLJan Beulich1-2/+4
2022-11-17opcodes: Define NoSuf in i386-opc.tblH.J. Lu1-1847/+1848
2022-11-15Add AMD znver4 processor supportTejas Joshi1-0/+7
2022-11-14x86: fold special-operand insn attributes into a single enumJan Beulich1-2/+11
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