| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2022-11-04 | Support Intel AVX-NE-CONVERT | konglin1 | 1 | -0/+3 |
| 2022-11-02 | Support Intel MSRLIST | Hu, Lin1 | 1 | -0/+3 |
| 2022-11-02 | Support Intel WRMSRNS | Hu, Lin1 | 1 | -0/+3 |
| 2022-11-02 | Support Intel CMPccXADD | Haochen Jiang | 1 | -1/+4 |
| 2022-11-02 | Support Intel AVX-VNNI-INT8 | Cui,Lili | 1 | -1/+4 |
| 2022-11-02 | Support Intel AVX-IFMA | Hongyu Wang | 1 | -0/+3 |
| 2022-10-31 | Support Intel PREFETCHI | Cui, Lili | 1 | -0/+3 |
| 2022-10-21 | Support Intel AMX-FP16 | Cui,Lili | 1 | -0/+3 |
| 2022-10-20 | x86: re-work AVX-VNNI support | Jan Beulich | 1 | -3/+0 |
| 2022-09-30 | x86/Intel: restrict suffix derivation | Jan Beulich | 1 | -6/+0 |
| 2022-08-03 | x86: also use D for MOVBE | Jan Beulich | 1 | -1/+1 |
| 2022-07-18 | x86: re-order insn template fields | Jan Beulich | 1 | -3/+11 |
| 2022-07-06 | x86: make D attribute usable for XOP and FMA4 insns | Jan Beulich | 1 | -0/+3 |
| 2022-07-04 | x86: fold Disp32S and Disp32 | Jan Beulich | 1 | -4/+1 |
| 2022-03-17 | x86: never set i386_cpu_flags' "unused" field | Jan Beulich | 1 | -0/+4 |
| 2022-03-17 | x86: drop L1OM/K1OM support from gas | Jan Beulich | 1 | -6/+0 |
| 2022-01-06 | x86: drop NoAVX insn attribute | Jan Beulich | 1 | -3/+0 |
| 2022-01-02 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
| 2021-08-05 | [PATCH 1/2] Enable Intel AVX512_FP16 instructions | Cui,Lili | 1 | -0/+11 |
| 2021-04-05 | C99 opcodes configury | Alan Modra | 1 | -3/+0 |
| 2021-03-30 | x86: drop seg_entry | Jan Beulich | 1 | -14/+1 |
| 2021-03-30 | x86: drop REGNAM_{AL,AX,EAX} | Jan Beulich | 1 | -5/+0 |
| 2021-03-30 | x86: adjust st(<N>) parsing | Jan Beulich | 1 | -3/+3 |
| 2021-03-29 | x86: shrink some struct insn_template fields | Jan Beulich | 1 | -4/+4 |
| 2021-03-24 | x86: derive opcode length from opcode value | Jan Beulich | 1 | -3/+0 |
| 2021-03-24 | x86: don't use opcode_length to identify pseudo prefixes | Jan Beulich | 1 | -8/+11 |
| 2021-03-23 | x86: re-number PREFIX_0X<nn> | Jan Beulich | 1 | -5/+6 |
| 2021-03-23 | x86: re-order two fields of struct insn_template | Jan Beulich | 1 | -3/+3 |
| 2021-03-23 | x86: split opcode prefix and opcode space representation | Jan Beulich | 1 | -16/+21 |
| 2021-03-09 | x86: fold some prefix related attributes into a single one | Jan Beulich | 1 | -20/+11 |
| 2021-01-01 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
| 2020-10-20 | Add AMD znver3 processor support | Ganesh Gopalasubramanian | 1 | -0/+9 |
| 2020-10-16 | Enhancement for avx-vnni patch | Cui,Lili | 1 | -3/+3 |
| 2020-10-14 | x86: Support Intel AVX VNNI | H.J. Lu | 1 | -0/+6 |
| 2020-10-14 | x86: Add support for Intel HRESET instruction | Lili Cui | 1 | -0/+3 |
| 2020-10-14 | x86: Support Intel UINTR | Lili Cui | 1 | -0/+3 |
| 2020-10-13 | x86: Rename VexOpcode to OpcodePrefix | H.J. Lu | 1 | -2/+12 |
| 2020-09-24 | Add support for Intel TDX instructions. | Cui,Lili | 1 | -0/+3 |
| 2020-09-23 | Enable support to Intel Keylocker instructions | Terry Guo | 1 | -0/+6 |
| 2020-07-30 | x86: Add {disp16} pseudo prefix | H.J. Lu | 1 | -0/+12 |
| 2020-07-10 | x86: Add support for Intel AMX instructions | Lili Cui | 1 | -1/+15 |
| 2020-07-02 | x86: Add SwapSources | H.J. Lu | 1 | -0/+4 |
| 2020-06-26 | x86: Rename VecSIB to SIB for Intel AMX | H.J. Lu | 1 | -6/+6 |
| 2020-06-08 | x86: restrict use of register aliases | Jan Beulich | 1 | -1/+1 |
| 2020-04-07 | Add support for intel TSXLDTRK instructions$ | Cui,Lili | 1 | -0/+3 |
| 2020-04-02 | Add support for intel SERIALIZE instruction | LiliCui | 1 | -0/+3 |
| 2020-03-06 | x86: drop Rex64 attribute | Jan Beulich | 1 | -3/+0 |
| 2020-03-04 | x86: support VMGEXIT | Jan Beulich | 1 | -0/+3 |
| 2020-03-03 | x86: Replace IgnoreSize/DefaultSize with MnemonicSize | H.J. Lu | 1 | -4/+4 |
| 2020-02-17 | x86: Remove CpuABM and add CpuPOPCNT | H.J. Lu | 1 | -6/+6 |
