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path: root/opcodes/i386-opc.h
AgeCommit message (Expand)AuthorFilesLines
2016-11-02Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist1-0/+3
2016-11-02Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist1-0/+9
2016-10-21X86: Remove pcommit instructionH.J. Lu1-3/+0
2016-08-24X86: Add ptwrite instructionH.J. Lu1-0/+3
2016-05-27Update x86 CPU_XXX_FLAGS handlingH.J. Lu1-0/+15
2016-05-27Replace CpuAMD64/CpuIntel64 with AMD64/Intel64H.J. Lu1-7/+7
2016-05-27Correct CpuMax in i386-opc.hH.J. Lu1-1/+1
2016-05-10Enable Intel RDPID instruction.Alexander Fomin1-0/+3
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-12-09Implement Intel OSPKE instructionsH.J. Lu1-0/+3
2015-08-12Remove trailing spaces in opcodesH.J. Lu1-1/+1
2015-06-30Add support for monitorx/mwaitx instructionsAmit Pawar1-0/+3
2015-05-15Support AMD64/Intel ISAs in assembler/disassemblerH.J. Lu1-0/+6
2015-05-11Add Intel MCU support to opcodesH.J. Lu1-0/+3
2015-03-17Add znver1 processorGanesh Gopalasubramanian1-0/+3
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-11-17Add AVX512VBMI instructionsIlya Tocar1-0/+3
2014-11-17Add AVX512IFMA instructionsIlya Tocar1-0/+3
2014-11-17Add pcommit instructionIlya Tocar1-0/+3
2014-11-17Add clwb instructionIlya Tocar1-0/+3
2014-07-22Add AVX512DQ instructions and their AVX512VL variants.Ilya Tocar1-0/+3
2014-07-22Add support for AVX512BW instructions and their AVX512VL versions.Ilya Tocar1-0/+3
2014-07-22Add support for AVX512VL. Add AVX512VL versions of AVX512F instructions.Ilya Tocar1-0/+5
2014-04-04Add support for Intel SGX instructionsIlya Tocar1-0/+3
2014-03-05Update copyright yearsAlan Modra1-2/+1
2014-02-21Add support for CPUID PREFETCHWT1Ilya Tocar1-0/+3
2014-02-12Add clflushopt, xsaves, xsavec, xrstorsIlya Tocar1-0/+9
2013-07-26Add Intel AVX-512 supportH.J. Lu1-0/+91
2013-07-25Support Intel SHAH.J. Lu1-1/+4
2013-07-24Support Intel MPXH.J. Lu1-1/+11
2013-02-19Implement Intel SMAP instructionsH.J. Lu1-0/+3
2012-09-20Replace CpuSSE3 with CpuCX16 for cmpxchg16bH.J. Lu1-0/+3
2012-08-17Add AMD btver1 and btver2 supportH.J. Lu1-1/+1
2012-07-16Implement RDRSEED, ADX and PRFCHW instructionsH.J. Lu1-0/+9
2012-06-22gas/Roland McGrath1-3/+6
2012-02-21Add HLEPrefixNone/HLEPrefixLock/HLEPrefixAny/HLEPrefixReleaseH.J. Lu1-0/+4
2012-02-08Implement Intel Transactional Synchronization ExtensionsH.J. Lu1-0/+13
2012-01-13Add vmfuncH.J. Lu1-0/+3
2011-07-22Add initial Intel K1OM support.H.J. Lu1-0/+3
2011-06-10Support AVX Programming Reference (June, 2011).H.J. Lu1-3/+26
2011-01-17Add support for TBM instructions.Quentin Neill1-0/+3
2011-01-05Implement BMI instructions.H.J. Lu1-0/+3
2010-10-14Add CheckRegSize to instructions which require register size check.H.J. Lu1-0/+3
2010-08-06Don't generate multi-byte NOPs for i686.H.J. Lu1-0/+3
2010-08-06Fix typos in comments in i386-opc.h.H.J. Lu1-6/+6
2010-07-05Fix a typo in comments for CpuFSGSBase.H.J. Lu1-1/+1
2010-07-01Support AVX Programming Reference (June, 2010)H.J. Lu1-0/+12
2010-02-11Update copyright.H.J. Lu1-1/+1
2010-02-112010-02-10 Quentin Neill <quentin.neill@amd.com>Sebastian Pop1-0/+4
2010-01-24Replace "Vex" with "Vex=3" on AVX scalar instructions.H.J. Lu1-2/+4
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