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path: root/opcodes/i386-opc.h
AgeCommit message (Expand)AuthorFilesLines
2019-04-05x86: Support Intel AVX512 BF16Xuepeng Guo1-0/+3
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-10-10x86: fold Size{16,32,64} template attributesJan Beulich1-6/+5
2018-09-14x86: Support VEX/EVEX WIG encodingH.J. Lu1-0/+2
2018-09-13x86: use D attribute also for SIMD templatesJan Beulich1-0/+2
2018-08-11x86: Add CpuCMOV and CpuFXSRH.J. Lu1-0/+6
2018-08-06x86: fold RegEip/RegRip and RegEiz/RegRizJan Beulich1-4/+2
2018-08-03x86: drop "mem" operand type attributeJan Beulich1-1/+0
2018-07-31x86: fold various AVX512 templates with so far differing Masking attributesJan Beulich1-2/+2
2018-07-31x86: drop CpuVREXJan Beulich1-3/+0
2018-07-25x86: Expand Broadcast to 3 bitsH.J. Lu1-1/+12
2018-07-19x86: fold various AVX512VL templates into their AVX512F counterpartsJan Beulich1-1/+2
2018-07-18x86: Split vcvtps2{,u}qq and vcvttps2{,u}qqH.J. Lu1-9/+9
2018-07-11x86: replace off-by-one OTMaxJan Beulich1-4/+4
2018-05-07Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu1-0/+6
2018-05-07x86: Replace AddrPrefixOp0 with AddrPrefixOpRegH.J. Lu1-3/+3
2018-04-27Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist1-24/+0
2018-04-26Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist1-0/+24
2018-04-26x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMaskJan Beulich1-15/+0
2018-04-26x86: drop VexImmExtJan Beulich1-3/+0
2018-04-17Enable Intel CLDEMOTE instruction.Igor Tsimbalist1-0/+3
2018-04-11Enable Intel WAITPKG instructions.Igor Tsimbalist1-0/+3
2018-03-28x86: drop VecESizeJan Beulich1-7/+0
2018-03-28x86: convert broadcast insn attribute to booleanJan Beulich1-11/+1
2018-03-08x86: Remove support for old (<= 2.8.1) versions of gccH.J. Lu1-3/+0
2018-03-08x86: fold several AVX512VL templatesJan Beulich1-0/+2
2018-03-08x86: drop FloatDJan Beulich1-3/+0
2018-02-27x86: Add -O[2|s] assembler command-line optionsH.J. Lu1-0/+4
2018-01-23Enable Intel PCONFIG instruction.Igor Tsimbalist1-0/+3
2018-01-23Enable Intel WBNOINVD instruction.Igor Tsimbalist1-0/+3
2018-01-17Replace CET bit with IBT and SHSTK bits.Igor Tsimbalist1-3/+5
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-12-18x86: fold certain AVX and AVX2 templatesJan Beulich1-1/+1
2017-12-18x86: fold RegXMM/RegYMM/RegZMM into RegSIMDJan Beulich1-13/+4
2017-12-18x86: drop FloatReg and FloatAccJan Beulich1-7/+1
2017-12-18x86: replace Reg8, Reg16, Reg32, and Reg64Jan Beulich1-12/+3
2017-11-30x86: drop Vec_Disp8Jan Beulich1-4/+0
2017-10-23Enable Intel AVX512_BITALG instructions.Igor Tsimbalist1-0/+3
2017-10-23Enable Intel AVX512_VNNI instructions.Igor Tsimbalist1-1/+4
2017-10-23Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist1-1/+4
2017-10-23Enable Intel VAES instructions.Igor Tsimbalist1-0/+3
2017-10-23Enable Intel GFNI instructions.Igor Tsimbalist1-2/+3
2017-10-23Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist1-2/+5
2017-05-22x86: Add NOTRACK prefix supportH.J. Lu1-0/+3
2017-03-09X86: Add pseudo prefixes to control encodingH.J. Lu1-4/+3
2017-03-06Add support for Intel CET instructionsH.J. Lu1-0/+5
2017-01-12Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist1-0/+3
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-11-02Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist1-0/+3
2016-11-02Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist1-0/+9
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