riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2016-09-07	X86: Allow additional ISAs for IAMCU in assembler	H.J. Lu	1	-7/+0
2016-08-24	X86: Add ptwrite instruction	H.J. Lu	1	-129/+136
2016-05-29	Add .noavx512XX directives to x86 assembler	H.J. Lu	1	-0/+63
2016-05-27	Update x86 CPU_XXX_FLAGS handling	H.J. Lu	1	-182/+252
2016-05-27	Replace CpuAMD64/CpuIntel64 with AMD64/Intel64	H.J. Lu	1	-110/+110
2016-05-25	Enable VREX for all AVX512 directives	H.J. Lu	1	-38/+38
2016-05-25	Enable VREX for AVX512 directives	H.J. Lu	1	-4/+4
2016-05-25	Reimplement .no87/.nommx/.nosse/.noavx directives	H.J. Lu	1	-1/+8
2016-05-10	Enable Intel RDPID instruction.	Alexander Fomin	1	-108/+115
2016-01-01	Copyright update for binutils	Alan Modra	1	-1/+1
2015-12-09	Implement Intel OSPKE instructions	H.J. Lu	1	-107/+114
2015-08-07	Remove CpuFMA4 support from CPU_ZNVER1_FLAGS.	Amit Pawar	1	-1/+1
2015-06-30	Add support for monitorx/mwaitx instructions	Amit Pawar	1	-106/+113
2015-05-15	Support AMD64/Intel ISAs in assembler/disassembler	H.J. Lu	1	-106/+106
2015-05-11	Add Intel MCU support to opcodes	H.J. Lu	1	-168/+182
2015-03-17	Add znver1 processor	Ganesh Gopalasubramanian	1	-102/+116
2015-01-02	ChangeLog rotatation and copyright year update	Alan Modra	1	-1/+1
2014-11-17	Add AVX512VBMI instructions	Ilya Tocar	1	-104/+111
2014-11-17	Add AVX512IFMA instructions	Ilya Tocar	1	-103/+110
2014-11-17	Add pcommit instruction	Ilya Tocar	1	-99/+205
2014-11-17	Add clwb instruction	Ilya Tocar	1	-98/+104
2014-07-22	Add AVX512DQ instructions and their AVX512VL variants.	Ilya Tocar	1	-137/+143
2014-07-22	Add support for AVX512BW instructions and their AVX512VL versions.	Ilya Tocar	1	-136/+142
2014-07-22	Add support for AVX512VL. Add AVX512VL versions of AVX512F instructions.	Ilya Tocar	1	-137/+143
2014-04-04	Add support for Intel SGX instructions	Ilya Tocar	1	-94/+100
2014-03-05	Update copyright years	Alan Modra	1	-2/+1
2014-02-21	Add support for CPUID PREFETCHWT1	Ilya Tocar	1	-93/+99
2014-02-19	Don't output trailing space	H.J. Lu	1	-279/+279
2014-02-12	Add clflushopt, xsaves, xsavec, xrstors	Ilya Tocar	1	-91/+109
2013-11-08	Remove CpuNop from CPU_K6_2_FLAGS	H.J. Lu	1	-1/+1
2013-09-30	Add AMD bdver4 support.	Saravanan Ekanathan	1	-0/+6
2013-07-26	Add Intel AVX-512 support	H.J. Lu	1	-229/+268
2013-07-25	Support Intel SHA	H.J. Lu	1	-84/+90
2013-07-24	Support Intel MPX	H.J. Lu	1	-72/+83
2013-05-15	gas/	Saravanan Ekanathan	1	-1/+1
2013-02-19	Implement Intel SMAP instructions	H.J. Lu	1	-82/+88
2013-01-16	Add OPERAND_TYPE_IMM32_64	H.J. Lu	1	-1/+6
2012-10-09	Add AMD bdver3 support.	Nagajyothi Eggone	1	-0/+6
2012-09-25	Add missing Cpu flags in bd and bt cores	H.J. Lu	1	-12/+12
2012-09-20	Replace CpuSSE3 with CpuCX16 for cmpxchg16b	H.J. Lu	1	-108/+114
2012-08-17	Add AMD btver1 and btver2 support	H.J. Lu	1	-0/+12
2012-08-10	Enable FMA instructions for bdver2	H.J. Lu	1	-1/+1
2012-07-16	Implement RDRSEED, ADX and PRFCHW instructions	H.J. Lu	1	-75/+168
2012-02-08	Implement Intel Transactional Synchronization Extensions	H.J. Lu	1	-73/+83
2012-01-13	Add vmfunc	H.J. Lu	1	-72/+77
2011-07-22	Add initial Intel K1OM support.	H.J. Lu	1	-82/+87
2011-06-10	Support AVX Programming Reference (June, 2011).	H.J. Lu	1	-81/+101
2011-06-03	Add CpuF16C to CPU_BDVER2_FLAGS.	Quentin Neill	1	-1/+1
2011-05-11	2011-05-10 Quentin Neill <quentin.neill@amd.com>	Quentin Neill	1	-0/+5
2011-04-20	Regenerate i386-init.h.	H.J. Lu	1	-1/+1