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path: root/opcodes/i386-init.h
AgeCommit message (Expand)AuthorFilesLines
2015-06-30Add support for monitorx/mwaitx instructionsAmit Pawar1-106/+113
2015-05-15Support AMD64/Intel ISAs in assembler/disassemblerH.J. Lu1-106/+106
2015-05-11Add Intel MCU support to opcodesH.J. Lu1-168/+182
2015-03-17Add znver1 processorGanesh Gopalasubramanian1-102/+116
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-11-17Add AVX512VBMI instructionsIlya Tocar1-104/+111
2014-11-17Add AVX512IFMA instructionsIlya Tocar1-103/+110
2014-11-17Add pcommit instructionIlya Tocar1-99/+205
2014-11-17Add clwb instructionIlya Tocar1-98/+104
2014-07-22Add AVX512DQ instructions and their AVX512VL variants.Ilya Tocar1-137/+143
2014-07-22Add support for AVX512BW instructions and their AVX512VL versions.Ilya Tocar1-136/+142
2014-07-22Add support for AVX512VL. Add AVX512VL versions of AVX512F instructions.Ilya Tocar1-137/+143
2014-04-04Add support for Intel SGX instructionsIlya Tocar1-94/+100
2014-03-05Update copyright yearsAlan Modra1-2/+1
2014-02-21Add support for CPUID PREFETCHWT1Ilya Tocar1-93/+99
2014-02-19Don't output trailing spaceH.J. Lu1-279/+279
2014-02-12Add clflushopt, xsaves, xsavec, xrstorsIlya Tocar1-91/+109
2013-11-08Remove CpuNop from CPU_K6_2_FLAGSH.J. Lu1-1/+1
2013-09-30Add AMD bdver4 support.Saravanan Ekanathan1-0/+6
2013-07-26Add Intel AVX-512 supportH.J. Lu1-229/+268
2013-07-25Support Intel SHAH.J. Lu1-84/+90
2013-07-24Support Intel MPXH.J. Lu1-72/+83
2013-05-15gas/Saravanan Ekanathan1-1/+1
2013-02-19Implement Intel SMAP instructionsH.J. Lu1-82/+88
2013-01-16Add OPERAND_TYPE_IMM32_64H.J. Lu1-1/+6
2012-10-09Add AMD bdver3 support.Nagajyothi Eggone1-0/+6
2012-09-25Add missing Cpu flags in bd and bt coresH.J. Lu1-12/+12
2012-09-20Replace CpuSSE3 with CpuCX16 for cmpxchg16bH.J. Lu1-108/+114
2012-08-17Add AMD btver1 and btver2 supportH.J. Lu1-0/+12
2012-08-10Enable FMA instructions for bdver2H.J. Lu1-1/+1
2012-07-16Implement RDRSEED, ADX and PRFCHW instructionsH.J. Lu1-75/+168
2012-02-08Implement Intel Transactional Synchronization ExtensionsH.J. Lu1-73/+83
2012-01-13Add vmfuncH.J. Lu1-72/+77
2011-07-22Add initial Intel K1OM support.H.J. Lu1-82/+87
2011-06-10Support AVX Programming Reference (June, 2011).H.J. Lu1-81/+101
2011-06-03Add CpuF16C to CPU_BDVER2_FLAGS.Quentin Neill1-1/+1
2011-05-112011-05-10 Quentin Neill <quentin.neill@amd.com>Quentin Neill1-0/+5
2011-04-20Regenerate i386-init.h.H.J. Lu1-1/+1
2011-01-18opcodes/Jan Kratochvil1-65/+70
2011-01-05Implement BMI instructions.H.J. Lu1-66/+71
2010-10-16Add CpuNop to CPU_GENERIC64_FLAGS.H.J. Lu1-1/+1
2010-08-06Don't generate multi-byte NOPs for i686.H.J. Lu1-128/+138
2010-07-01Support AVX Programming Reference (June, 2010)H.J. Lu1-71/+91
2010-03-232010-03-22 Sebastian Pop <sebastian.pop@amd.com>Sebastian Pop1-1/+1
2010-02-112010-02-10 Quentin Neill <quentin.neill@amd.com>Sebastian Pop1-46/+51
2010-02-032010-02-03 Quentin Neill <quentin.neill@amd.com>Sebastian Pop1-1/+1
2010-01-062010-01-06 Quentin Neill <quentin.neill@amd.com>Sebastian Pop1-0/+5
2009-11-182009-11-18 Sebastian Pop <sebastian.pop@amd.com>Sebastian Pop1-70/+65
2009-11-182009-11-17 Sebastian Pop <sebastian.pop@amd.com>Sebastian Pop1-66/+76
2009-11-052009-11-05 Sebastian Pop <sebastian.pop@amd.com>Sebastian Pop1-66/+71
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