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path: root/opcodes/i386-gen.c
AgeCommit message (Expand)AuthorFilesLines
2018-04-26Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist1-0/+16
2018-04-26x86: CpuXSAVE is a prereq for various other featuresJan Beulich1-7/+7
2018-04-26x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMaskJan Beulich1-15/+6
2018-04-26x86: x87-related adjustmentsJan Beulich1-3/+3
2018-04-26x86: drop VexImmExtJan Beulich1-1/+0
2018-04-17Enable Intel CLDEMOTE instruction.Igor Tsimbalist1-0/+3
2018-04-11Enable Intel WAITPKG instructions.Igor Tsimbalist1-0/+3
2018-03-28x86: drop VecESizeJan Beulich1-1/+0
2018-03-08x86: Remove support for old (<= 2.8.1) versions of gccH.J. Lu1-1/+0
2018-03-08x86: drop FloatDJan Beulich1-1/+0
2018-03-03opcodes error messagesAlan Modra1-4/+4
2018-02-27x86: Add -O[2|s] assembler command-line optionsH.J. Lu1-0/+1
2018-01-23Enable Intel PCONFIG instruction.Igor Tsimbalist1-0/+3
2018-01-23Enable Intel WBNOINVD instruction.Igor Tsimbalist1-0/+3
2018-01-17Replace CET bit with IBT and SHSTK bits.Igor Tsimbalist1-3/+10
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-2/+2
2018-01-02x86: partial revert of 10c17abdd0Jan Beulich1-0/+4
2017-12-18x86: fold certain AVX and AVX2 templatesJan Beulich1-4/+0
2017-12-18x86: fold RegXMM/RegYMM/RegZMM into RegSIMDJan Beulich1-4/+4
2017-12-18x86: drop FloatReg and FloatAccJan Beulich1-2/+2
2017-12-18x86: replace Reg8, Reg16, Reg32, and Reg64Jan Beulich1-9/+29
2017-11-30x86: derive DispN from BaseIndexJan Beulich1-11/+48
2017-11-30x86: drop Vec_Disp8Jan Beulich1-3/+0
2017-10-23Enable Intel AVX512_BITALG instructions.Igor Tsimbalist1-1/+6
2017-10-23Enable Intel AVX512_VNNI instructions.Igor Tsimbalist1-1/+6
2017-10-23Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist1-0/+3
2017-10-23Enable Intel VAES instructions.Igor Tsimbalist1-0/+3
2017-10-23Enable Intel GFNI instructions.Igor Tsimbalist1-0/+3
2017-10-23Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist1-1/+6
2017-05-22x86: Add NOTRACK prefix supportH.J. Lu1-0/+1
2017-03-09X86: Add pseudo prefixes to control encodingH.J. Lu1-1/+1
2017-03-06Add support for Intel CET instructionsH.J. Lu1-0/+3
2017-01-12Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist1-1/+6
2017-01-02Update year range in copyright notice of all files.Alan Modra1-2/+2
2016-11-02Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist1-1/+6
2016-11-02Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist1-1/+7
2016-10-21X86: Remove pcommit instructionH.J. Lu1-3/+0
2016-09-07X86: Allow additional ISAs for IAMCU in assemblerH.J. Lu1-2/+0
2016-08-24X86: Add ptwrite instructionH.J. Lu1-0/+3
2016-05-29Add .noavx512XX directives to x86 assemblerH.J. Lu1-0/+18
2016-05-27Update x86 CPU_XXX_FLAGS handlingH.J. Lu1-69/+131
2016-05-27Replace CpuAMD64/CpuIntel64 with AMD64/Intel64H.J. Lu1-9/+13
2016-05-27Correct CpuMax in i386-opc.hH.J. Lu1-1/+10
2016-05-25Enable VREX for all AVX512 directivesH.J. Lu1-11/+11
2016-05-25Enable VREX for AVX512 directivesH.J. Lu1-4/+4
2016-05-25Reimplement .no87/.nommx/.nosse/.noavx directivesH.J. Lu1-1/+3
2016-05-10Enable Intel RDPID instruction.Alexander Fomin1-0/+3
2016-01-01Copyright update for binutilsAlan Modra1-2/+2
2015-12-09Implement Intel OSPKE instructionsH.J. Lu1-0/+3
2015-08-07Remove CpuFMA4 support from CPU_ZNVER1_FLAGS.Amit Pawar1-1/+1
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