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2016-09-07X86: Allow additional ISAs for IAMCU in assemblerH.J. Lu1-2/+0
2016-08-24X86: Add ptwrite instructionH.J. Lu1-0/+3
2016-05-29Add .noavx512XX directives to x86 assemblerH.J. Lu1-0/+18
2016-05-27Update x86 CPU_XXX_FLAGS handlingH.J. Lu1-69/+131
2016-05-27Replace CpuAMD64/CpuIntel64 with AMD64/Intel64H.J. Lu1-9/+13
2016-05-27Correct CpuMax in i386-opc.hH.J. Lu1-1/+10
2016-05-25Enable VREX for all AVX512 directivesH.J. Lu1-11/+11
2016-05-25Enable VREX for AVX512 directivesH.J. Lu1-4/+4
2016-05-25Reimplement .no87/.nommx/.nosse/.noavx directivesH.J. Lu1-1/+3
2016-05-10Enable Intel RDPID instruction.Alexander Fomin1-0/+3
2016-01-01Copyright update for binutilsAlan Modra1-2/+2
2015-12-09Implement Intel OSPKE instructionsH.J. Lu1-0/+3
2015-08-07Remove CpuFMA4 support from CPU_ZNVER1_FLAGS.Amit Pawar1-1/+1
2015-06-30Add support for monitorx/mwaitx instructionsAmit Pawar1-2/+5
2015-05-15Support AMD64/Intel ISAs in assembler/disassemblerH.J. Lu1-0/+2
2015-05-11Add Intel MCU support to opcodesH.J. Lu1-0/+5
2015-03-17Add znver1 processorGanesh Gopalasubramanian1-0/+5
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-2/+2
2014-11-17Add AVX512VBMI instructionsIlya Tocar1-0/+3
2014-11-17Add AVX512IFMA instructionsIlya Tocar1-0/+3
2014-11-17Add pcommit instructionIlya Tocar1-0/+3
2014-11-17Add clwb instructionIlya Tocar1-0/+3
2014-07-22Add AVX512DQ instructions and their AVX512VL variants.Ilya Tocar1-0/+3
2014-07-22Add support for AVX512BW instructions and their AVX512VL versions.Ilya Tocar1-0/+3
2014-07-22Add support for AVX512VL. Add AVX512VL versions of AVX512F instructions.Ilya Tocar1-0/+3
2014-04-04Add support for Intel SGX instructionsIlya Tocar1-0/+3
2014-03-05Update copyright yearsAlan Modra1-3/+2
2014-03-03Fix various copyright issuesAlan Modra1-2/+1
2014-02-21Add support for CPUID PREFETCHWT1Ilya Tocar1-0/+3
2014-02-19Don't output trailing spaceH.J. Lu1-4/+13
2014-02-12Add clflushopt, xsaves, xsavec, xrstorsIlya Tocar1-0/+9
2014-01-08Update copyright year to 2014H.J. Lu1-2/+2
2013-11-08Remove CpuNop from CPU_K6_2_FLAGSH.J. Lu1-1/+1
2013-09-30Add AMD bdver4 support.Saravanan Ekanathan1-0/+2
2013-07-26Add Intel AVX-512 supportH.J. Lu1-2/+33
2013-07-25Support Intel SHAH.J. Lu1-0/+3
2013-07-24Support Intel MPXH.J. Lu1-0/+7
2013-05-15gas/Saravanan Ekanathan1-1/+1
2013-02-19Implement Intel SMAP instructionsH.J. Lu1-0/+3
2013-01-16Add OPERAND_TYPE_IMM32_64H.J. Lu1-0/+2
2013-01-02Update copyright year to 2013H.J. Lu1-2/+2
2012-10-09Add AMD bdver3 support.Nagajyothi Eggone1-0/+2
2012-09-25Add missing Cpu flags in bd and bt coresH.J. Lu1-4/+4
2012-09-20Replace CpuSSE3 with CpuCX16 for cmpxchg16bH.J. Lu1-8/+11
2012-08-17Add AMD btver1 and btver2 supportH.J. Lu1-0/+4
2012-08-10Enable FMA instructions for bdver2H.J. Lu1-1/+1
2012-07-16Implement RDRSEED, ADX and PRFCHW instructionsH.J. Lu1-0/+9
2012-06-22gas/Roland McGrath1-8/+9
2012-02-08Implement Intel Transactional Synchronization ExtensionsH.J. Lu1-0/+7
2012-01-13Add vmfuncH.J. Lu1-0/+3
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