| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2014-03-03 | Fix various copyright issues | Alan Modra | 1 | -2/+1 |
| 2014-02-21 | Add support for CPUID PREFETCHWT1 | Ilya Tocar | 1 | -0/+3 |
| 2014-02-19 | Don't output trailing space | H.J. Lu | 1 | -4/+13 |
| 2014-02-12 | Add clflushopt, xsaves, xsavec, xrstors | Ilya Tocar | 1 | -0/+9 |
| 2014-01-08 | Update copyright year to 2014 | H.J. Lu | 1 | -2/+2 |
| 2013-11-08 | Remove CpuNop from CPU_K6_2_FLAGS | H.J. Lu | 1 | -1/+1 |
| 2013-09-30 | Add AMD bdver4 support. | Saravanan Ekanathan | 1 | -0/+2 |
| 2013-07-26 | Add Intel AVX-512 support | H.J. Lu | 1 | -2/+33 |
| 2013-07-25 | Support Intel SHA | H.J. Lu | 1 | -0/+3 |
| 2013-07-24 | Support Intel MPX | H.J. Lu | 1 | -0/+7 |
| 2013-05-15 | gas/ | Saravanan Ekanathan | 1 | -1/+1 |
| 2013-02-19 | Implement Intel SMAP instructions | H.J. Lu | 1 | -0/+3 |
| 2013-01-16 | Add OPERAND_TYPE_IMM32_64 | H.J. Lu | 1 | -0/+2 |
| 2013-01-02 | Update copyright year to 2013 | H.J. Lu | 1 | -2/+2 |
| 2012-10-09 | Add AMD bdver3 support. | Nagajyothi Eggone | 1 | -0/+2 |
| 2012-09-25 | Add missing Cpu flags in bd and bt cores | H.J. Lu | 1 | -4/+4 |
| 2012-09-20 | Replace CpuSSE3 with CpuCX16 for cmpxchg16b | H.J. Lu | 1 | -8/+11 |
| 2012-08-17 | Add AMD btver1 and btver2 support | H.J. Lu | 1 | -0/+4 |
| 2012-08-10 | Enable FMA instructions for bdver2 | H.J. Lu | 1 | -1/+1 |
| 2012-07-16 | Implement RDRSEED, ADX and PRFCHW instructions | H.J. Lu | 1 | -0/+9 |
| 2012-06-22 | gas/ | Roland McGrath | 1 | -8/+9 |
| 2012-02-08 | Implement Intel Transactional Synchronization Extensions | H.J. Lu | 1 | -0/+7 |
| 2012-01-13 | Add vmfunc | H.J. Lu | 1 | -0/+3 |
| 2011-07-22 | Add initial Intel K1OM support. | H.J. Lu | 1 | -1/+4 |
| 2011-06-10 | Support AVX Programming Reference (June, 2011). | H.J. Lu | 1 | -2/+15 |
| 2011-06-03 | Add CpuF16C to CPU_BDVER2_FLAGS. | Quentin Neill | 1 | -1/+1 |
| 2011-05-11 | 2011-05-10 Quentin Neill <quentin.neill@amd.com> | Quentin Neill | 1 | -0/+2 |
| 2011-04-19 | * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits | Quentin Neill | 1 | -1/+1 |
| 2011-01-17 | Add support for TBM instructions. | Quentin Neill | 1 | -0/+3 |
| 2011-01-05 | Implement BMI instructions. | H.J. Lu | 1 | -0/+3 |
| 2011-01-01 | Update copyright in comments to 2011. | H.J. Lu | 1 | -2/+2 |
| 2011-01-01 | Update copyright to 2011. | H.J. Lu | 1 | -1/+1 |
| 2010-10-16 | Add CpuNop to CPU_GENERIC64_FLAGS. | H.J. Lu | 1 | -1/+1 |
| 2010-10-14 | Add CheckRegSize to instructions which require register size check. | H.J. Lu | 1 | -0/+1 |
| 2010-08-06 | Don't generate multi-byte NOPs for i686. | H.J. Lu | 1 | -12/+17 |
| 2010-07-01 | Support AVX Programming Reference (June, 2010) | H.J. Lu | 1 | -0/+12 |
| 2010-02-11 | Update copyright. | H.J. Lu | 1 | -2/+2 |
| 2010-02-11 | 2010-02-10 Quentin Neill <quentin.neill@amd.com> | Sebastian Pop | 1 | -0/+3 |
| 2010-02-03 | 2010-02-03 Quentin Neill <quentin.neill@amd.com> | Sebastian Pop | 1 | -1/+1 |
| 2010-01-06 | 2010-01-06 Quentin Neill <quentin.neill@amd.com> | Sebastian Pop | 1 | -0/+2 |
| 2009-12-19 | Replace VexNDS, VexNDD and VexLWP with VexVVVV. | H.J. Lu | 1 | -3/+1 |
| 2009-12-18 | Move Imm1 before Imm8. | H.J. Lu | 1 | -1/+1 |
| 2009-12-16 | Remove ByteOkIntel. | H.J. Lu | 1 | -1/+0 |
| 2009-12-16 | Replace Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A with VexOpcode. | H.J. Lu | 1 | -6/+1 |
| 2009-12-16 | Replace Vex2Sources and Vex3Sources with VexSources. | H.J. Lu | 1 | -2/+1 |
| 2009-12-16 | Remove VexW0 and VexW1. Add VexW. | H.J. Lu | 1 | -2/+1 |
| 2009-11-18 | 2009-11-18 Sebastian Pop <sebastian.pop@amd.com> | Sebastian Pop | 1 | -4/+1 |
| 2009-11-18 | 2009-11-17 Sebastian Pop <sebastian.pop@amd.com> | Sebastian Pop | 1 | -0/+8 |
| 2009-11-12 | gas/ | H.J. Lu | 1 | -0/+1 |
| 2009-11-05 | 2009-11-05 Sebastian Pop <sebastian.pop@amd.com> | Sebastian Pop | 1 | -1/+7 |
