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path: root/opcodes/i386-gen.c
AgeCommit message (Expand)AuthorFilesLines
2013-05-15gas/Saravanan Ekanathan1-1/+1
2013-02-19Implement Intel SMAP instructionsH.J. Lu1-0/+3
2013-01-16Add OPERAND_TYPE_IMM32_64H.J. Lu1-0/+2
2013-01-02Update copyright year to 2013H.J. Lu1-2/+2
2012-10-09Add AMD bdver3 support.Nagajyothi Eggone1-0/+2
2012-09-25Add missing Cpu flags in bd and bt coresH.J. Lu1-4/+4
2012-09-20Replace CpuSSE3 with CpuCX16 for cmpxchg16bH.J. Lu1-8/+11
2012-08-17Add AMD btver1 and btver2 supportH.J. Lu1-0/+4
2012-08-10Enable FMA instructions for bdver2H.J. Lu1-1/+1
2012-07-16Implement RDRSEED, ADX and PRFCHW instructionsH.J. Lu1-0/+9
2012-06-22gas/Roland McGrath1-8/+9
2012-02-08Implement Intel Transactional Synchronization ExtensionsH.J. Lu1-0/+7
2012-01-13Add vmfuncH.J. Lu1-0/+3
2011-07-22Add initial Intel K1OM support.H.J. Lu1-1/+4
2011-06-10Support AVX Programming Reference (June, 2011).H.J. Lu1-2/+15
2011-06-03Add CpuF16C to CPU_BDVER2_FLAGS.Quentin Neill1-1/+1
2011-05-112011-05-10 Quentin Neill <quentin.neill@amd.com>Quentin Neill1-0/+2
2011-04-19 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bitsQuentin Neill1-1/+1
2011-01-17Add support for TBM instructions.Quentin Neill1-0/+3
2011-01-05Implement BMI instructions.H.J. Lu1-0/+3
2011-01-01Update copyright in comments to 2011.H.J. Lu1-2/+2
2011-01-01Update copyright to 2011.H.J. Lu1-1/+1
2010-10-16Add CpuNop to CPU_GENERIC64_FLAGS.H.J. Lu1-1/+1
2010-10-14Add CheckRegSize to instructions which require register size check.H.J. Lu1-0/+1
2010-08-06Don't generate multi-byte NOPs for i686.H.J. Lu1-12/+17
2010-07-01Support AVX Programming Reference (June, 2010)H.J. Lu1-0/+12
2010-02-11Update copyright.H.J. Lu1-2/+2
2010-02-112010-02-10 Quentin Neill <quentin.neill@amd.com>Sebastian Pop1-0/+3
2010-02-032010-02-03 Quentin Neill <quentin.neill@amd.com>Sebastian Pop1-1/+1
2010-01-062010-01-06 Quentin Neill <quentin.neill@amd.com>Sebastian Pop1-0/+2
2009-12-19Replace VexNDS, VexNDD and VexLWP with VexVVVV.H.J. Lu1-3/+1
2009-12-18Move Imm1 before Imm8.H.J. Lu1-1/+1
2009-12-16Remove ByteOkIntel.H.J. Lu1-1/+0
2009-12-16Replace Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A with VexOpcode.H.J. Lu1-6/+1
2009-12-16Replace Vex2Sources and Vex3Sources with VexSources.H.J. Lu1-2/+1
2009-12-16Remove VexW0 and VexW1. Add VexW.H.J. Lu1-2/+1
2009-11-182009-11-18 Sebastian Pop <sebastian.pop@amd.com>Sebastian Pop1-4/+1
2009-11-182009-11-17 Sebastian Pop <sebastian.pop@amd.com>Sebastian Pop1-0/+8
2009-11-12gas/H.J. Lu1-0/+1
2009-11-052009-11-05 Sebastian Pop <sebastian.pop@amd.com>Sebastian Pop1-1/+7
2009-09-24gas/H.J. Lu1-1/+23
2009-08-29 Updated sources to avoid using the identifier name "new", which is aNick Clifton1-1/+1
2009-07-25bfd/H.J. Lu1-11/+45
2009-07-24gas/Jan Beulich1-16/+39
2009-07-06<gas changes>Dwarakanath Rajagopal1-0/+3
2009-05-22<gas changes>Dwarakanath Rajagopal1-6/+0
2009-02-23gas/H.J. Lu1-3/+0
2009-01-142009-01-13 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu1-2/+2
2009-01-10gas/H.J. Lu1-34/+48
2009-01-09gas/H.J. Lu1-5/+6
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