aboutsummaryrefslogtreecommitdiff
path: root/opcodes/i386-gen.c
AgeCommit message (Expand)AuthorFilesLines
2021-03-03x86: infer operand count of templatesJan Beulich1-34/+21
2021-02-16x86: have preprocessor expand macrosJan Beulich1-11/+0
2021-01-26Segmentation fault i386-genAlan Modra1-0/+2
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-2/+2
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian1-0/+11
2020-10-16Enhancement for avx-vnni patchCui,Lili1-2/+2
2020-10-14x86: Support Intel AVX VNNIH.J. Lu1-0/+6
2020-10-14x86: Add support for Intel HRESET instructionLili Cui1-0/+7
2020-10-14x86: Support Intel UINTRLili Cui1-0/+5
2020-10-14x86: Remove the prefix byte from non-VEX/EVEX base_opcodeH.J. Lu1-3/+52
2020-10-13x86: Rename VexOpcode to OpcodePrefixH.J. Lu1-1/+1
2020-09-24Add support for Intel TDX instructions.Cui,Lili1-0/+5
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo1-0/+10
2020-07-10x86: Add support for Intel AMX instructionsLili Cui1-0/+18
2020-07-02x86: Add SwapSourcesH.J. Lu1-0/+1
2020-06-26x86: Rename VecSIB to SIB for Intel AMXH.J. Lu1-1/+1
2020-04-07Add support for intel TSXLDTRK instructions$Cui,Lili1-0/+5
2020-04-02Add support for intel SERIALIZE instructionLiliCui1-0/+5
2020-03-09x86: use template for SSE floating point comparison insnsJan Beulich1-0/+4
2020-03-09x86: allow opcode templates to be templatedJan Beulich1-46/+267
2020-03-06x86: drop Rex64 attributeJan Beulich1-1/+0
2020-03-04x86: support VMGEXITJan Beulich1-0/+3
2020-03-03x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu1-2/+1
2020-02-17x86: Remove CpuABM and add CpuPOPCNTH.J. Lu1-7/+9
2020-02-16x86: Don't disable SSE3 when disabling SSE4aH.J. Lu1-1/+1
2020-02-17Re: x86: Don't disable SSE4a when disabling SSE4Alan Modra1-2/+2
2020-02-16x86: Don't disable SSE4a when disabling SSE4H.J. Lu1-2/+2
2020-02-13x86: fix SSE4a dependencies of ".arch .nosse*"Jan Beulich1-2/+4
2020-02-11x86: drop ShortForm attributeJan Beulich1-1/+0
2020-02-10x86: Accept Intel64 only instruction by defaultH.J. Lu1-2/+1
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-2/+2
2019-12-27x86: consolidate Disp<NN> handling a littleJan Beulich1-1/+2
2019-11-14x86: fold individual Jump* attributes into a single Jump oneJan Beulich1-4/+0
2019-11-14x86: make JumpAbsolute an insn attributeJan Beulich1-3/+1
2019-11-14x86: make AnySize an insn attributeJan Beulich1-1/+1
2019-11-12x86: fold EsSeg into IsStringJan Beulich1-4/+1
2019-11-12x86: eliminate ImmExt abuseJan Beulich1-0/+1
2019-11-12x86: introduce operand type "instance"Jan Beulich1-17/+42
2019-11-08x86: convert RegMask and RegBND from bitfield to enumeratorJan Beulich1-5/+5
2019-11-08x86: convert RegSIMD and RegMMX from bitfield to enumeratorJan Beulich1-6/+6
2019-11-08x86: convert Control/Debug/Test from bitfield to enumeratorJan Beulich1-6/+6
2019-11-08x86: convert SReg from bitfield to enumeratorJan Beulich1-2/+2
2019-11-08x86: introduce operand type "class"Jan Beulich1-13/+42
2019-11-07x86: support further AMD Zen2 instructionsJan Beulich1-1/+7
2019-10-30x86: re-do "shorthand" handlingJan Beulich1-42/+13
2019-10-30x86: slightly rearrange struct insn_templateJan Beulich1-2/+1
2019-10-30x86: drop stray WJan Beulich1-0/+24
2019-07-17x86: drop stale Mem enumeratorJan Beulich1-1/+15
2019-07-16x86: make RegMem an opcode modifierJan Beulich1-1/+1
2019-07-16x86: fold SReg{2,3}Jan Beulich1-6/+3
generated by cgit v1.1 at 2025-03-07 21:46:15 +0000