| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2019-06-17 | i386: Check vector length for vshufXXX/vinsertXXX/vextractXXX | H.J. Lu | 1 | -1/+13 | |
| Since not all vector lengths are supported by vshufXXX, vinsertXXX and vextractXXX, decode them only with supported vector lengths. gas/ PR binutils/24691 * testsuite/gas/i386/disassem.s: Add test for vshuff32x4 with invalid vector length. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24691 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2. (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and EVEX_LEN_0F3A43_P_2_W_1. * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum. (EVEX_LEN_0F3A23_P_2_W_1): Likewise. (EVEX_LEN_0F3A38_P_2_W_0): Likewise. (EVEX_LEN_0F3A38_P_2_W_1): Likewise. (EVEX_LEN_0F3A39_P_2_W_0): Likewise. (EVEX_LEN_0F3A39_P_2_W_1): Likewise. (EVEX_LEN_0F3A3A_P_2_W_0): Likewise. (EVEX_LEN_0F3A3A_P_2_W_1): Likewise. (EVEX_LEN_0F3A3B_P_2_W_0): Likewise. (EVEX_LEN_0F3A3B_P_2_W_1): Likewise. (EVEX_LEN_0F3A43_P_2_W_0): Likewise. (EVEX_LEN_0F3A43_P_2_W_1): Likewise. | |||||
| 2019-06-05 | i386: Check vector length for EVEX vextractfXX and vinsertfXX | H.J. Lu | 1 | -1/+9 | |
| Since not all vector lengths are supported by EVEX vextractfXX and vinsertfXX, decode them only with supported vector lengths. gas/ PR binutils/24633 * testsuite/gas/i386/disassem.s: Add tests for invalid vector lengths for EVEX vextractfXX and vinsertfXX. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24633 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2. (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0, EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0, EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0, EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0, EVEX_LEN_0F3A1B_P_2_W_1. * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum. (EVEX_LEN_0F3A18_P_2_W_1): Likewise. (EVEX_LEN_0F3A19_P_2_W_0): Likewise. (EVEX_LEN_0F3A19_P_2_W_1): Likewise. (EVEX_LEN_0F3A1A_P_2_W_0): Likewise. (EVEX_LEN_0F3A1A_P_2_W_1): Likewise. (EVEX_LEN_0F3A1B_P_2_W_0): Likewise. (EVEX_LEN_0F3A1B_P_2_W_1): Likewise. | |||||
| 2019-06-04 | i386: Check for reserved VEX.vvvv and EVEX.vvvv | H.J. Lu | 1 | -10/+14 | |
| If VEX.vvvv and EVEX.vvvv are reserved, they must be all 1s, which are all 0s in inverted form. Add check for unused VEX.vvvv and EVEX.vvvv when disassembling VEX and EVEX instructions. gas/ PR binutils/24626 * testsuite/gas/i386/disassem.s: Add tests for reserved VEX.vvvv and EVEX.vvvv. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24626 * i386-dis.c (print_insn): Check for unused VEX.vvvv and EVEX.vvvv when disassembling VEX and EVEX instructions. (OP_VEX): Set vex.register_specifier to 0 after readding vex.register_specifier. (OP_Vex_2src_1): Likewise. (OP_Vex_2src_2): Likewise. (OP_LWP_E): Likewise. (OP_EX_Vex): Don't check vex.register_specifier. (OP_XMM_Vex): Likewise. | |||||
| 2019-06-04 | Enable Intel AVX512_VP2INTERSECT insn | H.J. Lu | 1 | -0/+2 | |
| This patch enables support for VP2INTERSECT in binutils. Please refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf for VP2INTERSECT details. Make check-gas is ok. gas/ 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_vp2intersect. (cpu_noarch): Likewise. * doc/c-i386.texi: Document avx512_vp2intersect. * testsuite/gas/i386/i386.exp: Run vp2intersect tests. * testsuite/gas/i386/vp2intersect-intel.d: New test. * testsuite/gas/i386/vp2intersect.d: Likewise. * testsuite/gas/i386/vp2intersect.s: Likewise. * testsuite/gas/i386/vp2intersect-inval-bcast.l: Likewise. * testsuite/gas/i386/vp2intersect-inval-bcast.s: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-intel.d: Likewise. * testsuite/gas/i386/x86-64-vp2intersect.d: Likewise. * testsuite/gas/i386/x86-64-vp2intersect.s: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.l: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.s: Likewise. opcodes/ 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3. * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT instructions. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS, CPU_ANY_AVX512_VP2INTERSECT_FLAGS. (cpu_flags): Add CpuAVX512_VP2INTERSECT. * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT. (i386_cpu_flags): Add cpuavx512_vp2intersect. * i386-opc.tbl: Add AVX512_VP2INTERSECT insns. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. | |||||
| 2019-06-04 | Add support for Intel ENQCMD[S] instructions | H.J. Lu | 1 | -1/+12 | |
| This patch enables support for ENQCMD[S] in binutils. Please refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf for ENQCMD[S] details. Make check-gas is ok. gas/ChangeLog: 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com> Lili Cui <lili.cui@intel.com> * doc/c-i386.texi: Document enqcmd. * testsuite/gas/i386/enqcmd-intel.d: New file. * testsuite/gas/i386/enqcmd-inval.l: Likewise. * testsuite/gas/i386/enqcmd-inval.s: Likewise. * testsuite/gas/i386/enqcmd.d: Likewise. * testsuite/gas/i386/enqcmd.s: Likewise. * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise. * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise. * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd.s: Likewise. * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval, enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval, and x86-64-enqcmd. opcodes/ChangeLog: 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (enum): Add MOD_0F38F8_PREFIX_1 and MOD_0F38F8_PREFIX_3. (prefix_table): New instructions (see prefix above). (mod_table): New instructions (see prefix above). * i386-gen.c (cpu_flag_init): Add entries for enqcmd. (cpu_flags): Add a bitfield for enqmcd. * i386-init.h: Regenerated. * i386-opc.h (enum): Add CpuENQCMD. (i386_cpu_flags): Add a bitfield for cpuenqcmd. * i386-opc.tbl: Add enqcmd and enqcmds instructions. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated. | |||||
| 2019-04-05 | x86: Support Intel AVX512 BF16 | Xuepeng Guo | 1 | -0/+3 | |
| Add assembler and disassembler support Intel AVX512 BF16: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference gas/ 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_bf16. (cpu_noarch): Add noavx512_bf16. * doc/c-i386.texi: Document avx512_bf16. * testsuite/gas/i386/avx512_bf16.d: New file. * testsuite/gas/i386/avx512_bf16.s: Likewise. * testsuite/gas/i386/avx512_bf16_vl-inval.l: Likewise. * testsuite/gas/i386/avx512_bf16_vl-inval.s: Likewise. * testsuite/gas/i386/avx512_bf16_vl.d: Likewise. * testsuite/gas/i386/avx512_bf16_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16.d: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l: Likesie. * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Likewise. * testsuite/gas/i386/i386.exp: Add BF16 related tests. opcodes/ 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> * i386-dis-evex.h (evex_table): Updated to support BF16 instructions. * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1 and EVEX_W_0F3872_P_3. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS. (cpu_flags): Add bitfield for CpuAVX512_BF16. * i386-opc.h (enum): Add CpuAVX512_BF16. (i386_cpu_flags): Add bitfield for cpuavx512_bf16. * i386-opc.tbl: Add AVX512 BF16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. | |||||
| 2019-01-01 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 | |
| 2018-11-06 | x86: correctly handle VMOVD with EVEX.W set outside of 64-bit mode | Jan Beulich | 1 | -2/+0 | |
| For the flavors having a GPR operand EVEX.W is ignored outside of 64-bit mode. The mnemonic should therefore not be KMOVQ, the GPR operand should not name a non-existing 64-bit register, just like is already the case for the AVX counterparts, and the Disp8 scaling factor should be 4 rather than 8. | |||||
| 2018-11-06 | x86: correctly handle KMOVD with VEX.W set outside of 64-bit mode | Jan Beulich | 1 | -32/+8 | |
| For the flavors having a GPR operand VEX.W is ignored outside of 64-bit mode. The mnemonic should therefore not be KMOVQ. | |||||
| 2018-11-06 | x86: adjust {,E}VEX.W handling for PEXTR* / PINSR* | Jan Beulich | 1 | -32/+12 | |
| PEXTR{B,W} and PINSR{B,W}, just like for AVX512BW, are WIG, no matter that the SDM uses a nonstandard description of that fact. PEXTRD, even with EVEX.W set, ignores that bit outside of 64-bit mode, just like its AVX counterpart. | |||||
| 2018-10-05 | x86: Add Intel ENCLV to assembler and disassembler | H.J. Lu | 1 | -1/+1 | |
| gas/ * testsuite/gas/i386/se1.s: Add enclv. * testsuite/gas/i386/x86-64-se1.s: Likewise. * testsuite/gas/i386/se1.d: Updated. * testsuite/gas/i386/x86-64-se1.d: Likewise. opcodes/ * i386-dis.c (rm_table): Add enclv. * i386-opc.tbl: Add enclv. * i386-tbl.h: Regenerated. | |||||
| 2018-09-17 | x86: Set EVex=2 on EVEX.128 only vmovd and vmovq | H.J. Lu | 1 | -1/+40 | |
| EVEX "VMOVD xmm1, r32/m32", "VMOVD r32/m32, xmm2", "VMOVQ xmm1, r64/m64", "VMOVD r64/m64, xmm2", "VMOVQ xmm1, xmm2/m64" and "VMOVQ xmm1/m64, xmm2" can only be encoded with EVEX.128. Set EVex=2 on EVEX.128 only vmovd and vmovq. gas/ PR gas/23670 * testsuite/gas/i386/evex-lig-2.d: New file. * testsuite/gas/i386/evex-lig-2.s: Likewise. * testsuite/gas/i386/x86-64-evex-lig-2.d: Likewise. * testsuite/gas/i386/x86-64-evex-lig-2.s: Likewise. * testsuite/gas/i386/i386.exp: Run evex-lig-2 and x86-64-evex-lig-2. opcodes/ PR gas/23670 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2, EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2. (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry. (EVEX_LEN_0F7E_P_1): Likewise. (EVEX_LEN_0F7E_P_2): Likewise. (EVEX_LEN_0FD6_P_2): Likewise. * i386-dis.c (USE_EVEX_LEN_TABLE): New. (EVEX_LEN_TABLE): Likewise. (EVEX_LEN_0F6E_P_2): New enum. (EVEX_LEN_0F7E_P_1): Likewise. (EVEX_LEN_0F7E_P_2): Likewise. (EVEX_LEN_0FD6_P_2): Likewise. (evex_len_table): New. (get_valid_dis386): Handle USE_EVEX_LEN_TABLE. * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq. * i386-tbl.h: Regenerated. | |||||
| 2018-09-17 | x86: Set Vex=1 on VEX.128 only vmovd and vmovq | H.J. Lu | 1 | -2/+0 | |
| AVX "VMOVD xmm1, r32/m32", "VMOVD r32/m32, xmm2", "VMOVQ xmm1, r64/m64" and "VMOVD r64/m64, xmm2" can only be encoded with VEX.128. Set Vex=1 on VEX.128 only vmovd and vmovq. gas/ PR gas/23665 * testsuite/gas/i386/avx-scalar.s: Remove vmovq and vmovd tests. * testsuite/gas/i386/x86-64-avx-scalar.s: Likewise. * testsuite/gas/i386/avx-scalar-intel.d: Updated. * testsuite/gas/i386/avx-scalar.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar.d: Likewise. * testsuite/gas/i386/i386.exp: Run avx-scalar2 and x86-64-avx-scalar2. * testsuite/gas/i386/avx-scalar-2.d: New file. * testsuite/gas/i386/avx-scalar-2.s: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-2.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-2.s: Likewise. opcodes/ PR gas/23665 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and VEX_LEN_0F7E_P_2 entries. * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq. * i386-tbl.h: Regenerated. | |||||
| 2018-09-17 | x86: Update disassembler for VexWIG | H.J. Lu | 1 | -1563/+232 | |
| The VEX.W bit is ignored by some VEX instructions, aka WIG instructions. Update x86 disassembler to handle VEX WIG instructions. * i386-dis.c (VZERO_Fixup): Removed. (VZERO): Likewise. (VEX_LEN_0F10_P_1): Likewise. (VEX_LEN_0F10_P_3): Likewise. (VEX_LEN_0F11_P_1): Likewise. (VEX_LEN_0F11_P_3): Likewise. (VEX_LEN_0F2E_P_0): Likewise. (VEX_LEN_0F2E_P_2): Likewise. (VEX_LEN_0F2F_P_0): Likewise. (VEX_LEN_0F2F_P_2): Likewise. (VEX_LEN_0F51_P_1): Likewise. (VEX_LEN_0F51_P_3): Likewise. (VEX_LEN_0F52_P_1): Likewise. (VEX_LEN_0F53_P_1): Likewise. (VEX_LEN_0F58_P_1): Likewise. (VEX_LEN_0F58_P_3): Likewise. (VEX_LEN_0F59_P_1): Likewise. (VEX_LEN_0F59_P_3): Likewise. (VEX_LEN_0F5A_P_1): Likewise. (VEX_LEN_0F5A_P_3): Likewise. (VEX_LEN_0F5C_P_1): Likewise. (VEX_LEN_0F5C_P_3): Likewise. (VEX_LEN_0F5D_P_1): Likewise. (VEX_LEN_0F5D_P_3): Likewise. (VEX_LEN_0F5E_P_1): Likewise. (VEX_LEN_0F5E_P_3): Likewise. (VEX_LEN_0F5F_P_1): Likewise. (VEX_LEN_0F5F_P_3): Likewise. (VEX_LEN_0FC2_P_1): Likewise. (VEX_LEN_0FC2_P_3): Likewise. (VEX_LEN_0F3A0A_P_2): Likewise. (VEX_LEN_0F3A0B_P_2): Likewise. (VEX_W_0F10_P_0): Likewise. (VEX_W_0F10_P_1): Likewise. (VEX_W_0F10_P_2): Likewise. (VEX_W_0F10_P_3): Likewise. (VEX_W_0F11_P_0): Likewise. (VEX_W_0F11_P_1): Likewise. (VEX_W_0F11_P_2): Likewise. (VEX_W_0F11_P_3): Likewise. (VEX_W_0F12_P_0_M_0): Likewise. (VEX_W_0F12_P_0_M_1): Likewise. (VEX_W_0F12_P_1): Likewise. (VEX_W_0F12_P_2): Likewise. (VEX_W_0F12_P_3): Likewise. (VEX_W_0F13_M_0): Likewise. (VEX_W_0F14): Likewise. (VEX_W_0F15): Likewise. (VEX_W_0F16_P_0_M_0): Likewise. (VEX_W_0F16_P_0_M_1): Likewise. (VEX_W_0F16_P_1): Likewise. (VEX_W_0F16_P_2): Likewise. (VEX_W_0F17_M_0): Likewise. (VEX_W_0F28): Likewise. (VEX_W_0F29): Likewise. (VEX_W_0F2B_M_0): Likewise. (VEX_W_0F2E_P_0): Likewise. (VEX_W_0F2E_P_2): Likewise. (VEX_W_0F2F_P_0): Likewise. (VEX_W_0F2F_P_2): Likewise. (VEX_W_0F50_M_0): Likewise. (VEX_W_0F51_P_0): Likewise. (VEX_W_0F51_P_1): Likewise. (VEX_W_0F51_P_2): Likewise. (VEX_W_0F51_P_3): Likewise. (VEX_W_0F52_P_0): Likewise. (VEX_W_0F52_P_1): Likewise. (VEX_W_0F53_P_0): Likewise. (VEX_W_0F53_P_1): Likewise. (VEX_W_0F58_P_0): Likewise. (VEX_W_0F58_P_1): Likewise. (VEX_W_0F58_P_2): Likewise. (VEX_W_0F58_P_3): Likewise. (VEX_W_0F59_P_0): Likewise. (VEX_W_0F59_P_1): Likewise. (VEX_W_0F59_P_2): Likewise. (VEX_W_0F59_P_3): Likewise. (VEX_W_0F5A_P_0): Likewise. (VEX_W_0F5A_P_1): Likewise. (VEX_W_0F5A_P_3): Likewise. (VEX_W_0F5B_P_0): Likewise. (VEX_W_0F5B_P_1): Likewise. (VEX_W_0F5B_P_2): Likewise. (VEX_W_0F5C_P_0): Likewise. (VEX_W_0F5C_P_1): Likewise. (VEX_W_0F5C_P_2): Likewise. (VEX_W_0F5C_P_3): Likewise. (VEX_W_0F5D_P_0): Likewise. (VEX_W_0F5D_P_1): Likewise. (VEX_W_0F5D_P_2): Likewise. (VEX_W_0F5D_P_3): Likewise. (VEX_W_0F5E_P_0): Likewise. (VEX_W_0F5E_P_1): Likewise. (VEX_W_0F5E_P_2): Likewise. (VEX_W_0F5E_P_3): Likewise. (VEX_W_0F5F_P_0): Likewise. (VEX_W_0F5F_P_1): Likewise. (VEX_W_0F5F_P_2): Likewise. (VEX_W_0F5F_P_3): Likewise. (VEX_W_0F60_P_2): Likewise. (VEX_W_0F61_P_2): Likewise. (VEX_W_0F62_P_2): Likewise. (VEX_W_0F63_P_2): Likewise. (VEX_W_0F64_P_2): Likewise. (VEX_W_0F65_P_2): Likewise. (VEX_W_0F66_P_2): Likewise. (VEX_W_0F67_P_2): Likewise. (VEX_W_0F68_P_2): Likewise. (VEX_W_0F69_P_2): Likewise. (VEX_W_0F6A_P_2): Likewise. (VEX_W_0F6B_P_2): Likewise. (VEX_W_0F6C_P_2): Likewise. (VEX_W_0F6D_P_2): Likewise. (VEX_W_0F6F_P_1): Likewise. (VEX_W_0F6F_P_2): Likewise. (VEX_W_0F70_P_1): Likewise. (VEX_W_0F70_P_2): Likewise. (VEX_W_0F70_P_3): Likewise. (VEX_W_0F71_R_2_P_2): Likewise. (VEX_W_0F71_R_4_P_2): Likewise. (VEX_W_0F71_R_6_P_2): Likewise. (VEX_W_0F72_R_2_P_2): Likewise. (VEX_W_0F72_R_4_P_2): Likewise. (VEX_W_0F72_R_6_P_2): Likewise. (VEX_W_0F73_R_2_P_2): Likewise. (VEX_W_0F73_R_3_P_2): Likewise. (VEX_W_0F73_R_6_P_2): Likewise. (VEX_W_0F73_R_7_P_2): Likewise. (VEX_W_0F74_P_2): Likewise. (VEX_W_0F75_P_2): Likewise. (VEX_W_0F76_P_2): Likewise. (VEX_W_0F77_P_0): Likewise. (VEX_W_0F7C_P_2): Likewise. (VEX_W_0F7C_P_3): Likewise. (VEX_W_0F7D_P_2): Likewise. (VEX_W_0F7D_P_3): Likewise. (VEX_W_0F7E_P_1): Likewise. (VEX_W_0F7F_P_1): Likewise. (VEX_W_0F7F_P_2): Likewise. (VEX_W_0FAE_R_2_M_0): Likewise. (VEX_W_0FAE_R_3_M_0): Likewise. (VEX_W_0FC2_P_0): Likewise. (VEX_W_0FC2_P_1): Likewise. (VEX_W_0FC2_P_2): Likewise. (VEX_W_0FC2_P_3): Likewise. (VEX_W_0FD0_P_2): Likewise. (VEX_W_0FD0_P_3): Likewise. (VEX_W_0FD1_P_2): Likewise. (VEX_W_0FD2_P_2): Likewise. (VEX_W_0FD3_P_2): Likewise. (VEX_W_0FD4_P_2): Likewise. (VEX_W_0FD5_P_2): Likewise. (VEX_W_0FD6_P_2): Likewise. (VEX_W_0FD7_P_2_M_1): Likewise. (VEX_W_0FD8_P_2): Likewise. (VEX_W_0FD9_P_2): Likewise. (VEX_W_0FDA_P_2): Likewise. (VEX_W_0FDB_P_2): Likewise. (VEX_W_0FDC_P_2): Likewise. (VEX_W_0FDD_P_2): Likewise. (VEX_W_0FDE_P_2): Likewise. (VEX_W_0FDF_P_2): Likewise. (VEX_W_0FE0_P_2): Likewise. (VEX_W_0FE1_P_2): Likewise. (VEX_W_0FE2_P_2): Likewise. (VEX_W_0FE3_P_2): Likewise. (VEX_W_0FE4_P_2): Likewise. (VEX_W_0FE5_P_2): Likewise. (VEX_W_0FE6_P_1): Likewise. (VEX_W_0FE6_P_2): Likewise. (VEX_W_0FE6_P_3): Likewise. (VEX_W_0FE7_P_2_M_0): Likewise. (VEX_W_0FE8_P_2): Likewise. (VEX_W_0FE9_P_2): Likewise. (VEX_W_0FEA_P_2): Likewise. (VEX_W_0FEB_P_2): Likewise. (VEX_W_0FEC_P_2): Likewise. (VEX_W_0FED_P_2): Likewise. (VEX_W_0FEE_P_2): Likewise. (VEX_W_0FEF_P_2): Likewise. (VEX_W_0FF0_P_3_M_0): Likewise. (VEX_W_0FF1_P_2): Likewise. (VEX_W_0FF2_P_2): Likewise. (VEX_W_0FF3_P_2): Likewise. (VEX_W_0FF4_P_2): Likewise. (VEX_W_0FF5_P_2): Likewise. (VEX_W_0FF6_P_2): Likewise. (VEX_W_0FF7_P_2): Likewise. (VEX_W_0FF8_P_2): Likewise. (VEX_W_0FF9_P_2): Likewise. (VEX_W_0FFA_P_2): Likewise. (VEX_W_0FFB_P_2): Likewise. (VEX_W_0FFC_P_2): Likewise. (VEX_W_0FFD_P_2): Likewise. (VEX_W_0FFE_P_2): Likewise. (VEX_W_0F3800_P_2): Likewise. (VEX_W_0F3801_P_2): Likewise. (VEX_W_0F3802_P_2): Likewise. (VEX_W_0F3803_P_2): Likewise. (VEX_W_0F3804_P_2): Likewise. (VEX_W_0F3805_P_2): Likewise. (VEX_W_0F3806_P_2): Likewise. (VEX_W_0F3807_P_2): Likewise. (VEX_W_0F3808_P_2): Likewise. (VEX_W_0F3809_P_2): Likewise. (VEX_W_0F380A_P_2): Likewise. (VEX_W_0F380B_P_2): Likewise. (VEX_W_0F3817_P_2): Likewise. (VEX_W_0F381C_P_2): Likewise. (VEX_W_0F381D_P_2): Likewise. (VEX_W_0F381E_P_2): Likewise. (VEX_W_0F3820_P_2): Likewise. (VEX_W_0F3821_P_2): Likewise. (VEX_W_0F3822_P_2): Likewise. (VEX_W_0F3823_P_2): Likewise. (VEX_W_0F3824_P_2): Likewise. (VEX_W_0F3825_P_2): Likewise. (VEX_W_0F3828_P_2): Likewise. (VEX_W_0F3829_P_2): Likewise. (VEX_W_0F382A_P_2_M_0): Likewise. (VEX_W_0F382B_P_2): Likewise. (VEX_W_0F3830_P_2): Likewise. (VEX_W_0F3831_P_2): Likewise. (VEX_W_0F3832_P_2): Likewise. (VEX_W_0F3833_P_2): Likewise. (VEX_W_0F3834_P_2): Likewise. (VEX_W_0F3835_P_2): Likewise. (VEX_W_0F3837_P_2): Likewise. (VEX_W_0F3838_P_2): Likewise. (VEX_W_0F3839_P_2): Likewise. (VEX_W_0F383A_P_2): Likewise. (VEX_W_0F383B_P_2): Likewise. (VEX_W_0F383C_P_2): Likewise. (VEX_W_0F383D_P_2): Likewise. (VEX_W_0F383E_P_2): Likewise. (VEX_W_0F383F_P_2): Likewise. (VEX_W_0F3840_P_2): Likewise. (VEX_W_0F3841_P_2): Likewise. (VEX_W_0F38DB_P_2): Likewise. (VEX_W_0F3A08_P_2): Likewise. (VEX_W_0F3A09_P_2): Likewise. (VEX_W_0F3A0A_P_2): Likewise. (VEX_W_0F3A0B_P_2): Likewise. (VEX_W_0F3A0C_P_2): Likewise. (VEX_W_0F3A0D_P_2): Likewise. (VEX_W_0F3A0E_P_2): Likewise. (VEX_W_0F3A0F_P_2): Likewise. (VEX_W_0F3A21_P_2): Likewise. (VEX_W_0F3A40_P_2): Likewise. (VEX_W_0F3A41_P_2): Likewise. (VEX_W_0F3A42_P_2): Likewise. (VEX_W_0F3A62_P_2): Likewise. (VEX_W_0F3A63_P_2): Likewise. (VEX_W_0F3ADF_P_2): Likewise. (VEX_LEN_0F77_P_0): New. (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11, PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E, PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52, PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59, PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C, PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F, PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F, PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4, PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2, PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6, PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C, PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2, PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2, PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5, PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE, PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1, PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4, PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8, PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB, PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE, PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2, PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5, PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832, PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries. (vex_table): Update VEX 0F28 and 0F29 entries. (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3, VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0, VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2, VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1, VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3, VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1, VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3, VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1, VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3, VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and VEX_LEN_0F3A0B_P_2 entries. (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1, VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1, VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0, VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2, VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15, VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1, VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29, VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0, VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1, VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1, VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1, VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1, VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1, VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2, VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3, VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3, VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3, VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3, VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2, VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2, VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2, VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2, VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3, VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2, VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2, VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2, VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2, VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3, VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1, VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0, VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3, VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2, VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2, VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2, VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2, VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2, VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2, VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3, VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2, VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2, VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0, VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2, VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2, VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2, VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2, VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2, VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2, VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2, VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2, VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2, VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2, VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2, VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0, VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2, VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2, VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2, VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2, VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2, VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2, VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2, VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2, VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2, VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2, VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and VEX_W_0F3ADF_P_2 entries. (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50, MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2, MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries. | |||||
| 2018-09-15 | x86: Set Vex=1 on VEX.128 only vmovq | H.J. Lu | 1 | -2/+0 | |
| AVX "VMOVQ xmm1, xmm2/m64" and "VMOVQ xmm1/m64, xmm2" can only be encoded with VEX.128. Set Vex=1 on VEX.128 only vmovq and update assembler tests. gas/ PR gas/23665 * testsuite/gas/i386/avx-scalar-intel.d: Updated. * testsuite/gas/i386/avx-scalar.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar.d: Likewise. opcodes/ PR gas/23665 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and VEX_LEN_0FD6_P_2 entries. * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq. * i386-tbl.h: Regenerated. | |||||
| 2018-09-14 | x86: Handle unsupported static rounding in vcvt[u]si2sd in 32-bit mode | H.J. Lu | 1 | -0/+11 | |
| Update x86 disassembler to handle the unsupported static rounding in vcvt[u]si2sd in 32-bit mode. gas/ PR binutils/23655 * testsuite/gas/i386/evex.d: Updated. opcodes/ PR binutils/23655 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for vcvtsi2sd%LQ and vcvtusi2sd%LQ. * i386-dis.c (EXxEVexR64): New. (evex_rounding_64_mode): Likewise. (OP_Rounding): Handle evex_rounding_64_mode. | |||||
| 2018-09-14 | x86: Properly decode EVEX.W in vcvt[u]si2s[sd] in 32-bit mode | H.J. Lu | 1 | -0/+8 | |
| Update x86 disassembler to ignore the EVEX.W bit in EVEX vcvt[u]si2s[sd] instructions in 32-bit mode. gas/ PR binutils/23655 * testsuite/gas/i386/evex.d: New file. * testsuite/gas/i386/evex.s: Likewise. * testsuite/gas/i386/i386.exp: Run evex. opcodes/ PR binutils/23655 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ. * i386-dis.c (Edqa): New. (dqa_mode): Likewise. (intel_operand_size): Handle dqa_mode as m_mode. (OP_E_register): Handle dqa_mode as dq_mode. (OP_E_memory): Set shift for dqa_mode based on address_mode. | |||||
| 2018-09-14 | i386: Reformat OP_E_memory | H.J. Lu | 1 | -2/+2 | |
| * i386-dis.c (OP_E_memory): Reformat. | |||||
| 2018-09-13 | x86-64: bndmk, bndldx, and bndstx don't allow RIP-relative addressing | Jan Beulich | 1 | -3/+14 | |
| 2018-08-14 | x86-64: Display eiz for address with the addr32 prefix | H.J. Lu | 1 | -7/+23 | |
| In 64-bit mode, display eiz for address with the addr32 prefix and without base nor index registers. For mov -0xccddef(,%eiz,), %rax disassembler now displays: 67 48 8b 04 25 11 22 33 ff mov -0xccddef(,%eiz,1),%rax instead of 67 48 8b 04 25 11 22 33 ff addr32 mov 0xffffffffff332211,%rax gas/ * testsuite/gas/i386/evex-no-scale-64.d: Updated. * testsuite/gas/i386/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/x86-64-addr32.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-addr32.d: Likewise. * testsuite/gas/i386/x86-64-addr32.s: Add %eiz tests. opcodes/ * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for address with the addr32 prefix and without base nor index registers. | |||||
| 2018-05-07 | Enable Intel MOVDIRI, MOVDIR64B instructions | H.J. Lu | 1 | -2/+46 | |
| gas/ * config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b. (cpu_noarch): Likewise. (process_suffix): Add check for register size. * doc/c-i386.texi: Document movdiri, movdir64b. * testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests. * testsuite/gas/i386/movdir-intel.d: New file. * testsuite/gas/i386/movdir.d: Likewise. * testsuite/gas/i386/movdir.s: Likewise. * testsuite/gas/i386/movdir64b-reg.s: Likewise. * testsuite/gas/i386/movdir64b-reg.l: Likewise. * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise. * testsuite/gas/i386/x86-64-movdir.d: Likewise. * testsuite/gas/i386/x86-64-movdir.s: Likewise. * testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise. * testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise. opcodes/ * i386-dis.c (Gva): New. (enum): Add PREFIX_0F38F8, PREFIX_0F38F9, MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0. (prefix_table): New instructions (see prefix above). (mod_table): New instructions (see prefix above). (OP_G): Handle va_mode. * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS, CPU_MOVDIR64B_FLAGS. (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B. * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B. (i386_cpu_flags): Add cpumovdiri and cpumovdir64b. * i386-opc.tbl: Add movidir{i,64b}. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. | |||||
| 2018-04-27 | Revert "Enable Intel MOVDIRI, MOVDIR64B instructions." | Igor Tsimbalist | 1 | -50/+4 | |
| This reverts commit a914a7c95895161c99533d5919b8504b37ea54a0. | |||||
| 2018-04-26 | Enable Intel MOVDIRI, MOVDIR64B instructions. | Igor Tsimbalist | 1 | -4/+50 | |
| gas/ * config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b. (cpu_noarch): Likewise. (process_suffix): Add check for register size. * doc/c-i386.texi: Document movdiri, movdir64b. * testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests. * testsuite/gas/i386/movdir-intel.d: New test. * testsuite/gas/i386/movdir.d: Likewise. * testsuite/gas/i386/movdir.s: Likewise. * testsuite/gas/i386/movdir64b-reg.s: Likewise. * testsuite/gas/i386/movdir64b-reg.l: Likewise. * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise. * testsuite/gas/i386/x86-64-movdir.d: Likewise. * testsuite/gas/i386/x86-64-movdir.s: Likewise. * testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise. * testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F38F8, PREFIX_0F38F9. (prefix_table): New instructions (see prefix above). Add Gva macro and handling in OP_G. * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS, CPU_MOVDIR64B_FLAGS. (cpu_flags): Likewise. (opcode_modifiers): Add AddrPrefixOpReg. (i386_opcode_modifier): Likewise. * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B. (i386_cpu_flags): Likewise. * i386-opc.tbl: Add movidir{i,64b}. * i386-init.h: Regenerate. * i386-tbl.h: Likewise. | |||||
| 2018-04-17 | Enable Intel CLDEMOTE instruction. | Igor Tsimbalist | 1 | -1/+28 | |
| gas/ * config/tc-i386.c (cpu_arch): Add .cldemote. * doc/c-i386.texi: Document cldemote/.cldemote. * testsuite/gas/i386/cldemote-intel.d: New. * testsuite/gas/i386/cldemote.d: Likewise. * testsuite/gas/i386/cldemote.s: Likewise. * testsuite/gas/i386/i386.exp: Run new tests. * testsuite/gas/i386/x86-64-cldemote-intel.d: New. * testsuite/gas/i386/x86-64-cldemote.d: Likewise. * testsuite/gas/i386/x86-64-cldemote.s: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops.d: Remove 0x0f1c NOP encoding that maps to cldemote. * testsuite/gas/i386/nops.d: Likewise. * testsuite/gas/i386/nops.s: Likewise. * testsuite/gas/i386/x86-64-nops.d: Likewise. * testsuite/gas/i386/x86-64-nops.s: Likewise. opcode/ * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0, PREFIX_0F1C. * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS, (cpu_flags): Add CpuCLDEMOTE. * i386-init.h: Regenerate. * i386-opc.h (enum): Add CpuCLDEMOTE, (i386_cpu_flags): Add cpucldemote. * i386-opc.tbl: Add cldemote. * i386-tbl.h: Regenerate. | |||||
| 2018-04-15 | x86: Allow 32-bit registers for tpause and umwait | H.J. Lu | 1 | -2/+2 | |
| Since only the first 32 bits of input operand are used for tpause and umwait, the REX.W bit is skipped. Both 32-bit registers and 64-bit registers are allowed. gas/ * testsuite/gas/i386/x86-64-waitpkg.s: Add 32-bit registers tests for tpause and umwait. * testsuite/gas/i386/x86-64-waitpkg-intel.d: Updated. * testsuite/gas/i386/x86-64-waitpkg.d: Likewise. opcodes/ * i386-dis.c (prefix_table): Replace Em with Edq on tpause and umwait. * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in 64-bit mode. * i386-tbl.h: Regenerated. | |||||
| 2018-04-11 | Enable Intel WAITPKG instructions. | Igor Tsimbalist | 1 | -4/+31 | |
| Intel has disclosed a set of new instructions for Tremont processor. The spec is https://software.intel.com/en-us/intel-architecture-instruction-set-extensions-programming-reference This patch enables Intel WAITPKG instructions. gas/ * config/tc-i386.c (cpu_arch): Add WAITPKG. (cpu_noarch): Likewise. * doc/c-i386.texi: Document WAITPKG. * i386/i386.exp: Run WAITPKG tests. * testsuite/gas/i386/waitpkg-intel.d: New test. * testsuite/gas/i386/waitpkg.d: Likewise. * testsuite/gas/i386/waitpkg.s: Likewise. * testsuite/gas/i386/x86-64-waitpkg-intel.d: Likewise. * testsuite/gas/i386/x86-64-waitpkg.d: Likewise. * testsuite/gas/i386/x86-64-waitpkg.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6, PREFIX_MOD_1_0FAE_REG_6. (va_mode): New. (OP_E_register): Use va_mode. * i386-dis-evex.h (prefix_table): New instructions (see prefixes above). * i386-gen.c (cpu_flag_init): Add WAITPKG. (cpu_flags): Likewise. * i386-opc.h (enum): Likewise. (i386_cpu_flags): Likewise. * i386-opc.tbl: Add umonitor, umwait, tpause. * i386-init.h: Regenerate. * i386-tbl.h: Likewise. | |||||
| 2018-04-04 | i386: Clear vex instead of vex.evex | H.J. Lu | 1 | -6/+1 | |
| "vex" has many fields to control how to decode an instruction. Clear all fields in "vex" before decoding an instruction to avoid using values left from the previous instruction. gas/ PR binutils/23025 * testsuite/gas/i386/prefix.s: Add tests for vcvtpd2dq with VEX and EVEX prefixes. * testsuite/gas/i386/prefix.d: Updated. opcodes/ PR binutils/23025 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w to 0. (print_insn): Clear vex instead of vex.evex. | |||||
| 2018-03-28 | x86: don't show suffixes for to-scalar-int conversion insns | Jan Beulich | 1 | -24/+14 | |
| In the course of folding their patterns (possible now that the pointless and partly even bogus VecESize are no longer in the way) I've noticed that vcvt*2usi, other than their vcvt*2si counterparts, don't allow for any suffixes. As that is supposedly intentional, make the disassembler consistently omit suffixes for all to-scalar-int conversion insns. | |||||
| 2018-03-22 | x86: fix swapped operand handling for BNDMOV | Jan Beulich | 1 | -3/+11 | |
| The wrong placement of the Load attribute in the templates prevented this from working. The disassembler also didn't handle this consistently with other similar dual-encoding insns. | |||||
| 2018-03-08 | x86/Intel: correct disassembly of fsub*/fdiv* | Jan Beulich | 1 | -8/+8 | |
| fsub/fsubr/fsubp/fsubrp as well as fdiv/fdivr/fdivp/fdivrp disassembly should match (a) the Intel SDM and (b) respective input fed to gas (both of course with the exception of when we intentionally convert bogus insns, accompanied by a warning). | |||||
| 2018-01-23 | Enable Intel PCONFIG instruction. | Igor Tsimbalist | 1 | -0/+1 | |
| Intel has disclosed a set of new instructions for Icelake processor. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf This patch enables Intel PCONFIG instruction. gas/ * config/tc-i386.c (cpu_arch): Add .pconfig. * doc/c-i386.texi: Document .pconfig. * testsuite/gas/i386/i386.exp: Add PCONFIG tests. * testsuite/gas/i386/pconfig-intel.d: New test. * testsuite/gas/i386/pconfig.d: Likewise. * testsuite/gas/i386/pconfig.s: Likewise. * testsuite/gas/i386/x86-64-pconfig-intel.d: Likewise. * testsuite/gas/i386/x86-64-pconfig.d: Likewise. * testsuite/gas/i386/x86-64-pconfig.s: Likewise. opcodes/ * i386-dis.c (enum): Add pconfig. * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS. (cpu_flags): Add CpuPCONFIG. * i386-opc.h (enum): Add CpuPCONFIG. (i386_cpu_flags): Add cpupconfig. * i386-opc.tbl: Add PCONFIG instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise. | |||||
| 2018-01-23 | Enable Intel WBNOINVD instruction. | Igor Tsimbalist | 1 | -1/+8 | |
| Intel has disclosed a set of new instructions for Icelake processor. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf This patch enables Intel WBNOINVD instruction. gas/ * config/tc-i386.c (cpu_arch): Add .wbnoinvd. * doc/c-i386.texi: Document .wbnoinvd. * testsuite/gas/i386/i386.exp: Add WBNOINVD tests. * testsuite/gas/i386/wbnoinvd-intel.d: New test. * testsuite/gas/i386/wbnoinvd.d: Likewise. * testsuite/gas/i386/wbnoinvd.s: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd-intel.d: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd.d: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F09. * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS. (cpu_flags): Add CpuWBNOINVD. * i386-opc.h (enum): Add CpuWBNOINVD. (i386_cpu_flags): Add cpuwbnoinvd. * i386-opc.tbl: Add WBNOINVD instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise. | |||||
| 2018-01-03 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 | |
| 2017-11-24 | x86: don't omit disambiguating suffixes from "fi*" | Jan Beulich | 1 | -12/+12 | |
| "fi*" typically come in two (loads/stores: three) flavors, distinguished by the suffix. Don't omit the 's' one when disassembling. | |||||
| 2017-11-23 | x86: fix AVX-512 16-bit addressing | Jan Beulich | 1 | -0/+2 | |
| Despite EVEX encodings not being available in real and VM86 modes, 16-bit addressing still needs to be handled properly for 16-bit protected mode as well as 16-bit addressing in 32-bit mode. Neither should displacements be dropped silently by the assembler, nor should the disassembler fail to correctly scale 8-bit displacements. | |||||
| 2017-11-23 | x86: correct UDn | Jan Beulich | 1 | -4/+4 | |
| Make the assembler recognize UD0, supporting only the newer form expecting a ModR/M byte. Make assembler and disassembler properly emit / expect a ModR/M byte for UD1. For the testsuite, as arch-4 already tests all UDn, avoid producing a huge delta for other tests using UD2B by making them use UD2 instead. | |||||
| 2017-11-16 | x86: ignore high register select bit(s) in 32- and 16-bit modes | Jan Beulich | 1 | -28/+36 | |
| While commits 9889cbb14e ("Check invalid mask registers") and abfcb414b9 ("X86: Ignore REX_B bit for 32-bit XOP instructions") went a bit into the right direction, this wasn't quite enough: - VEX.vvvv has its high bit ignored - EVEX.vvvv has its high bit ignored together with EVEX.v' - the high bits of {,E}VEX.vvvv should not be prematurely zapped, to allow proper checking of them when the fields has to hold al ones - when the high bits of an immediate specify a register, bit 7 is ignored | |||||
| 2017-11-15 | x86: use correct register names | Jan Beulich | 1 | -3/+3 | |
| VEX.W may be legitimately set (and is then ignored by the CPU) for non-64-bit code. Don't print 64-bit register names in such a case, by utilizing that REX_W would never be set for non-64-bit code, and that it is being set from VEX.W by generic decoding. A test for this is going to be introduced in the next patch of this series. | |||||
| 2017-11-15 | x86: drop VEXI4_Fixup() | Jan Beulich | 1 | -50/+37 | |
| The low four bits of an immediate being set when the high bits specify a fourth register operand is not a problem: CPUs ignore these bits rather than raising #UD. Take care of incrementing codep in OP_EX_VexW() instead. | |||||
| 2017-11-14 | x86: add disassembler support for XOP VPCOM* pseudo-ops | Jan Beulich | 1 | -8/+62 | |
| Matching up with the assembler, which already supports them. | |||||
| 2017-10-23 | Enable Intel AVX512_BITALG instructions. | Igor Tsimbalist | 1 | -0/+3 | |
| Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .avx512_bitalg. (cpu_noarch): noavx512_bitalg. * doc/c-i386.texi: Document .avx512_bitalg, noavx512_bitalg. * testsuite/gas/i386/i386.exp: Add AVX512_BITALG tests. * testsuite/gas/i386/avx512f_bitalg-intel.d: New test. * testsuite/gas/i386/avx512f_bitalg.d: Likewise. * testsuite/gas/i386/avx512f_bitalg.s: Likewise. * testsuite/gas/i386/avx512vl_bitalg-intel.d: Likewise. * testsuite/gas/i386/avx512vl_bitalg.d: Likewise. * testsuite/gas/i386/avx512vl_bitalg.s: Likewise. * testsuite/gas/i386/x86-64-avx512f_bitalg-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_bitalg.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_bitalg.s: Likewise. * testsuite/gas/i386/x86-64-avx512vl_bitalg-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_bitalg.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_bitalg.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F. (enum): Add EVEX_W_0F3854_P_2. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG, CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_BITALG. * i386-opc.h (enum): Add CpuAVX512_BITALG. (i386_cpu_flags): Add cpuavx512_bitalg.. * i386-opc.tbl: Add Intel AVX512_BITALG instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise. | |||||
| 2017-10-23 | Enable Intel AVX512_VNNI instructions. | Igor Tsimbalist | 1 | -0/+2 | |
| Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .avx512_vnni. (cpu_noarch): Add noavx512_vnni. * doc/c-i386.texi: Document .avx512_vnni. * testsuite/gas/i386/i386.exp: Add AVX512_VNNI tests. * testsuite/gas/i386/avx512vnni-intel.d: New test. * testsuite/gas/i386/avx512vnni.d: Likewise. * testsuite/gas/i386/avx512vnni.s: Likewise. * testsuite/gas/i386/avx512vnni_vl-intel.d: Likewise. * testsuite/gas/i386/avx512vnni_vl.d: Likewise. * testsuite/gas/i386/avx512vnni_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512vnni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni.s: Likewise. * testsuite/gas/i386/x86-64-avx512vnni_vl-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni_vl.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI, CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_VNNI. * i386-opc.h (enum): Add CpuAVX512_VNNI. (i386_cpu_flags): Add cpuavx512_vnni. * i386-opc.tbl Add Intel AVX512_VNNI instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise. | |||||
| 2017-10-23 | Enable Intel VPCLMULQDQ instruction. | Igor Tsimbalist | 1 | -12/+2 | |
| Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add VPCLMULQDQ. * doc/c-i386.texi: Document VPCLMULQDQ. * testsuite/gas/i386/i386.exp: Run VPCLMULQDQ tests. * testsuite/gas/i386/avx512f_vpclmulqdq-intel.d: New test. * testsuite/gas/i386/avx512f_vpclmulqdq-wig.s: Ditto. * testsuite/gas/i386/avx512f_vpclmulqdq-wig1-intel.d: Ditto. * testsuite/gas/i386/avx512f_vpclmulqdq-wig1.d: Ditto. * testsuite/gas/i386/avx512f_vpclmulqdq.d: Ditto. * testsuite/gas/i386/avx512f_vpclmulqdq.s: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq-wig.s: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq-wig1-intel.d: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq-wig1.d: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq.d: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq.s: Ditto. * testsuite/gas/i386/vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/vpclmulqdq.d: Ditto. * testsuite/gas/i386/vpclmulqdq.s: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig.s: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig.s: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.s: Ditto. * testsuite/gas/i386/x86-64-vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/x86-64-vpclmulqdq.d: Ditto. * testsuite/gas/i386/x86-64-vpclmulqdq.s: Ditto. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44. (enum): Remove VEX_LEN_0F3A44_P_2. (vex_len_table): Ditto. (enum): Remove VEX_W_0F3A44_P_2. (vew_w_table): Ditto. (prefix_table): Adjust instructions (see prefixes above). * i386-dis-evex.h (evex_table): Add new instructions (see prefixes above). * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ. (bitfield_cpu_flags): Ditto. * i386-opc.h (enum): Ditto. (i386_cpu_flags): Ditto. (CpuUnused): Comment out to avoid zero-width field problem. * i386-opc.tbl (vpclmulqdq): New instruction. * i386-init.h: Regenerate. * i386-tbl.h: Ditto. | |||||
| 2017-10-23 | Enable Intel VAES instructions. | Igor Tsimbalist | 1 | -48/+8 | |
| Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add VAES. * doc/c-i386.texi: Document VAES. * testsuite/gas/i386/i386.exp: Run VAES tests. * testsuite/gas/i386/avx512f_vaes-intel.d: New test. * testsuite/gas/i386/avx512f_vaes-wig.s: Ditto. * testsuite/gas/i386/avx512f_vaes-wig1-intel.d: Ditto. * testsuite/gas/i386/avx512f_vaes-wig1.d: Ditto. * testsuite/gas/i386/avx512f_vaes.d: Ditto. * testsuite/gas/i386/avx512f_vaes.s: Ditto. * testsuite/gas/i386/avx512vl_vaes-intel.d: Ditto. * testsuite/gas/i386/avx512vl_vaes-wig.s: Ditto. * testsuite/gas/i386/avx512vl_vaes-wig1-intel.d: Ditto. * testsuite/gas/i386/avx512vl_vaes-wig1.d: Ditto. * testsuite/gas/i386/avx512vl_vaes.d: Ditto. * testsuite/gas/i386/avx512vl_vaes.s: Ditto. * testsuite/gas/i386/vaes-intel.d: Ditto. * testsuite/gas/i386/vaes.d: Ditto. * testsuite/gas/i386/vaes.s: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes-wig.s: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes-wig1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes-wig1.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes.s: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig.s: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig1.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes.s: Ditto. * testsuite/gas/i386/x86-64-vaes-intel.d: Ditto. * testsuite/gas/i386/x86-64-vaes.d: Ditto. * testsuite/gas/i386/x86-64-vaes.s: Ditto. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF. (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2, VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2. (vex_len_table): Ditto. (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2, VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2. (vew_w_table): Ditto. (prefix_table): Adjust instructions (see prefixes above). * i386-dis-evex.h (evex_table): Add new instructions (see prefixes above). * i386-gen.c (cpu_flag_init): Add VAES. (bitfield_cpu_flags): Ditto. * i386-opc.h (enum): Ditto. (i386_cpu_flags): Ditto. * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions. * i386-init.h: Regenerate. * i386-tbl.h: Ditto. | |||||
| 2017-10-23 | Enable Intel GFNI instructions. | Igor Tsimbalist | 1 | -8/+78 | |
| Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .gfni. * doc/c-i386.texi: Document .gfni. * testsuite/gas/i386/i386.exp: Add GFNI tests. * testsuite/gas/i386/avx.s: New GFNI test. * testsuite/gas/i386/x86-64-avx.s: Likewise. * testsuite/gas/i386/avx.d: Adjust. * testsuite/gas/i386/avx-intel.d: Likewise * testsuite/gas/i386/ilp32/x86-64-avx-intel.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-avx.d: Likewise. * testsuite/gas/i386/avx512f_gfni-intel.d: New test. * testsuite/gas/i386/avx512f_gfni.d: Likewise. * testsuite/gas/i386/avx512f_gfni.s: Likewise. * testsuite/gas/i386/avx512vl_gfni-intel.d: Likewise. * testsuite/gas/i386/avx512vl_gfni.d: Likewise. * testsuite/gas/i386/avx512vl_gfni.s: Likewise. * testsuite/gas/i386/gfni-intel.d: Likewise. * testsuite/gas/i386/gfni.d: Likewise. * testsuite/gas/i386/gfni.s: Likewise. * testsuite/gas/i386/x86-64-avx512f_gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_gfni.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_gfni.s: Likewise. * testsuite/gas/i386/x86-64-avx512vl_gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_gfni.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_gfni.s: Likewise. * testsuite/gas/i386/x86-64-avx_gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx_gfni.d: Likewise. * testsuite/gas/i386/x86-64-avx_gfni.s: Likewise. * testsuite/gas/i386/x86-64-gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-gfni.d: Likewise. * testsuite/gas/i386/x86-64-gfni.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF. (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2. (prefix_table): Updated (see prefixes above). (three_byte_table): Likewise. (vex_w_table): Likewise. * i386-dis-evex.h: Likewise. * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI. (cpu_flags): Add CpuGFNI. * i386-opc.h (enum): Add CpuGFNI. (i386_cpu_flags): Add cpugfni. * i386-opc.tbl: Add Intel GFNI instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise. | |||||
| 2017-10-23 | Enable Intel AVX512_VBMI2 instructions. | Igor Tsimbalist | 1 | -2/+32 | |
| Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .avx512_vbmi2. (cpu_noarch): noavx512_vbmi2. * doc/c-i386.texi: Document .avx512_vbmi2, noavx512_vbmi2. * testsuite/gas/i386/i386.exp: Add AVX512_VBMI2 tests. * testsuite/gas/i386/avx512vbmi2-intel.d: New test. * testsuite/gas/i386/avx512vbmi2.d: Likewise. * testsuite/gas/i386/avx512vbmi2.s: Likewise. * testsuite/gas/i386/avx512vbmi2_vl-intel.d: Likewise. * testsuite/gas/i386/avx512vbmi2_vl.d: Likewise. * testsuite/gas/i386/avx512vbmi2_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2.s: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2_vl-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2_vl.s: Likewise. opcodes/ * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode. Define EXbScalar and EXwScalar for OP_EX. (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71, PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73. (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2, EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2, EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2, EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2. (intel_operand_size): Handle b_scalar_mode and w_scalar_mode. (OP_E_memory): Likewise. * i386-dis-evex.h: Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2, CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_VBMI2. * i386-opc.h (enum): Add CpuAVX512_VBMI2. (i386_cpu_flags): Add cpuavx512_vbmi2. * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise. | |||||
| 2017-09-09 | x86: Remove restriction on NOTRACK prefix position | H.J. Lu | 1 | -16/+2 | |
| Since the NOTRACK prefix is no longer required to be the last prefix before the REX prefix, restriction on the NOTRACK prefix position is removed from assembler as well as disassembler. Assembler encodes the NOTRACK prefix the same way as the DS segment register, which places it before other prefixes. Disassembler displays prefixes in the order they appear. gas/ * config/tc-i386.c (NOTRACK_PREFIX): Removed. (REX_PREFIX): Updated. (MAX_PREFIXES): Likewise. (parse_insn): Remove restriction on NOTRACK prefix position. * testsuite/gas/i386/notrack.s: Add tests with NOTRACK prefix before other prefixes. * testsuite/gas/i386/x86-64-notrack.s: Likewise. * testsuite/gas/i386/notrackbad.s: Remove tests with NOTRACK prefix before other prefixes. * testsuite/gas/i386/x86-64-notrackbad.s: Likewise. * testsuite/gas/i386/notrack-intel.d: Updated. * testsuite/gas/i386/notrack.d: Likewise. * testsuite/gas/i386/notrackbad.l: Likewise. * testsuite/gas/i386/x86-64-notrack-intel.d: Likewise. * testsuite/gas/i386/x86-64-notrack.d: Likewise. * testsuite/gas/i386/x86-64-notrackbad.l: Likewise. opcodes/ * i386-dis.c (last_active_prefix): Removed. (ckprefix): Don't set last_active_prefix. (NOTRACK_Fixup): Don't check last_active_prefix. | |||||
| 2017-07-18 | Fix spelling typos. | Yuri Chornovian | 1 | -1/+1 | |
| 2017-07-05 | X86: Disassemble primary opcode map's group 2 ModRM.reg == 6 aliases correctly | Borislav Petkov | 1 | -6/+6 | |
| The instructions are not documented in the Intel SDM but are documented in the AMD APM as an alias to the group 2, ModRM.reg == 4 variant. Both AMD and Intel CPUs execute the C[0-1] and D[0-3] instructions as expected, i.e., like the /4 aliases: #include <stdio.h> int main(void) { int a = 2; printf ("a before: %d\n", a); asm volatile(".byte 0xd0,0xf0" /* SHL %al */ : "+a" (a)); printf("a after : %d\n", a); return 0; } $ ./a.out a before: 2 a after : 4 | |||||
| 2017-06-21 | x86: CET v2.0: Update incssp and setssbsy | H.J. Lu | 1 | -11/+12 | |
| Update x86 assembler and disassembler for CET v2.0: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf 1. incsspd and incsspq are changed to take a register opeand with a different opcode. 2. setssbsy is changed to take no opeand with a different opcode. gas/ * testsuite/gas/i386/cet-intel.d: Updated. * testsuite/gas/i386/cet.d: Likewise. * testsuite/gas/i386/x86-64-cet-intel.d: Likewise. * testsuite/gas/i386/x86-64-cet.d: Likewise. * testsuite/gas/i386/cet.s: Update incsspd and setssbsy tests. * testsuite/gas/i386/x86-64-cet.s: Likewise. opcodes/ * i386-dis.c (RM_0FAE_REG_5): Removed. (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. (PREFIX_MOD_3_0F01_REG_5_RM_0): New. (PREFIX_MOD_3_0FAE_REG_5): Likewise. (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add PREFIX_MOD_3_0F01_REG_5_RM_0. (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add PREFIX_MOD_3_0FAE_REG_5. (mod_table): Update MOD_0FAE_REG_5. (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5. * i386-opc.tbl: Update incsspd, incsspq and setssbsy. * i386-tbl.h: Regenerated. | |||||
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