aboutsummaryrefslogtreecommitdiff
path: root/opcodes/i386-dis.c
AgeCommit message (Collapse)AuthorFilesLines
2018-05-07Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu1-2/+46
gas/ * config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b. (cpu_noarch): Likewise. (process_suffix): Add check for register size. * doc/c-i386.texi: Document movdiri, movdir64b. * testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests. * testsuite/gas/i386/movdir-intel.d: New file. * testsuite/gas/i386/movdir.d: Likewise. * testsuite/gas/i386/movdir.s: Likewise. * testsuite/gas/i386/movdir64b-reg.s: Likewise. * testsuite/gas/i386/movdir64b-reg.l: Likewise. * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise. * testsuite/gas/i386/x86-64-movdir.d: Likewise. * testsuite/gas/i386/x86-64-movdir.s: Likewise. * testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise. * testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise. opcodes/ * i386-dis.c (Gva): New. (enum): Add PREFIX_0F38F8, PREFIX_0F38F9, MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0. (prefix_table): New instructions (see prefix above). (mod_table): New instructions (see prefix above). (OP_G): Handle va_mode. * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS, CPU_MOVDIR64B_FLAGS. (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B. * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B. (i386_cpu_flags): Add cpumovdiri and cpumovdir64b. * i386-opc.tbl: Add movidir{i,64b}. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2018-04-27Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist1-50/+4
This reverts commit a914a7c95895161c99533d5919b8504b37ea54a0.
2018-04-26Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist1-4/+50
gas/ * config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b. (cpu_noarch): Likewise. (process_suffix): Add check for register size. * doc/c-i386.texi: Document movdiri, movdir64b. * testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests. * testsuite/gas/i386/movdir-intel.d: New test. * testsuite/gas/i386/movdir.d: Likewise. * testsuite/gas/i386/movdir.s: Likewise. * testsuite/gas/i386/movdir64b-reg.s: Likewise. * testsuite/gas/i386/movdir64b-reg.l: Likewise. * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise. * testsuite/gas/i386/x86-64-movdir.d: Likewise. * testsuite/gas/i386/x86-64-movdir.s: Likewise. * testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise. * testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F38F8, PREFIX_0F38F9. (prefix_table): New instructions (see prefix above). Add Gva macro and handling in OP_G. * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS, CPU_MOVDIR64B_FLAGS. (cpu_flags): Likewise. (opcode_modifiers): Add AddrPrefixOpReg. (i386_opcode_modifier): Likewise. * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B. (i386_cpu_flags): Likewise. * i386-opc.tbl: Add movidir{i,64b}. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-04-17Enable Intel CLDEMOTE instruction.Igor Tsimbalist1-1/+28
gas/ * config/tc-i386.c (cpu_arch): Add .cldemote. * doc/c-i386.texi: Document cldemote/.cldemote. * testsuite/gas/i386/cldemote-intel.d: New. * testsuite/gas/i386/cldemote.d: Likewise. * testsuite/gas/i386/cldemote.s: Likewise. * testsuite/gas/i386/i386.exp: Run new tests. * testsuite/gas/i386/x86-64-cldemote-intel.d: New. * testsuite/gas/i386/x86-64-cldemote.d: Likewise. * testsuite/gas/i386/x86-64-cldemote.s: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops.d: Remove 0x0f1c NOP encoding that maps to cldemote. * testsuite/gas/i386/nops.d: Likewise. * testsuite/gas/i386/nops.s: Likewise. * testsuite/gas/i386/x86-64-nops.d: Likewise. * testsuite/gas/i386/x86-64-nops.s: Likewise. opcode/ * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0, PREFIX_0F1C. * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS, (cpu_flags): Add CpuCLDEMOTE. * i386-init.h: Regenerate. * i386-opc.h (enum): Add CpuCLDEMOTE, (i386_cpu_flags): Add cpucldemote. * i386-opc.tbl: Add cldemote. * i386-tbl.h: Regenerate.
2018-04-15x86: Allow 32-bit registers for tpause and umwaitH.J. Lu1-2/+2
Since only the first 32 bits of input operand are used for tpause and umwait, the REX.W bit is skipped. Both 32-bit registers and 64-bit registers are allowed. gas/ * testsuite/gas/i386/x86-64-waitpkg.s: Add 32-bit registers tests for tpause and umwait. * testsuite/gas/i386/x86-64-waitpkg-intel.d: Updated. * testsuite/gas/i386/x86-64-waitpkg.d: Likewise. opcodes/ * i386-dis.c (prefix_table): Replace Em with Edq on tpause and umwait. * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in 64-bit mode. * i386-tbl.h: Regenerated.
2018-04-11Enable Intel WAITPKG instructions.Igor Tsimbalist1-4/+31
Intel has disclosed a set of new instructions for Tremont processor. The spec is https://software.intel.com/en-us/intel-architecture-instruction-set-extensions-programming-reference This patch enables Intel WAITPKG instructions. gas/ * config/tc-i386.c (cpu_arch): Add WAITPKG. (cpu_noarch): Likewise. * doc/c-i386.texi: Document WAITPKG. * i386/i386.exp: Run WAITPKG tests. * testsuite/gas/i386/waitpkg-intel.d: New test. * testsuite/gas/i386/waitpkg.d: Likewise. * testsuite/gas/i386/waitpkg.s: Likewise. * testsuite/gas/i386/x86-64-waitpkg-intel.d: Likewise. * testsuite/gas/i386/x86-64-waitpkg.d: Likewise. * testsuite/gas/i386/x86-64-waitpkg.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6, PREFIX_MOD_1_0FAE_REG_6. (va_mode): New. (OP_E_register): Use va_mode. * i386-dis-evex.h (prefix_table): New instructions (see prefixes above). * i386-gen.c (cpu_flag_init): Add WAITPKG. (cpu_flags): Likewise. * i386-opc.h (enum): Likewise. (i386_cpu_flags): Likewise. * i386-opc.tbl: Add umonitor, umwait, tpause. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-04-04i386: Clear vex instead of vex.evexH.J. Lu1-6/+1
"vex" has many fields to control how to decode an instruction. Clear all fields in "vex" before decoding an instruction to avoid using values left from the previous instruction. gas/ PR binutils/23025 * testsuite/gas/i386/prefix.s: Add tests for vcvtpd2dq with VEX and EVEX prefixes. * testsuite/gas/i386/prefix.d: Updated. opcodes/ PR binutils/23025 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w to 0. (print_insn): Clear vex instead of vex.evex.
2018-03-28x86: don't show suffixes for to-scalar-int conversion insnsJan Beulich1-24/+14
In the course of folding their patterns (possible now that the pointless and partly even bogus VecESize are no longer in the way) I've noticed that vcvt*2usi, other than their vcvt*2si counterparts, don't allow for any suffixes. As that is supposedly intentional, make the disassembler consistently omit suffixes for all to-scalar-int conversion insns.
2018-03-22x86: fix swapped operand handling for BNDMOVJan Beulich1-3/+11
The wrong placement of the Load attribute in the templates prevented this from working. The disassembler also didn't handle this consistently with other similar dual-encoding insns.
2018-03-08x86/Intel: correct disassembly of fsub*/fdiv*Jan Beulich1-8/+8
fsub/fsubr/fsubp/fsubrp as well as fdiv/fdivr/fdivp/fdivrp disassembly should match (a) the Intel SDM and (b) respective input fed to gas (both of course with the exception of when we intentionally convert bogus insns, accompanied by a warning).
2018-01-23Enable Intel PCONFIG instruction.Igor Tsimbalist1-0/+1
Intel has disclosed a set of new instructions for Icelake processor. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf This patch enables Intel PCONFIG instruction. gas/ * config/tc-i386.c (cpu_arch): Add .pconfig. * doc/c-i386.texi: Document .pconfig. * testsuite/gas/i386/i386.exp: Add PCONFIG tests. * testsuite/gas/i386/pconfig-intel.d: New test. * testsuite/gas/i386/pconfig.d: Likewise. * testsuite/gas/i386/pconfig.s: Likewise. * testsuite/gas/i386/x86-64-pconfig-intel.d: Likewise. * testsuite/gas/i386/x86-64-pconfig.d: Likewise. * testsuite/gas/i386/x86-64-pconfig.s: Likewise. opcodes/ * i386-dis.c (enum): Add pconfig. * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS. (cpu_flags): Add CpuPCONFIG. * i386-opc.h (enum): Add CpuPCONFIG. (i386_cpu_flags): Add cpupconfig. * i386-opc.tbl: Add PCONFIG instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-01-23Enable Intel WBNOINVD instruction.Igor Tsimbalist1-1/+8
Intel has disclosed a set of new instructions for Icelake processor. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf This patch enables Intel WBNOINVD instruction. gas/ * config/tc-i386.c (cpu_arch): Add .wbnoinvd. * doc/c-i386.texi: Document .wbnoinvd. * testsuite/gas/i386/i386.exp: Add WBNOINVD tests. * testsuite/gas/i386/wbnoinvd-intel.d: New test. * testsuite/gas/i386/wbnoinvd.d: Likewise. * testsuite/gas/i386/wbnoinvd.s: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd-intel.d: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd.d: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F09. * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS. (cpu_flags): Add CpuWBNOINVD. * i386-opc.h (enum): Add CpuWBNOINVD. (i386_cpu_flags): Add cpuwbnoinvd. * i386-opc.tbl: Add WBNOINVD instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-11-24x86: don't omit disambiguating suffixes from "fi*"Jan Beulich1-12/+12
"fi*" typically come in two (loads/stores: three) flavors, distinguished by the suffix. Don't omit the 's' one when disassembling.
2017-11-23x86: fix AVX-512 16-bit addressingJan Beulich1-0/+2
Despite EVEX encodings not being available in real and VM86 modes, 16-bit addressing still needs to be handled properly for 16-bit protected mode as well as 16-bit addressing in 32-bit mode. Neither should displacements be dropped silently by the assembler, nor should the disassembler fail to correctly scale 8-bit displacements.
2017-11-23x86: correct UDnJan Beulich1-4/+4
Make the assembler recognize UD0, supporting only the newer form expecting a ModR/M byte. Make assembler and disassembler properly emit / expect a ModR/M byte for UD1. For the testsuite, as arch-4 already tests all UDn, avoid producing a huge delta for other tests using UD2B by making them use UD2 instead.
2017-11-16x86: ignore high register select bit(s) in 32- and 16-bit modesJan Beulich1-28/+36
While commits 9889cbb14e ("Check invalid mask registers") and abfcb414b9 ("X86: Ignore REX_B bit for 32-bit XOP instructions") went a bit into the right direction, this wasn't quite enough: - VEX.vvvv has its high bit ignored - EVEX.vvvv has its high bit ignored together with EVEX.v' - the high bits of {,E}VEX.vvvv should not be prematurely zapped, to allow proper checking of them when the fields has to hold al ones - when the high bits of an immediate specify a register, bit 7 is ignored
2017-11-15x86: use correct register namesJan Beulich1-3/+3
VEX.W may be legitimately set (and is then ignored by the CPU) for non-64-bit code. Don't print 64-bit register names in such a case, by utilizing that REX_W would never be set for non-64-bit code, and that it is being set from VEX.W by generic decoding. A test for this is going to be introduced in the next patch of this series.
2017-11-15x86: drop VEXI4_Fixup()Jan Beulich1-50/+37
The low four bits of an immediate being set when the high bits specify a fourth register operand is not a problem: CPUs ignore these bits rather than raising #UD. Take care of incrementing codep in OP_EX_VexW() instead.
2017-11-14x86: add disassembler support for XOP VPCOM* pseudo-opsJan Beulich1-8/+62
Matching up with the assembler, which already supports them.
2017-10-23Enable Intel AVX512_BITALG instructions.Igor Tsimbalist1-0/+3
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .avx512_bitalg. (cpu_noarch): noavx512_bitalg. * doc/c-i386.texi: Document .avx512_bitalg, noavx512_bitalg. * testsuite/gas/i386/i386.exp: Add AVX512_BITALG tests. * testsuite/gas/i386/avx512f_bitalg-intel.d: New test. * testsuite/gas/i386/avx512f_bitalg.d: Likewise. * testsuite/gas/i386/avx512f_bitalg.s: Likewise. * testsuite/gas/i386/avx512vl_bitalg-intel.d: Likewise. * testsuite/gas/i386/avx512vl_bitalg.d: Likewise. * testsuite/gas/i386/avx512vl_bitalg.s: Likewise. * testsuite/gas/i386/x86-64-avx512f_bitalg-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_bitalg.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_bitalg.s: Likewise. * testsuite/gas/i386/x86-64-avx512vl_bitalg-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_bitalg.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_bitalg.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F. (enum): Add EVEX_W_0F3854_P_2. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG, CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_BITALG. * i386-opc.h (enum): Add CpuAVX512_BITALG. (i386_cpu_flags): Add cpuavx512_bitalg.. * i386-opc.tbl: Add Intel AVX512_BITALG instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2017-10-23Enable Intel AVX512_VNNI instructions.Igor Tsimbalist1-0/+2
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .avx512_vnni. (cpu_noarch): Add noavx512_vnni. * doc/c-i386.texi: Document .avx512_vnni. * testsuite/gas/i386/i386.exp: Add AVX512_VNNI tests. * testsuite/gas/i386/avx512vnni-intel.d: New test. * testsuite/gas/i386/avx512vnni.d: Likewise. * testsuite/gas/i386/avx512vnni.s: Likewise. * testsuite/gas/i386/avx512vnni_vl-intel.d: Likewise. * testsuite/gas/i386/avx512vnni_vl.d: Likewise. * testsuite/gas/i386/avx512vnni_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512vnni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni.s: Likewise. * testsuite/gas/i386/x86-64-avx512vnni_vl-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni_vl.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI, CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_VNNI. * i386-opc.h (enum): Add CpuAVX512_VNNI. (i386_cpu_flags): Add cpuavx512_vnni. * i386-opc.tbl Add Intel AVX512_VNNI instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2017-10-23Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist1-12/+2
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add VPCLMULQDQ. * doc/c-i386.texi: Document VPCLMULQDQ. * testsuite/gas/i386/i386.exp: Run VPCLMULQDQ tests. * testsuite/gas/i386/avx512f_vpclmulqdq-intel.d: New test. * testsuite/gas/i386/avx512f_vpclmulqdq-wig.s: Ditto. * testsuite/gas/i386/avx512f_vpclmulqdq-wig1-intel.d: Ditto. * testsuite/gas/i386/avx512f_vpclmulqdq-wig1.d: Ditto. * testsuite/gas/i386/avx512f_vpclmulqdq.d: Ditto. * testsuite/gas/i386/avx512f_vpclmulqdq.s: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq-wig.s: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq-wig1-intel.d: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq-wig1.d: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq.d: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq.s: Ditto. * testsuite/gas/i386/vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/vpclmulqdq.d: Ditto. * testsuite/gas/i386/vpclmulqdq.s: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig.s: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig.s: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.s: Ditto. * testsuite/gas/i386/x86-64-vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/x86-64-vpclmulqdq.d: Ditto. * testsuite/gas/i386/x86-64-vpclmulqdq.s: Ditto. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44. (enum): Remove VEX_LEN_0F3A44_P_2. (vex_len_table): Ditto. (enum): Remove VEX_W_0F3A44_P_2. (vew_w_table): Ditto. (prefix_table): Adjust instructions (see prefixes above). * i386-dis-evex.h (evex_table): Add new instructions (see prefixes above). * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ. (bitfield_cpu_flags): Ditto. * i386-opc.h (enum): Ditto. (i386_cpu_flags): Ditto. (CpuUnused): Comment out to avoid zero-width field problem. * i386-opc.tbl (vpclmulqdq): New instruction. * i386-init.h: Regenerate. * i386-tbl.h: Ditto.
2017-10-23Enable Intel VAES instructions.Igor Tsimbalist1-48/+8
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add VAES. * doc/c-i386.texi: Document VAES. * testsuite/gas/i386/i386.exp: Run VAES tests. * testsuite/gas/i386/avx512f_vaes-intel.d: New test. * testsuite/gas/i386/avx512f_vaes-wig.s: Ditto. * testsuite/gas/i386/avx512f_vaes-wig1-intel.d: Ditto. * testsuite/gas/i386/avx512f_vaes-wig1.d: Ditto. * testsuite/gas/i386/avx512f_vaes.d: Ditto. * testsuite/gas/i386/avx512f_vaes.s: Ditto. * testsuite/gas/i386/avx512vl_vaes-intel.d: Ditto. * testsuite/gas/i386/avx512vl_vaes-wig.s: Ditto. * testsuite/gas/i386/avx512vl_vaes-wig1-intel.d: Ditto. * testsuite/gas/i386/avx512vl_vaes-wig1.d: Ditto. * testsuite/gas/i386/avx512vl_vaes.d: Ditto. * testsuite/gas/i386/avx512vl_vaes.s: Ditto. * testsuite/gas/i386/vaes-intel.d: Ditto. * testsuite/gas/i386/vaes.d: Ditto. * testsuite/gas/i386/vaes.s: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes-wig.s: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes-wig1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes-wig1.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes.s: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig.s: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig1.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes.s: Ditto. * testsuite/gas/i386/x86-64-vaes-intel.d: Ditto. * testsuite/gas/i386/x86-64-vaes.d: Ditto. * testsuite/gas/i386/x86-64-vaes.s: Ditto. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF. (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2, VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2. (vex_len_table): Ditto. (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2, VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2. (vew_w_table): Ditto. (prefix_table): Adjust instructions (see prefixes above). * i386-dis-evex.h (evex_table): Add new instructions (see prefixes above). * i386-gen.c (cpu_flag_init): Add VAES. (bitfield_cpu_flags): Ditto. * i386-opc.h (enum): Ditto. (i386_cpu_flags): Ditto. * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions. * i386-init.h: Regenerate. * i386-tbl.h: Ditto.
2017-10-23Enable Intel GFNI instructions.Igor Tsimbalist1-8/+78
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .gfni. * doc/c-i386.texi: Document .gfni. * testsuite/gas/i386/i386.exp: Add GFNI tests. * testsuite/gas/i386/avx.s: New GFNI test. * testsuite/gas/i386/x86-64-avx.s: Likewise. * testsuite/gas/i386/avx.d: Adjust. * testsuite/gas/i386/avx-intel.d: Likewise * testsuite/gas/i386/ilp32/x86-64-avx-intel.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-avx.d: Likewise. * testsuite/gas/i386/avx512f_gfni-intel.d: New test. * testsuite/gas/i386/avx512f_gfni.d: Likewise. * testsuite/gas/i386/avx512f_gfni.s: Likewise. * testsuite/gas/i386/avx512vl_gfni-intel.d: Likewise. * testsuite/gas/i386/avx512vl_gfni.d: Likewise. * testsuite/gas/i386/avx512vl_gfni.s: Likewise. * testsuite/gas/i386/gfni-intel.d: Likewise. * testsuite/gas/i386/gfni.d: Likewise. * testsuite/gas/i386/gfni.s: Likewise. * testsuite/gas/i386/x86-64-avx512f_gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_gfni.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_gfni.s: Likewise. * testsuite/gas/i386/x86-64-avx512vl_gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_gfni.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_gfni.s: Likewise. * testsuite/gas/i386/x86-64-avx_gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx_gfni.d: Likewise. * testsuite/gas/i386/x86-64-avx_gfni.s: Likewise. * testsuite/gas/i386/x86-64-gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-gfni.d: Likewise. * testsuite/gas/i386/x86-64-gfni.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF. (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2. (prefix_table): Updated (see prefixes above). (three_byte_table): Likewise. (vex_w_table): Likewise. * i386-dis-evex.h: Likewise. * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI. (cpu_flags): Add CpuGFNI. * i386-opc.h (enum): Add CpuGFNI. (i386_cpu_flags): Add cpugfni. * i386-opc.tbl: Add Intel GFNI instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2017-10-23Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist1-2/+32
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .avx512_vbmi2. (cpu_noarch): noavx512_vbmi2. * doc/c-i386.texi: Document .avx512_vbmi2, noavx512_vbmi2. * testsuite/gas/i386/i386.exp: Add AVX512_VBMI2 tests. * testsuite/gas/i386/avx512vbmi2-intel.d: New test. * testsuite/gas/i386/avx512vbmi2.d: Likewise. * testsuite/gas/i386/avx512vbmi2.s: Likewise. * testsuite/gas/i386/avx512vbmi2_vl-intel.d: Likewise. * testsuite/gas/i386/avx512vbmi2_vl.d: Likewise. * testsuite/gas/i386/avx512vbmi2_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2.s: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2_vl-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2_vl.s: Likewise. opcodes/ * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode. Define EXbScalar and EXwScalar for OP_EX. (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71, PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73. (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2, EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2, EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2, EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2. (intel_operand_size): Handle b_scalar_mode and w_scalar_mode. (OP_E_memory): Likewise. * i386-dis-evex.h: Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2, CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_VBMI2. * i386-opc.h (enum): Add CpuAVX512_VBMI2. (i386_cpu_flags): Add cpuavx512_vbmi2. * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2017-09-09x86: Remove restriction on NOTRACK prefix positionH.J. Lu1-16/+2
Since the NOTRACK prefix is no longer required to be the last prefix before the REX prefix, restriction on the NOTRACK prefix position is removed from assembler as well as disassembler. Assembler encodes the NOTRACK prefix the same way as the DS segment register, which places it before other prefixes. Disassembler displays prefixes in the order they appear. gas/ * config/tc-i386.c (NOTRACK_PREFIX): Removed. (REX_PREFIX): Updated. (MAX_PREFIXES): Likewise. (parse_insn): Remove restriction on NOTRACK prefix position. * testsuite/gas/i386/notrack.s: Add tests with NOTRACK prefix before other prefixes. * testsuite/gas/i386/x86-64-notrack.s: Likewise. * testsuite/gas/i386/notrackbad.s: Remove tests with NOTRACK prefix before other prefixes. * testsuite/gas/i386/x86-64-notrackbad.s: Likewise. * testsuite/gas/i386/notrack-intel.d: Updated. * testsuite/gas/i386/notrack.d: Likewise. * testsuite/gas/i386/notrackbad.l: Likewise. * testsuite/gas/i386/x86-64-notrack-intel.d: Likewise. * testsuite/gas/i386/x86-64-notrack.d: Likewise. * testsuite/gas/i386/x86-64-notrackbad.l: Likewise. opcodes/ * i386-dis.c (last_active_prefix): Removed. (ckprefix): Don't set last_active_prefix. (NOTRACK_Fixup): Don't check last_active_prefix.
2017-07-18Fix spelling typos.Yuri Chornovian1-1/+1
2017-07-05X86: Disassemble primary opcode map's group 2 ModRM.reg == 6 aliases correctlyBorislav Petkov1-6/+6
The instructions are not documented in the Intel SDM but are documented in the AMD APM as an alias to the group 2, ModRM.reg == 4 variant. Both AMD and Intel CPUs execute the C[0-1] and D[0-3] instructions as expected, i.e., like the /4 aliases: #include <stdio.h> int main(void) { int a = 2; printf ("a before: %d\n", a); asm volatile(".byte 0xd0,0xf0" /* SHL %al */ : "+a" (a)); printf("a after : %d\n", a); return 0; } $ ./a.out a before: 2 a after : 4
2017-06-21x86: CET v2.0: Update incssp and setssbsyH.J. Lu1-11/+12
Update x86 assembler and disassembler for CET v2.0: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf 1. incsspd and incsspq are changed to take a register opeand with a different opcode. 2. setssbsy is changed to take no opeand with a different opcode. gas/ * testsuite/gas/i386/cet-intel.d: Updated. * testsuite/gas/i386/cet.d: Likewise. * testsuite/gas/i386/x86-64-cet-intel.d: Likewise. * testsuite/gas/i386/x86-64-cet.d: Likewise. * testsuite/gas/i386/cet.s: Update incsspd and setssbsy tests. * testsuite/gas/i386/x86-64-cet.s: Likewise. opcodes/ * i386-dis.c (RM_0FAE_REG_5): Removed. (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. (PREFIX_MOD_3_0F01_REG_5_RM_0): New. (PREFIX_MOD_3_0FAE_REG_5): Likewise. (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add PREFIX_MOD_3_0F01_REG_5_RM_0. (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add PREFIX_MOD_3_0FAE_REG_5. (mod_table): Update MOD_0FAE_REG_5. (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5. * i386-opc.tbl: Update incsspd, incsspq and setssbsy. * i386-tbl.h: Regenerated.
2017-06-21x86: CET v2.0: Rename savessp to saveprevsspH.J. Lu1-1/+1
Replace savessp with saveprevssp for CET v2.0: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf gas/ * testsuite/gas/i386/cet-intel.d: Updated. * testsuite/gas/i386/cet.d: Likewise. * testsuite/gas/i386/x86-64-cet-intel.d: Likewise. * testsuite/gas/i386/x86-64-cet.d: Likewise. * testsuite/gas/i386/cet.s: Replace savessp with saveprevssp. * testsuite/gas/i386/x86-64-cet.s: Likewise. opcodes/ * i386-dis.c (prefix_table): Replace savessp with saveprevssp. * i386-opc.tbl: Likewise. * i386-tbl.h: Regenerated.
2017-06-21x86: CET v2.0: Update NOTRACK prefixH.J. Lu1-8/+6
Update NOTRACK prefix handling to support memory indirect branch for CET v2.0: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf gas/ * config/tc-i386.c (md_assemble): Update NOTRACK prefix check. * testsuite/gas/i386/notrack-intel.d: Updated. * testsuite/gas/i386/notrack.d: Likewise. * testsuite/gas/i386/notrackbad.l: Likewise. * testsuite/gas/i386/x86-64-notrack-intel.d: Likewise. * testsuite/gas/i386/x86-64-notrack.d: Likewise. * testsuite/gas/i386/x86-64-notrackbad.l: Likewise. * testsuite/gas/i386/notrack.s: Add NOTRACK prefix tests with memory indirect branch. * testsuite/gas/i386/x86-64-notrack.s: Likewise. * testsuite/gas/i386/notrackbad.s: Remove memory indirect branch with NOTRACK prefix. * testsuite/gas/i386/x86-64-notrackbad.s: Likewise. opcodes/ * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}" and "jmp{&|}". (NOTRACK_Fixup): Support memory indirect branch with NOTRACK prefix.
2017-06-15i386-dis: Check valid bnd registerH.J. Lu1-0/+10
Since there are only 4 bnd registers, return "(bad)" for register number > 3. PR binutils/21594 * i386-dis.c (OP_E_register): Check valid bnd register. (OP_G): Likewise.
2017-05-24Move print_insn_XXX to an opcodes internal headerYao Qi1-1/+1
With the changes done in previous patches, print_insn_XXX functions don't have to be external visible out of opcodes, because both gdb and objdump select disassemblers through a single interface. This patch moves these print_insn_XXX declarations from include/dis-asm.h to opcodes/disassemble.h, which is a new header added by this patch. include: 2017-05-24 Yao Qi <yao.qi@linaro.org> * dis-asm.h: Move some function declarations to opcodes/disassemble.h. opcodes: 2017-05-24 Yao Qi <yao.qi@linaro.org> * alpha-dis.c: Include disassemble.h, don't include dis-asm.h. * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise. * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise. * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise. * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise. * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise. * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise. * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise. * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise. * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise. * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise. * moxie-dis.c, msp430-dis.c, mt-dis.c: * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise. * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise. * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise. * rl78-dis.c, s390-dis.c, score-dis.c: Likewise. * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise. * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise. * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise. * v850-dis.c, vax-dis.c, visium-dis.c: Likewise. * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise. * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise. * z80-dis.c, z8k-dis.c: Likewise. * disassemble.h: New file.
2017-05-22x86: Add NOTRACK prefix supportH.J. Lu1-3/+41
For register indirect branches, NOTRACK prefix (0x3e), which is also the DS segment register prefix, can be used to ignore the CET indirect branch track. gas/ * config/tc-i386.c (REX_PREFIX): Changed to 7. (NOTRACK_PREFIX): New. (MAX_PREFIXES): Changed to 8. (_i386_insn): Add notrack_prefix. (PREFIX_GROUP): Add PREFIX_DS. (add_prefix): Return PREFIX_DS for DS_PREFIX_OPCODE. (md_assemble): Check if NOTRACK prefix is supported. (parse_insn): Set notrack_prefix and issue an error for other prefixes after NOTRACK prefix. * testsuite/gas/i386/i386.exp: Run tests for NOTRACK prefix. * testsuite/gas/i386/notrack-intel.d: New file. * testsuite/gas/i386/notrack.d: Likewise. * testsuite/gas/i386/notrack.s: Likewise. * testsuite/gas/i386/notrackbad.l: Likewise. * testsuite/gas/i386/notrackbad.s: Likewise. * testsuite/gas/i386/x86-64-notrack-intel.d: Likewise. * testsuite/gas/i386/x86-64-notrack.d: Likewise. * testsuite/gas/i386/x86-64-notrack.s: Likewise. * testsuite/gas/i386/x86-64-notrackbad.l: Likewise. * testsuite/gas/i386/x86-64-notrackbad.s: Likewise. include/ * include/opcode/i386.h (NOTRACK_PREFIX_OPCODE): New. opcodes/ * i386-dis.c (NOTRACK_Fixup): New. (NOTRACK): Likewise. (NOTRACK_PREFIX): Likewise. (last_active_prefix): Likewise. (reg_table): Use NOTRACK on indirect call and jmp. (ckprefix): Set last_active_prefix. (prefix_name): Return "notrack" for NOTRACK_PREFIX. * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk. * i386-opc.h (NoTrackPrefixOk): New. (i386_opcode_modifier): Add notrackprefixok. * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp. Add notrack. * i386-tbl.h: Regenerated.
2017-03-06Add support for Intel CET instructionsH.J. Lu1-10/+95
Support Intel Control-flow Enforcement Technology (CET) instructions: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf gas/ * config/tc-i386.c (cpu_arch): Add .cet. * doc/c-i386.texi: Document cet. * testsuite/gas/i386/cet-intel.d: New file. * testsuite/gas/i386/cet.d: Likewise. * testsuite/gas/i386/cet.s: Likewise. * testsuite/gas/i386/x86-64-cet-intel.d: Likewise. * testsuite/gas/i386/x86-64-cet.d: Likewise. * testsuite/gas/i386/x86-64-cet.s: Likewise. * testsuite/gas/i386/i386.exp: Run Intel CET tests. opcodes/ * i386-dis.c (REG_0F1E_MOD_3): New enum. (MOD_0F1E_PREFIX_1): Likewise. (MOD_0F38F5_PREFIX_2): Likewise. (MOD_0F38F6_PREFIX_0): Likewise. (RM_0F1E_MOD_3_REG_7): Likewise. (PREFIX_MOD_0_0F01_REG_5): Likewise. (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise. (PREFIX_0F1E): Likewise. (PREFIX_MOD_0_0FAE_REG_5): Likewise. (PREFIX_0F38F5): Likewise. (dis386_twobyte): Use PREFIX_0F1E. (reg_table): Add REG_0F1E_MOD_3. (prefix_table): Add PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2, PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update PREFIX_0FAE_REG_6 and PREFIX_0F38F6. (three_byte_table): Use PREFIX_0F38F5. (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5. Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0. (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0, RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and PREFIX_MOD_3_0F01_REG_5_RM_2. * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS. (cpu_flags): Add CpuCET. * i386-opc.h (CpuCET): New enum. (CpuUnused): Commented out. (i386_cpu_flags): Add cpucet. * i386-opc.tbl: Add Intel CET instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2017-02-28x86: fix handling of 64-bit operand size VPCMPESTR{I,M}Jan Beulich1-14/+26
Just like REX.W affects operand size of the implicit rAX/rDX inputs to PCMPESTR{I,M}, VEX.W does for VPCMPESTR{I,M}. Allow Q or L suffixes on the instructions. Similarly the disassembler needs to be adjusted to no longer require VEX.W to be zero for the instructions to be valid, and to emit proper suffixes. Note, however, that this doesn't address the problem of there being no way to control (at least) {,E}VEX.W for 32- or 16-bit code. Nor does it address the problem of the many WIG instructions not getting properly disassembled when VEX.W=1.
2017-02-24x86: also correctly support TEST opcode aliasesJan Beulich1-2/+2
Opcodes F6/1 and F7/1 are aliases of F6/0 and F7/0 in all modes. This complements commit 8b89fe14b5 ("X86: Decode opcode 0x82 as opcode 0x80 in 32-bit mode"), just that here 64-bit mode is also covered.
2017-02-23x86: drop stray VEX opcode 82 referencesJan Beulich1-4/+4
No such ModR/M-less opcode has ever existed in public documentation afaict, so I can't see why it had been added in the first place. Furthermore opcode 77 is special only with implied prefix 0F.
2017-01-12Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist1-0/+2
gas/ 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_vpopcntdq. (cpu_noarch): Add noavx512_vpopcntdq. * doc/c-i386.texi: Document avx512_vpopcntdq, noavx512_vpopcntdq. * testsuite/gas/i386/i386.exp: Run AVX512_VPOPCNTDQ tests. * testsuite/gas/i386/avx512_vpopcntdqd-intel.d: New file. * testsuite/gas/i386/avx512_vpopcntdqd.d: Ditto. * testsuite/gas/i386/avx512_vpopcntdqd.s: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd.d: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd.s: Ditto. opcodes/ 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS, CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_VPOPCNTDQ. * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New. (i386_cpu_flags): Add cpuavx512_vpopcntdq. * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions. * i386-init.h: Regenerate. * i386-tbl.h: Ditto.
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-01Fix abort in x86 disassembler.Nick Clifton1-1/+2
PR binutils/20893 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad opcode designator.
2016-11-28X86: Ignore REX_B bit for 32-bit XOP instructionsAmit Pawar1-4/+8
While decoding 32-bit XOP instructions, 64 bit registers names are printed. This patch fixes this by ignoring REX_B bit in 32-bit mode. opcodes/ PR binutils/20637 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP instructions. gas/ PR binutils/20637 * testsuite/gas/i386/xop32reg.d: New file. * testsuite/gas/i386/xop32reg.s: New file. * testsuite/gas/i386/i386.exp: Run new test.
2016-11-09X86: Remove the .s suffix from EVEX vpextrwH.J. Lu1-9/+1
The .s suffix indicates that the instruction is encoded by swapping 2 register operands. Since vpextrw takes an XMM register and an integer register, the .s suffix should be ignored for EVEX vpextrw. gas/ PR binutils/20799 * testsuite/gas/i386/opcode.s: Add a test for EVEX vpextrw. * testsuite/gas/i386/opcode-intel.d: Updated. * testsuite/gas/i386/opcode-suffix.d: Likewise. * testsuite/gas/i386/opcode.d: Likewise. * testsuite/gas/i386/x86-64-avx512bw-opts.s: Remove vpextrw tests. * testsuite/gas/i386/x86-64-avx512bw-opts-intel.d: Updated. * testsuite/gas/i386/x86-64-avx512bw-opts.d: Likewise. opcodes/ PR binutils/20799 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw. * i386-dis.c (EdqwS): Removed. (dqw_swap_mode): Likewise. (intel_operand_size): Don't check dqw_swap_mode. (OP_E_register): Likewise. (OP_E_memory): Likewise. (OP_G): Likewise. (OP_EX): Likewise. * i386-opc.tbl: Remove "S" from EVEX vpextrw. * i386-tbl.h: Regerated.
2016-11-08X86: Remove the THREE_BYTE_0F7A entryH.J. Lu1-295/+2
Remove the THREE_BYTE_0F7A entry which is leftover from SSE5. PR binutils/20701 * i386-dis.c (THREE_BYTE_0F7A): Removed. (dis386_twobyte): Don't use THREE_BYTE_0F7A. (three_byte_table): Remove THREE_BYTE_0F7A.
2016-11-07X86: Properly handle bad FPU opcodeH.J. Lu1-18/+23
Since Bad_Opcode and FGRPd9_2 were the same in i386-dis.c, all Bad_Opcode entries in float_reg were displaced as FGRPd9_2. This patch adds an entry for Bad_Opcode in fgrps to avoid treating it as FGRPd9_2. gas/ PR binutils/20775 * testsuite/gas/i386/i386.exp: Run fpu-bad. * testsuite/gas/i386/fpu-bad.d: New file. * testsuite/gas/i386/fpu-bad.s: Likewise. opcodes/ PR binutils/20775 * i386-dis.c (FGRPd9_2): Replace 0 with 1. (FGRPd9_4): Replace 1 with 2. (FGRPd9_5): Replace 2 with 3. (FGRPd9_6): Replace 3 with 4. (FGRPd9_7): Replace 4 with 5. (FGRPda_5): Replace 5 with 6. (FGRPdb_4): Replace 6 with 7. (FGRPde_3): Replace 7 with 8. (FGRPdf_4): Replace 8 with 9. (fgrps): Add an entry for Bad_Opcode.
2016-11-03X86: Reuse opcode 0x80 decoder for opcode 0x82H.J. Lu1-58/+5
Since opcode 0x82 is an alias of opcode 0x80, we can reuse opcode 0x80 decoder. * i386-dis.c (REG_82): Removed. (X86_64_82_REG_0): Likewise. (X86_64_82_REG_1): Likewise. (X86_64_82_REG_2): Likewise. (X86_64_82_REG_3): Likewise. (X86_64_82_REG_4): Likewise. (X86_64_82_REG_5): Likewise. (X86_64_82_REG_6): Likewise. (X86_64_82_REG_7): Likewise. (X86_64_82): New. (dis386): Use X86_64_82 instead of REG_82. (reg_table): Remove REG_82. (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0, X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
2016-11-03X86: Decode opcode 0x82 as opcode 0x80 in 32-bit modeH.J. Lu1-1/+61
Update x86 disassembler to treat opcode 0x82 as an aliase of opcode 0x80 in 32-bit mode. gas/ PR binutils/20754 * testsuite/gas/i386/opcode.s: Add tests for opcode 0x82. * testsuite/gas/i386/opcode-intel.d: Updated. * testsuite/gas/i386/opcode.d: Likewise. opcodes/ PR binutils/20754 * i386-dis.c (REG_82): New. (X86_64_82_REG_0): Likewise. (X86_64_82_REG_1): Likewise. (X86_64_82_REG_2): Likewise. (X86_64_82_REG_3): Likewise. (X86_64_82_REG_4): Likewise. (X86_64_82_REG_5): Likewise. (X86_64_82_REG_6): Likewise. (X86_64_82_REG_7): Likewise. (dis386): Use REG_82. (reg_table): Add REG_82. (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
2016-11-03X86: Rename REG_82 to REG_83H.J. Lu1-3/+3
The REG_82 entry in x86 disassembler is for opcode 0x83, not opcode 0x82. * i386-dis.c (REG_82): Renamed to ... (REG_83): This. (dis386): Updated. (reg_table): Likewise.
2016-11-02Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist1-0/+2
gas/ * config/tc-i386.c: (cpu_arch) Add .avx512_4vnniw. (cpu_noarch): Add noavx512_4vnniw. * doc/c-i386.texi: Document avx512_4vnniw, noavx512_4vnniw. * testsuite/gas/i386/i386.exp: Run AVX512_4VNNIW tests. * testsuite/gas/i386/avx512_4vnniwd_vl-intel.d: New test. * testsuite/gas/i386/avx512_4vnniwd_vl.d: Ditto. * testsuite/gas/i386/avx512_4vnniwd_vl.s: Ditto. * testsuite/gas/i386/avx512_4vnniwd-intel.d: Ditto. * testsuite/gas/i386/avx512_4vnniwd.d: Ditto. * testsuite/gas/i386/avx512_4vnniwd.s: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd_vl-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.s: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd.s: Ditto. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS, CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_4VNNIW. * i386-opc.h (enum): (AVX512_4VNNIW): New. (i386_cpu_flags): Add cpuavx512_4vnniw. * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions. * i386-init.h: Regenerate. * i386-tbl.h: Ditto.
generated by cgit v1.1 at 2025-02-21 11:20:07 +0000