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2017-02-23x86: drop stray VEX opcode 82 referencesJan Beulich1-4/+4
No such ModR/M-less opcode has ever existed in public documentation afaict, so I can't see why it had been added in the first place. Furthermore opcode 77 is special only with implied prefix 0F.
2017-01-12Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist1-0/+2
gas/ 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_vpopcntdq. (cpu_noarch): Add noavx512_vpopcntdq. * doc/c-i386.texi: Document avx512_vpopcntdq, noavx512_vpopcntdq. * testsuite/gas/i386/i386.exp: Run AVX512_VPOPCNTDQ tests. * testsuite/gas/i386/avx512_vpopcntdqd-intel.d: New file. * testsuite/gas/i386/avx512_vpopcntdqd.d: Ditto. * testsuite/gas/i386/avx512_vpopcntdqd.s: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd.d: Ditto. * testsuite/gas/i386/x86-64-avx512_vpopcntdqd.s: Ditto. opcodes/ 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS, CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_VPOPCNTDQ. * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New. (i386_cpu_flags): Add cpuavx512_vpopcntdq. * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions. * i386-init.h: Regenerate. * i386-tbl.h: Ditto.
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-01Fix abort in x86 disassembler.Nick Clifton1-1/+2
PR binutils/20893 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad opcode designator.
2016-11-28X86: Ignore REX_B bit for 32-bit XOP instructionsAmit Pawar1-4/+8
While decoding 32-bit XOP instructions, 64 bit registers names are printed. This patch fixes this by ignoring REX_B bit in 32-bit mode. opcodes/ PR binutils/20637 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP instructions. gas/ PR binutils/20637 * testsuite/gas/i386/xop32reg.d: New file. * testsuite/gas/i386/xop32reg.s: New file. * testsuite/gas/i386/i386.exp: Run new test.
2016-11-09X86: Remove the .s suffix from EVEX vpextrwH.J. Lu1-9/+1
The .s suffix indicates that the instruction is encoded by swapping 2 register operands. Since vpextrw takes an XMM register and an integer register, the .s suffix should be ignored for EVEX vpextrw. gas/ PR binutils/20799 * testsuite/gas/i386/opcode.s: Add a test for EVEX vpextrw. * testsuite/gas/i386/opcode-intel.d: Updated. * testsuite/gas/i386/opcode-suffix.d: Likewise. * testsuite/gas/i386/opcode.d: Likewise. * testsuite/gas/i386/x86-64-avx512bw-opts.s: Remove vpextrw tests. * testsuite/gas/i386/x86-64-avx512bw-opts-intel.d: Updated. * testsuite/gas/i386/x86-64-avx512bw-opts.d: Likewise. opcodes/ PR binutils/20799 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw. * i386-dis.c (EdqwS): Removed. (dqw_swap_mode): Likewise. (intel_operand_size): Don't check dqw_swap_mode. (OP_E_register): Likewise. (OP_E_memory): Likewise. (OP_G): Likewise. (OP_EX): Likewise. * i386-opc.tbl: Remove "S" from EVEX vpextrw. * i386-tbl.h: Regerated.
2016-11-08X86: Remove the THREE_BYTE_0F7A entryH.J. Lu1-295/+2
Remove the THREE_BYTE_0F7A entry which is leftover from SSE5. PR binutils/20701 * i386-dis.c (THREE_BYTE_0F7A): Removed. (dis386_twobyte): Don't use THREE_BYTE_0F7A. (three_byte_table): Remove THREE_BYTE_0F7A.
2016-11-07X86: Properly handle bad FPU opcodeH.J. Lu1-18/+23
Since Bad_Opcode and FGRPd9_2 were the same in i386-dis.c, all Bad_Opcode entries in float_reg were displaced as FGRPd9_2. This patch adds an entry for Bad_Opcode in fgrps to avoid treating it as FGRPd9_2. gas/ PR binutils/20775 * testsuite/gas/i386/i386.exp: Run fpu-bad. * testsuite/gas/i386/fpu-bad.d: New file. * testsuite/gas/i386/fpu-bad.s: Likewise. opcodes/ PR binutils/20775 * i386-dis.c (FGRPd9_2): Replace 0 with 1. (FGRPd9_4): Replace 1 with 2. (FGRPd9_5): Replace 2 with 3. (FGRPd9_6): Replace 3 with 4. (FGRPd9_7): Replace 4 with 5. (FGRPda_5): Replace 5 with 6. (FGRPdb_4): Replace 6 with 7. (FGRPde_3): Replace 7 with 8. (FGRPdf_4): Replace 8 with 9. (fgrps): Add an entry for Bad_Opcode.
2016-11-03X86: Reuse opcode 0x80 decoder for opcode 0x82H.J. Lu1-58/+5
Since opcode 0x82 is an alias of opcode 0x80, we can reuse opcode 0x80 decoder. * i386-dis.c (REG_82): Removed. (X86_64_82_REG_0): Likewise. (X86_64_82_REG_1): Likewise. (X86_64_82_REG_2): Likewise. (X86_64_82_REG_3): Likewise. (X86_64_82_REG_4): Likewise. (X86_64_82_REG_5): Likewise. (X86_64_82_REG_6): Likewise. (X86_64_82_REG_7): Likewise. (X86_64_82): New. (dis386): Use X86_64_82 instead of REG_82. (reg_table): Remove REG_82. (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0, X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
2016-11-03X86: Decode opcode 0x82 as opcode 0x80 in 32-bit modeH.J. Lu1-1/+61
Update x86 disassembler to treat opcode 0x82 as an aliase of opcode 0x80 in 32-bit mode. gas/ PR binutils/20754 * testsuite/gas/i386/opcode.s: Add tests for opcode 0x82. * testsuite/gas/i386/opcode-intel.d: Updated. * testsuite/gas/i386/opcode.d: Likewise. opcodes/ PR binutils/20754 * i386-dis.c (REG_82): New. (X86_64_82_REG_0): Likewise. (X86_64_82_REG_1): Likewise. (X86_64_82_REG_2): Likewise. (X86_64_82_REG_3): Likewise. (X86_64_82_REG_4): Likewise. (X86_64_82_REG_5): Likewise. (X86_64_82_REG_6): Likewise. (X86_64_82_REG_7): Likewise. (dis386): Use REG_82. (reg_table): Add REG_82. (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
2016-11-03X86: Rename REG_82 to REG_83H.J. Lu1-3/+3
The REG_82 entry in x86 disassembler is for opcode 0x83, not opcode 0x82. * i386-dis.c (REG_82): Renamed to ... (REG_83): This. (dis386): Updated. (reg_table): Likewise.
2016-11-02Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist1-0/+2
gas/ * config/tc-i386.c: (cpu_arch) Add .avx512_4vnniw. (cpu_noarch): Add noavx512_4vnniw. * doc/c-i386.texi: Document avx512_4vnniw, noavx512_4vnniw. * testsuite/gas/i386/i386.exp: Run AVX512_4VNNIW tests. * testsuite/gas/i386/avx512_4vnniwd_vl-intel.d: New test. * testsuite/gas/i386/avx512_4vnniwd_vl.d: Ditto. * testsuite/gas/i386/avx512_4vnniwd_vl.s: Ditto. * testsuite/gas/i386/avx512_4vnniwd-intel.d: Ditto. * testsuite/gas/i386/avx512_4vnniwd.d: Ditto. * testsuite/gas/i386/avx512_4vnniwd.s: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd_vl-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.s: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd.s: Ditto. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS, CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_4VNNIW. * i386-opc.h (enum): (AVX512_4VNNIW): New. (i386_cpu_flags): Add cpuavx512_4vnniw. * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions. * i386-init.h: Regenerate. * i386-tbl.h: Ditto.
2016-10-21X86: Remove pcommit instructionH.J. Lu1-9/+2
Remove x86 pcommit instruction support, which has been deprecated: https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction gas/ * config/tc-i386.c (cpu_arch): Remove .pcommit. * doc/c-i386.texi: Likewise. * testsuite/gas/i386/i386.exp: Remove pcommit tests. * testsuite/gas/i386/pcommit-intel.d: Removed. * testsuite/gas/i386/pcommit.d: Likewise. * testsuite/gas/i386/pcommit.s: Likewise. * testsuite/gas/i386/x86-64-pcommit-intel.d: Likewise. * testsuite/gas/i386/x86-64-pcommit.d: Likewise. * testsuite/gas/i386/x86-64-pcommit.s: Likewise. opcodes/ * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed. (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry. (rm_table): Update the RM_0FAE_REG_7 entry. * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS. (cpu_flags): Remove CpuPCOMMIT. * i386-opc.h (CpuPCOMMIT): Removed. (i386_cpu_flags): Remove cpupcommit. * i386-opc.tbl: Remove pcommit. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2016-10-20Check invalid mask registersH.J. Lu1-17/+34
In 32-bit, the REX_B bit in the 3-byte VEX prefix is ignored and the the highest bit in VEX.vvvv is either 1 or ignored. In 64-bit, we need to check invalid mask registers. gas/ PR binutis/20705 * testsuite/gas/i386/i386.exp: Run x86-64-opcode-bad. * testsuite/gas/i386/x86-64-opcode-bad.d: New file. * testsuite/gas/i386/x86-64-opcode-bad.s: Likewise. opcodes/ PR binutis/20705 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and the highest bit in VEX.vvvv for the 3-byte VEX prefix in 32-bit mode. Don't check vex.register_specifier in 32-bit mode. (OP_E_register): Check invalid mask registers. (OP_G): Likewise. (OP_VEX): Likewise.
2016-10-18Check addr32flag instead of sizeflag for rip/eipH.J. Lu1-2/+2
Since the address size prefix, 0x67, is ignored for MPX instructions in 64-bit mode, we should check addr32flag instead of sizeflag for rip/eip. PR binutis/20699 * i386-dis.c (OP_E_memory): Check addr32flag instead of sizeflag for rip/eip.
2016-10-18Remove the remaining SSE5 supportH.J. Lu1-1/+1
PR binutis/20704 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
2016-10-06-Wimplicit-fallthrough warning fixesAlan Modra1-3/+7
Comment changes. bfd/ * coff-h8300.c: Spell fall through comments consistently. * coffgen.c: Likewise. * elf32-hppa.c: Likewise. * elf32-ppc.c: Likewise. * elf32-score.c: Likewise. * elf32-score7.c: Likewise. * elf64-ppc.c: Likewise. * elfxx-aarch64.c: Likewise. * elfxx-mips.c: Likewise. * cpu-ns32k.c: Add missing fall through comments. * elf-m10300.c: Likewise. * elf32-arm.c: Likewise. * elf32-avr.c: Likewise. * elf32-bfin.c: Likewise. * elf32-frv.c: Likewise. * elf32-i386.c: Likewise. * elf32-microblaze.c: Likewise. * elf32-nds32.c: Likewise. * elf32-ppc.c: Likewise. * elf32-rl78.c: Likewise. * elf32-rx.c: Likewise. * elf32-s390.c: Likewise. * elf32-sh.c: Likewise. * elf32-tic6x.c: Likewise. * elf64-ia64-vms.c: Likewise. * elf64-ppc.c: Likewise. * elf64-s390.c: Likewise. * elf64-x86-64.c: Likewise. * elflink.c: Likewise. * elfnn-aarch64.c: Likewise. * elfnn-ia64.c: Likewise. * ieee.c: Likewise. * oasys.c: Likewise. * pdp11.c: Likewise. * srec.c: Likewise. * versados.c: Likewise. opcodes/ * aarch64-opc.c: Spell fall through comments consistently. * i386-dis.c: Likewise. * aarch64-dis.c: Add missing fall through comments. * aarch64-opc.c: Likewise. * arc-dis.c: Likewise. * arm-dis.c: Likewise. * i386-dis.c: Likewise. * m68k-dis.c: Likewise. * mep-asm.c: Likewise. * ns32k-dis.c: Likewise. * sh-dis.c: Likewise. * tic4x-dis.c: Likewise. * tic6x-dis.c: Likewise. * vax-dis.c: Likewise. binutils/ * dlltool.c: Spell fall through comments consistently. * objcopy.c: Likewise. * readelf.c: Likewise. * dwarf.c: Add missing fall through comments. * elfcomm.c: Likewise. * sysinfo.y: Likewise. * readelf.c: Likewise. Also remove extraneous comments. gas/ * app.c: Add missing fall through comments. * dw2gencfi.c: Likewise. * expr.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arc.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-crx.c: Likewise. * config/tc-dlx.c: Likewise. * config/tc-h8300.c: Likewise. * config/tc-hppa.c: Likewise. * config/tc-i370.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-i960.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-m68hc11.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-metag.c: Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mips.c: Likewise. * config/tc-ns32k.c: Likewise. * config/tc-rx.c: Likewise. * config/tc-score.c: Likewise. * config/tc-score7.c: Likewise. * config/tc-sh.c: Likewise. * config/tc-tic4x.c: Likewise. * config/tc-vax.c: Likewise. * config/tc-xstormy16.c: Likewise. * config/tc-z80.c: Likewise. * config/tc-z8k.c: Likewise. * config/obj-elf.c: Likewise. * config/tc-i386.c: Likewise. * depend.c: Spell fall through comments consistently. * config/tc-arm.c: Likewise. * config/tc-d10v.c: Likewise. * config/tc-i960.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-mcore.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-ns32k.c: Likewise. * config/tc-visium.c: Likewise. * config/tc-xstormy16.c: Likewise. * config/tc-z8k.c: Likewise. gprof/ * gprof.c: Add missing fall through comments. ld/ * lexsup.c: Spell fall through comments consistently and add missing fall through comments.
2016-09-30Don't assign alt twiceH.J. Lu1-1/+0
PR binutils/20657 * i386-dis.c (putop): Don't assign alt twice.
2016-08-24X86: Add ptwrite instructionH.J. Lu1-1/+16
Implement ptwrite instruction defined in Intel64 and IA-32 Architectures Software Developer’s Manual, June 2016. gas/ * config/tc-i386.c (cpu_arch): Add .ptwrite. * doc/c-i386.texi: Document ptwrite and .ptwrite. * testsuite/gas/i386/i386.exp: Run ptwrite, ptwrite-intel, x86-64-ptwrite and x86-64-ptwrite-intel. * testsuite/gas/i386/ptwrite-intel.d: New file. * testsuite/gas/i386/ptwrite.d: Likewise. * testsuite/gas/i386/ptwrite.s: Likewise. * testsuite/gas/i386/x86-64-ptwrite-intel.d: Likewise. * testsuite/gas/i386/x86-64-ptwrite.d: Likewise. * testsuite/gas/i386/x86-64-ptwrite.s: Likewise. opcodes/ * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New. (PREFIX_MOD_3_0FAE_REG_4): Likewise. (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and PREFIX_MOD_3_0FAE_REG_4. (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and PREFIX_MOD_3_0FAE_REG_4. * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS. (cpu_flags): Add CpuPTWRITE. * i386-opc.h (CpuPTWRITE): New. (i386_cpu_flags): Add cpuptwrite. * i386-opc.tbl: Add ptwrite instruction. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2016-06-03Handle indirect branches for AMD64 and Intel64H.J. Lu1-3/+29
AMD64 spec and Intel64 spec differ in indirect branches in 64-bit mode. AMD64 supports indirect branches with 16-bit address via the data size prefix while the data size prefix is ignored by Intel64. gas/ PR binutis/18386 * testsuite/gas/i386/i386.exp: Run x86-64-branch-4. * testsuite/gas/i386/x86-64-branch.d: Updated. * testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise. * testsuite/gas/i386/x86-64-branch-4.l: New file. * testsuite/gas/i386/x86-64-branch-4.s: Likewise. opcodes/ PR binutis/18386 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode. (indir_v_mode): New. Add comments for '&'. (reg_table): Replace "{T|}" with "{&|}" on call and jmp. (putop): Handle '&'. (intel_operand_size): Handle indir_v_mode. (OP_E_register): Likewise. * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add 64-bit indirect call/jmp for AMD64. * i386-tbl.h: Regenerated
2016-05-10Enable Intel RDPID instruction.Alexander Fomin1-1/+1
This patch enables Intel RDPID instruction described in Intel64 and IA-32 Architectures Software Developer's Manual, April 2016. gas/ * config/tc-i386.c (cpu_arch): Add RDPID. * doc/c-i386.texi: Document RDPID. gas/testsuite/ * gas/i386/i386.exp: Run RDPID tests. * gas/i386/prefix.d: Adjust. * gas/i386/rdpid.s: New test. * gas/i386/rdpid.d: Ditto. * gas/i386/rdpid-intel.d: Ditto. * gas/i386/x86-64-rdpid.s: Ditto. * gas/i386/x86-64-rdpid.d: Ditto. * gas/i386/x86-64-rdpid-intel.d: Ditto. opcodes/ * i386-dis.c (prefix_table): Add RDPID instruction. * i386-gen.c (cpu_flag_init): Add RDPID flag. (cpu_flags): Add RDPID bitfield. * i386-opc.h (enum): Add RDPID element. (i386_cpu_flags): Add RDPID field. * i386-opc.tbl: Add RDPID instruction. * i386-init.h: Regenerate. * i386-tbl.h: Regenerate.
2016-04-23Skip if size of bfd_vma is smaller than address sizeH.J. Lu1-0/+7
Disassembler won't work properly when size of bfd_vma is smaller than address size. PR binutils/19983 PR binutils/19984 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is smaller than address size.
2016-02-15Add parentheses to prevent truncated addressesH.J. Lu1-2/+2
* i386-dis.c (print_insn): Parenthesize expression to prevent truncated addresses. (OP_J): Likewise.
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-12-09Implement Intel OSPKE instructionsH.J. Lu1-1/+19
This patch implements Intel OSPKE instructions documented in Intel64 and IA-32 Architectures Software Developer’s Manual Volume 2, September 2015. gas/testsuite/ * gas/i386/i386.exp: Run ospke and x86-64-ospke. * gas/i386/ospke.d: New file. * gas/i386/ospke.s: Likewise. * gas/i386/x86-64-ospke.d: Likewise. opcodes/ * i386-dis.c (MOD_0F01_REG_5): New. (RM_0F01_REG_5): Likewise. (reg_table): Use MOD_0F01_REG_5. (mod_table): Add MOD_0F01_REG_5. (rm_table): Add RM_0F01_REG_5. * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS. (cpu_flags): Add CpuOSPKE. * i386-opc.h (CpuOSPKE): New. (i386_cpu_flags): Add cpuospke. * i386-opc.tbl: Add rdpkru and wrpkru instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2015-08-24Fix the partial disassembly of a broken three byte instruction at the end of ↵Jan Stancek1-2/+4
a function. opcodes * i386-dis.c (print_insn): Fix decoding of three byte operands. tests * gas/i386/intel.s: Add test of disassembly of a potential three byte instuction at the end of a function. * gas/i386/intel.d: Update expected disassembly.
2015-08-21PR binutils/18257: Properly decode x86/Intel mask instructions.Alexander Fomin1-59/+413
opcodes/ PR binutils/18257 * i386-dis.c: Use MOD_TABLE for most of mask instructions. (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1, MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1, MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1, MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1, MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1, MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1, MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1, MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1, MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1, MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1, MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1, MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1, MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1, MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1, MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1, MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1, MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0, MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0, MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0, MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0, MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0, MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0, MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0, MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0, MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0. (vex_w_table): Replace terminals with MOD_TABLE entries for most of mask instructions. gas/testsuite PR binutils/18257 * gas/i386/disassem.s: Add mask instructions with invalid ModR/M byte. * gas/i386/x86-64-disassem.s: Likewise. * gas/i386/disassem.d: Updated. * gas/i386/x86-64-disassem.d: Likewise.
2015-07-30Properly disassemble movnti in Intel modeH.J. Lu1-5/+10
gas/testsuite/ PR binutils/13571 * gas/i386/i386.exp: Run i386-intel and x86_64-intel. * gas/i386/i386-intel.d: New file. * gas/i386/x86_64-intel.d: Likewise. opcodes/ PR binutils/13571 * i386-dis.c (MOD_0FC3): New. (PREFIX_0FC3): Renamed to ... (PREFIX_MOD_0_0FC3): This. (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3. (prefix_table): Replace Ma with Ev on movntiS. (mod_table): Add MOD_0FC3.
2015-07-23Fix ubsan signed integer overflowAlan Modra1-2/+2
IMO a fairly useless warning in this case, but technically correct. PR 18708 * i386-dis.c (get64): Avoid signed integer overflow.
2015-06-30Add support for monitorx/mwaitx instructionsAmit Pawar1-2/+22
gas/ * config/tc-i386.c (cpu_arch): Add .mwaitx. (process_immext): Check operands for monitorx/mwaitx instructions. * doc/c-i386.texi: Document mwaitx. gas/testsuite/ * gas/i386/i386.exp: Add new mwaitx test cases. * gas/i386/mwaitx.s: New. * gas/i386/mwaitx-bdver4.d: New. * gas/i386/x86-64-mwaitx.s: New. * gas/i386/x86-64-mwaitx-bdver4.d: New. * gas/i386/mwaitx-reg.s: New. * gas/i386/mwaitx-reg.l: New. * gas/i386/x86-64-mwaitx-reg.l: New. * gas/i386/x86-64-mwaitx-reg.s: New. * gas/i386/arch-13.s: Updated. * gas/i386/arch-13.d: Updated. * gas/i386/arch-13-znver1.d: Updated. * gas/i386/x86-64-arch-3.s: Updated. * gas/i386/x86-64-arch-3.d: Updated. * gas/i386/x86-64-arch-3-znver1.d: Updated. opcodes/ * i386-dis.c (OP_Mwaitx): New. (rm_table): Add monitorx/mwaitx. * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS. (operand_type_init): Add CpuMWAITX. * i386-opc.h (CpuMWAITX): New. (i386_cpu_flags): Add cpumwaitx. * i386-opc.tbl: Add monitorx and mwaitx. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2015-06-01x86/Intel: disassemble vcvt{,u}si2s{d,s} with correct operand orderJan Beulich1-0/+7
As pointed out before, the documentation mandates the rounding mode to follow the GPR, so disassembler should produce output accordingly. gas/testsuite/ 2015-06-01 Jan Beulich <jbeulich@suse.com> * gas/i386/avx512f.s: Adjust operand order for Intel syntax vcvt{,u}si2ss. * gas/i386/x86-64-avx512f.s: Adjust operand order for Intel syntax vcvt{,u}si2s{d,s}. opcodes/ 2015-06-01 Jan Beulich <jbeulich@suse.com> * i386-dis.c (print_insn): Swap rounding mode specifier and general purpose register in Intel mode.
2015-05-15Support AMD64/Intel ISAs in assembler/disassemblerH.J. Lu1-5/+40
AMD64 spec and Intel64 spec differ in direct unconditional branches in 64-bit mode. AMD64 supports direct unconditional branches with 16-bit offset via the data size prefix, which truncates RIP to 16 bits, while the data size prefix is ignored by Intel64. This patch adds -mamd64/-mintel64 option to x86-64 assembler and -Mamd64/-Mintel64 option to x86-64 disassembler. The most permissive ISA, which is AMD64, is the default. GDB can add an option, similar to (gdb) help set disassembly-flavor Set the disassembly flavor. The valid values are "att" and "intel", and the default value is "att". to select which ISA to disassemble. binutils/ PR binutis/18386 * doc/binutils.texi: Document -Mamd64 and -Mintel64. gas/ PR binutis/18386 * config/tc-i386.c (OPTION_MAMD64): New. (OPTION_MINTEL64): Likewise. (md_longopts): Add -mamd64 and -mintel64. (md_parse_option): Handle OPTION_MAMD64 and OPTION_MINTEL64. (md_show_usage): Add -mamd64 and -mintel64. * doc/c-i386.texi: Document -mamd64 and -mintel64. gas/testsuite/ PR binutis/18386 * gas/i386/i386.exp: Run x86-64-branch-2 and x86-64-branch-3. * gas/i386/x86-64-branch.d: Also pass -Mintel64 to objdump. * gas/i386/ilp32/x86-64-branch.d: Likewise. * gas/i386/x86-64-branch-2.d: New file. * gas/i386/x86-64-branch-2.s: Likewise. * gas/i386/x86-64-branch-3.l: Likewise. * gas/i386/x86-64-branch-3.s: Likewise. ld/testsuite/ PR binutis/18386 * ld-x86-64/tlsgdesc.dd: Also pass -Mintel64 to objdump. * ld-x86-64/tlspic.dd: Likewise. * ld-x86-64/x86-64.exp (x86_64tests): Also pass -Mintel64 to objdump for tlspic.dd and tlsgdesc.dd. opcodes/ PR binutis/18386 * i386-dis.c: Add comments for '@'. (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9. (enum x86_64_isa): New. (isa64): Likewise. (print_i386_disassembler_options): Add amd64 and intel64. (print_insn): Handle amd64 and intel64. (putop): Handle '@'. (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit. * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64. * i386-opc.h (AMD64): New. (CpuIntel64): Likewise. (i386_cpu_flags): Add cpuamd64 and cpuintel64. * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64. Mark direct call/jmp without Disp16|Disp32 as Intel64. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2015-05-09Ignore 0x66 prefix for call/jmp/jcc in 64-bit modeH.J. Lu1-10/+40
The operand size prefix (0x66) is ignored for 32-bit PC-relative call, jmp and jcc in 64-bit mode. gas/testsuite/ PR binutis/18386 * gas/i386/i386.exp: Run x86-64-jump. * gas/i386/x86-64-branch.d: Updated. * gas/i386/ilp32/x86-64-branch.d: Likewise. * gas/i386/x86-64-branch.s: Add tests for the operand size prefix with call, jmp and jb. * gas/i386/x86-64-jump.d: New file. * gas/i386/x86-64-jump.s: Likewise. ld/testsuite/ PR binutis/18386 * ld-x86-64/tlsgdesc.dd: Updated. * ld-x86-64/tlspic.dd: Likewise. opcodes/ PR binutis/18386 * i386-dis.c (X86_64_E8): New. (X86_64_E9): Likewise. Update comments on 'T', 'U', 'V'. Add comments for '^'. (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9. (x86_64_table): Add X86_64_E8 and X86_64_E9. (mod_table): Replace {T|} with ^ on Jcall/Jmp. (putop): Handle '^'. (OP_J): Ignore the operand size prefix in 64-bit. Don't check REX_W.
2015-04-23x86: disambiguate disassembly of certain AVX512 insnsJan Beulich1-4/+36
Certain conversion operations as well as vfpclassp{d,s} are ambiguous when the input operand is in memory and no broadcast is being used. While in Intel mode this gets resolved by printing suitable operand size modifiers, AT&T mode need mnemonic suffixes to be added. gas/testsuite/ 2015-04-23 Jan Beulich <jbeulich@suse.com> * gas/i386/avx512dq.d: Add 'z' suffix to vfpclassp{d,s} non- register, non-broadcast cases. * gas/i386/x86-64-avx512dq.d: Likewise. * gas/i386/avx512dq_vl.d: Add 'x' and 'y' suffixes to vcvt{,u}qq2ps and vfpclassp{d,s} non-register, non-broadcast cases. * gas/i386/x86-64-avx512dq_vl.d: Likewise. * gas/i386/avx512f_vl.d: Add 'x' and 'y' suffixes to vcvt{,t}pd2{,u}dq and vcvtpd2ps non-register, non-broadcast cases. * gas/i386/x86-64-avx512f_vl.d: Likewise. opcodes/ 2015-04-23 Jan Beulich <jbeulich@suse.com> * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ". * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq, vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY. (vfpclasspd, vfpclassps): Add %XZ.
2015-04-15Remove the unused PREFIX_UD_XXXH.J. Lu1-6/+0
Remove the unused PREFIX_UD_XXX. Invalid opcodes should be handled by prefix_table. * i386-dis.c (PREFIX_UD_SHIFT): Removed. (PREFIX_UD_REPZ): Likewise. (PREFIX_UD_REPNZ): Likewise. (PREFIX_UD_DATA): Likewise. (PREFIX_UD_ADDR): Likewise. (PREFIX_UD_LOCK): Likewise.
2015-04-15Check dp->prefix_requirement insteadH.J. Lu1-5/+1
This patch removes prefix_requirement and checks dp->prefix_requirement instead. * i386-dis.c (prefix_requirement): Removed. (print_insn): Don't set prefix_requirement. Check dp->prefix_requirement instead of prefix_requirement.
2015-04-15Handle invalid prefixes for rdrand and rdseedH.J. Lu1-5/+21
This patch puts rdrand and rdseed in prefix_table so that invalid prefixes for rdrand and rdseed are handled properly. gas/testsuite/ PR binutils/17898 * gas/i386/prefix.s: Add rdrand/rdseed prefix tests. * gas/i386/prefix.d: Updated. opcodes/ PR binutils/17898 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ... (PREFIX_MOD_0_0FC7_REG_6): This. (PREFIX_MOD_3_0FC7_REG_6): New. (PREFIX_MOD_3_0FC7_REG_7): Likewise. (prefix_table): Replace PREFIX_0FC7_REG_6 with PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and PREFIX_MOD_3_0FC7_REG_7. (mod_table): Replace PREFIX_0FC7_REG_6 with PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and PREFIX_MOD_3_0FC7_REG_7.
2015-04-15Replace mandatory_prefix with prefix_requirementH.J. Lu1-310/+315
* i386-dis.c (PREFIX_MANDATORY_REPZ): Removed. (PREFIX_MANDATORY_REPNZ): Likewise. (PREFIX_MANDATORY_DATA): Likewise. (PREFIX_MANDATORY_ADDR): Likewise. (PREFIX_MANDATORY_LOCK): Likewise. (PREFIX_MANDATORY): Likewise. (PREFIX_UD_SHIFT): Set to 8 (PREFIX_UD_REPZ): Updated. (PREFIX_UD_REPNZ): Likewise. (PREFIX_UD_DATA): Likewise. (PREFIX_UD_ADDR): Likewise. (PREFIX_UD_LOCK): Likewise. (PREFIX_IGNORED_SHIFT): New. (PREFIX_IGNORED_REPZ): Likewise. (PREFIX_IGNORED_REPNZ): Likewise. (PREFIX_IGNORED_DATA): Likewise. (PREFIX_IGNORED_ADDR): Likewise. (PREFIX_IGNORED_LOCK): Likewise. (PREFIX_OPCODE): Likewise. (PREFIX_IGNORED): Likewise. (Bad_Opcode): Replace PREFIX_MANDATORY with 0. (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE. (three_byte_table): Likewise. (mod_table): Likewise. (mandatory_prefix): Renamed to ... (prefix_requirement): This. (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE. Update PREFIX_90 entry. (get_valid_dis386): Check prefix_requirement to see if a prefix should be ignored. (print_insn): Replace mandatory_prefix with prefix_requirement.
2015-04-06x86: Use individual prefix control for each opcode.Ilya Tocar1-1442/+1440
2015-04-06 Ilya Tocar <ilya.tocar@intel.com> H.J. Lu <hongjiu.lu@intel.com> * i386-dis-evex.h (evex_table): Fill prefix_requirement field. * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ, PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK, PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA, PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_OPTIONAL, PREFIX_MANDATORY): Define. (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX): Fill prefix_requirement field. (struct dis386): Add prefix_requirement field. (dis386): Fill prefix_requirement field. (dis386_twobyte): Ditto. (twobyte_has_mandatory_prefix_: Remove. (reg_table): Fill prefix_requirement field. (prefix_table): Ditto. (x86_64_table): Ditto. (three_byte_table): Ditto. (xop_table): Ditto. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (bad_opcode): Ditto. (print_insn): Use prefix_requirement. (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4, FGRPde_3, FGRPdf_4): Fill prefix_requirement field. (float_reg): Ditto.
2015-03-17Add znver1 processorGanesh Gopalasubramanian1-0/+3
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-11-17Add AVX512VBMI instructionsIlya Tocar1-0/+2
gas/ * config/tc-i386.c (cpu_arch): Add .avx512vbmi. * doc/c-i386.texi: Document it. opcodes/ * i386-dis-evex.c (evex_table): Add vpermi2b, vpermt2b, vpermb, vpmultishiftqb. * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F3883, EVEX_W_0F3883_P_2. * i386-gen.c (cpu_flag_init): Add CPU_AVX512VBMI_FLAGS. (cpu_flags): Add CpuAVX512VBMI. * i386-opc.h (enum): Add CpuAVX512VBMI. (i386_cpu_flags): Add cpuavx512vbmi. * i386-opc.tbl: Add vpmadd52luq, vpmultishiftqb, vpermb, vpermi2b, vpermt2b. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. /gas/testsuite/ * gas/i386/i386.exp: Run new tests. * gas/i386/avx512vbmi-intel.d: New file. * gas/i386/avx512vbmi.d: Likewise. * gas/i386/avx512vbmi.s: Likewise. * gas/i386/avx512vbmi_vl-intel.d: Likewise. * gas/i386/avx512vbmi_vl.d: Likewise. * gas/i386/avx512vbmi_vl.s: Likewise. * gas/i386/x86-64-avx512vbmi-intel.d: Likewise. * gas/i386/x86-64-avx512vbmi.d: Likewise. * gas/i386/x86-64-avx512vbmi.s: Likewise. * gas/i386/x86-64-avx512vbmi_vl-intel.d: Likewise. * gas/i386/x86-64-avx512vbmi_vl.d: Likewise. * gas/i386/x86-64-avx512vbmi_vl.s: Likewise.
2014-11-17Add AVX512IFMA instructionsIlya Tocar1-0/+2
gas/ * config/tc-i386.c (cpu_arch): Add .avx512ifma. * doc/c-i386.texi: Document it. opcodes/ * i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq. * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F38B4, PREFIX_EVEX_0F38B5. * i386-gen.c (cpu_flag_init): Add CPU_AVX512IFMA_FLAGS. (cpu_flags): Add CpuAVX512IFMA. * i386-opc.h (enum): Add CpuAVX512IFMA. (i386_cpu_flags): Add cpuavx512ifma. * i386-opc.tbl: Add vpmadd52huq, vpmadd52luq. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. /gas/testsuite/ * gas/i386/i386.exp: Run new tests. * gas/i386/avx512ifma-intel.d: New file. * gas/i386/avx512ifma.d: Likewise. * gas/i386/avx512ifma.s: Likewise. * gas/i386/avx512ifma_vl-intel.d: Likewise. * gas/i386/avx512ifma_vl.d: Likewise. * gas/i386/avx512ifma_vl.s: Likewise. * gas/i386/x86-64-avx512ifma-intel.d: Likewise. * gas/i386/x86-64-avx512ifma.d: Likewise. * gas/i386/x86-64-avx512ifma.s: Likewise. * gas/i386/x86-64-avx512ifma_vl-intel.d: Likewise. * gas/i386/x86-64-avx512ifma_vl.d: Likewise. * gas/i386/x86-64-avx512ifma_vl.s: Likewise.
2014-11-17Add pcommit instructionIlya Tocar1-1/+9
gas/ * config/tc-i386.c (cpu_arch): Add .pcommit. * doc/c-i386.texi: Document it. /opcodes * i386-dis.c (PREFIX enum): Add PREFIX_RM_0_0FAE_REG_7. (prefix_table): Add pcommit. * i386-gen.c (cpu_flag_init): Add CPU_PCOMMIT_FLAGS. (cpu_flags): Add CpuPCOMMIT. * i386-opc.h (enum): Add CpuPCOMMIT. (i386_cpu_flags): Add cpupcommit. * i386-opc.tbl: Add pcommit. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. /gas/testsuite/ * gas/i386/i386.exp: Run new tests. * gas/i386/pcommit-intel.d: New file. * gas/i386/pcommit.d: Likewise. * gas/i386/pcommit.s: Likewise. * gas/i386/x86-64-pcommit-intel.d: Likewise. * gas/i386/x86-64-pcommit.d: Likewise. * gas/i386/x86-64-pcommit.s: Likewise.
2014-11-17Add clwb instructionIlya Tocar1-1/+9
gas/ * config/tc-i386.c (cpu_arch): Add .clwb. * doc/c-i386.texi: Document it. opcodes/ * i386-dis.c (PREFIX enum): Add PREFIX_0FAE_REG_6. (prefix_table): Add clwb. * i386-gen.c (cpu_flag_init): Add CPU_CLWB_FLAGS. (cpu_flags): Add CpuCLWB. * i386-opc.h (enum): Add CpuCLWB. (i386_cpu_flags): Add cpuclwb. * i386-opc.tbl: Add clwb. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. gas/testsuite/ * gas/i386/i386.exp: Run new tests. * gas/i386/clwb-intel.d: New file. * gas/i386/clwb.d: Likewise. * gas/i386/clwb.s: Likewise. * gas/i386/x86-64-clwb-intel.d: Likewise. * gas/i386/x86-64-clwb.d: Likewise. * gas/i386/x86-64-clwb.s: Likewise.
2014-09-22Ignore MOD field for control/debug register moveH.J. Lu1-32/+8
This patch ignores the MOD field in control/debug register move instructions. gas/testsuite/ * gas/i386/cdr.d: New file. * gas/i386/cdr.s: Likewise. * gas/i386/x86-64-cdr.d: Likewise. * gas/i386/i386.exp: Run cdr and x86-64-cdr. opcodes/ * i386-dis.c (MOD_0F20): Removed. (MOD_0F21): Likewise. (MOD_0F22): Likewise. (MOD_0F23): Likewise. (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23 with "movZ". (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23. (OP_R): Check mod/rm byte and call OP_E_register.
2014-09-10Properly handle suffix for iret and sysretH.J. Lu1-21/+54
gas/testsuite/ * gas/i386/i386.exp: Run suffix-intel, x86-64-suffix and x86-64-suffix-intel. * gas/i386/suffix.s: Add tests for iret and sysret. * gas/i386/suffix.d: Updated. * gas/i386/suffix-intel.d: New file. * gas/i386/x86-64-suffix-intel.d: Likewise. * gas/i386/x86-64-suffix.d: Likewise. * gas/i386/x86-64-suffix.s: Likewise. opcodes/ * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret. (putop): Handle "%LP".
2014-07-22Add AVX512DQ instructions and their AVX512VL variants.Ilya Tocar1-21/+81
gas/ * config/tc-i386.c (cpu_arch): Add .avx512dq, CPU_AVX512DQ_FLAGS. * doc/c-i386.texi: Document avx512dq/.avx512dq. gas/testsuite/ * gas/i386/avx512dq-intel.d: New. * gas/i386/avx512dq.d: New. * gas/i386/avx512dq.s: New. * gas/i386/avx512dq_vl-intel.d: New. * gas/i386/avx512dq_vl.d: New. * gas/i386/avx512dq_vl.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. * gas/i386/x86-64-avx512dq-intel.d: New. * gas/i386/x86-64-avx512dq.d: New. * gas/i386/x86-64-avx512dq.s: New. * gas/i386/x86-64-avx512dq_vl-intel.d: New. * gas/i386/x86-64-avx512dq_vl.d: New. * gas/i386/x86-64-avx512dq_vl.s: New. opcodes/ * i386-dis-evex.h: Updated. * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67. (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2, VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2, EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1, EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2. (prefix_table): Add entries for new instructions. (vex_len_table): Ditto. (vex_w_table): Ditto. (OP_E_memory): Update xmmq_mode handling. * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS. (cpu_flags): Add CpuAVX512DQ. * i386-init.h: Regenerared. * i386-opc.h (CpuAVX512DQ): New. (i386_cpu_flags): Add cpuavx512dq. * i386-opc.tbl: Add AVX512DQ instructions. * i386-tbl.h: Regenerate.
2014-07-22Add support for AVX512BW instructions and their AVX512VL versions.Ilya Tocar1-17/+437
gas/ * config/tc-i386.c (cpu_arch): Add .avx512bw, CPU_AVX512BW_FLAGS. * doc/c-i386.texi: Document avx512bw/.avx512bw. gas/testsuite/ * gas/i386/avx512bw-intel.d: New. * gas/i386/avx512bw-opts-intel.d: New. * gas/i386/avx512bw-opts.d: New. * gas/i386/avx512bw-opts.s: New. * gas/i386/avx512bw-wig.s: New. * gas/i386/avx512bw-wig1-intel.d: New. * gas/i386/avx512bw-wig1.d: New. * gas/i386/avx512bw.d: New. * gas/i386/avx512bw.s: New. * gas/i386/avx512bw_vl-intel.d: New. * gas/i386/avx512bw_vl-opts-intel.d: New. * gas/i386/avx512bw_vl-opts.d: New. * gas/i386/avx512bw_vl-opts.s: New. * gas/i386/avx512bw_vl-wig.s: New. * gas/i386/avx512bw_vl-wig1-intel.d: New. * gas/i386/avx512bw_vl-wig1.d: New. * gas/i386/avx512bw_vl.d: New. * gas/i386/avx512bw_vl.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. * gas/i386/x86-64-avx512bw-intel.d: New. * gas/i386/x86-64-avx512bw-opts-intel.d: New. * gas/i386/x86-64-avx512bw-opts.d: New. * gas/i386/x86-64-avx512bw-opts.s: New. * gas/i386/x86-64-avx512bw-wig.s: New. * gas/i386/x86-64-avx512bw-wig1-intel.d: New. * gas/i386/x86-64-avx512bw-wig1.d: New. * gas/i386/x86-64-avx512bw.d: New. * gas/i386/x86-64-avx512bw.s: New. * gas/i386/x86-64-avx512bw_vl-intel.d: New. * gas/i386/x86-64-avx512bw_vl-opts-intel.d: New. * gas/i386/x86-64-avx512bw_vl-opts.d: New. * gas/i386/x86-64-avx512bw_vl-opts.s: New. * gas/i386/x86-64-avx512bw_vl-wig.s: New. * gas/i386/x86-64-avx512bw_vl-wig1-intel.d: New. * gas/i386/x86-64-avx512bw_vl-wig1.d: New. * gas/i386/x86-64-avx512bw_vl.d: New. * gas/i386/x86-64-avx512bw_vl.s: New. opcodes/ * i386-dis-evex.h: Add new instructions (prefixes bellow). * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE. (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71. (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63, PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68, PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE, PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1, PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D, PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830, PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A, PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42. (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0, VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1, VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0, VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0, VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3, EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2, EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2, EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2. (prefix_table): Add entries for new instructions. (vex_table) : Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling. (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode handling. (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode handling. (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling. (OP_EX): Add dqw_swap_mode handling. (OP_VEX): Add mask_bd_mode handling. (OP_Mask): Add mask_bd_mode handling. * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512BW. * i386-init.h: Regenerated. * i386-opc.h (CpuAVX512BW): New. (i386_cpu_flags): Add cpuavx512bw. * i386-opc.tbl: Add AVX512BW instructions. * i386-tbl.h: Regenerate.
2014-07-22Add support for AVX512VL. Add AVX512VL versions of AVX512F instructions.Ilya Tocar1-7/+63
gas/ * config/tc-i386.c (cpu_arch): Add .avx512vl, CPU_AVX512VL_FLAGS. (build_vex_prefix): Don't abort on VEX.W. (check_VecOperands): Support BROADCAST_1TO4 and BROADCAST_1TO2. (check_VecOperations): Ditto. * doc/c-i386.texi: Document avx512vl/.avx512vl. gas/testsuite/ * gas/i386/avx512f_vl-intel.d: New. * gas/i386/avx512f_vl-opts-intel.d: New. * gas/i386/avx512f_vl-opts.d: New. * gas/i386/avx512f_vl-opts.s: New. * gas/i386/avx512f_vl-wig.s: New. * gas/i386/avx512f_vl-wig1-intel.d: New. * gas/i386/avx512f_vl-wig1.d: New. * gas/i386/avx512f_vl.d: New. * gas/i386/avx512f_vl.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. * gas/i386/x86-64-avx512f_vl-intel.d: New. * gas/i386/x86-64-avx512f_vl-opts-intel.d: New. * gas/i386/x86-64-avx512f_vl-opts.d: New. * gas/i386/x86-64-avx512f_vl-opts.s: New. * gas/i386/x86-64-avx512f_vl-wig.s: New. * gas/i386/x86-64-avx512f_vl-wig1-intel.d: New. * gas/i386/x86-64-avx512f_vl-wig1.d: New. * gas/i386/x86-64-avx512f_vl.d: New. * gas/i386/x86-64-avx512f_vl.s: New. opcodes/ * i386-dis.c (intel_operand_size): Support 128/256 length in vex_vsib_q_w_dq_mode. (OP_E_memory): Add ymmq_mode handling, handle new broadcast. * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS. (cpu_flags): Add CpuAVX512VL. * i386-init.h: Regenerated. * i386-opc.h (CpuAVX512VL): New. (i386_cpu_flags): Add cpuavx512vl. (BROADCAST_1TO4, BROADCAST_1TO2): Define. * i386-opc.tbl: Add AVX512VL instructions. * i386-tbl.h: Regenerate.
generated by cgit v1.1 at 2024-11-20 04:23:33 +0000