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path: root/opcodes/i386-dis.c
AgeCommit message (Expand)AuthorFilesLines
2018-11-06x86: correctly handle KMOVD with VEX.W set outside of 64-bit modeJan Beulich1-32/+8
2018-11-06x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*Jan Beulich1-32/+12
2018-10-05x86: Add Intel ENCLV to assembler and disassemblerH.J. Lu1-1/+1
2018-09-17x86: Set EVex=2 on EVEX.128 only vmovd and vmovqH.J. Lu1-1/+40
2018-09-17x86: Set Vex=1 on VEX.128 only vmovd and vmovqH.J. Lu1-2/+0
2018-09-17x86: Update disassembler for VexWIGH.J. Lu1-1563/+232
2018-09-15x86: Set Vex=1 on VEX.128 only vmovqH.J. Lu1-2/+0
2018-09-14x86: Handle unsupported static rounding in vcvt[u]si2sd in 32-bit modeH.J. Lu1-0/+11
2018-09-14x86: Properly decode EVEX.W in vcvt[u]si2s[sd] in 32-bit modeH.J. Lu1-0/+8
2018-09-14i386: Reformat OP_E_memoryH.J. Lu1-2/+2
2018-09-13x86-64: bndmk, bndldx, and bndstx don't allow RIP-relative addressingJan Beulich1-3/+14
2018-08-14x86-64: Display eiz for address with the addr32 prefixH.J. Lu1-7/+23
2018-05-07Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu1-2/+46
2018-04-27Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist1-50/+4
2018-04-26Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist1-4/+50
2018-04-17Enable Intel CLDEMOTE instruction.Igor Tsimbalist1-1/+28
2018-04-15x86: Allow 32-bit registers for tpause and umwaitH.J. Lu1-2/+2
2018-04-11Enable Intel WAITPKG instructions.Igor Tsimbalist1-4/+31
2018-04-04i386: Clear vex instead of vex.evexH.J. Lu1-6/+1
2018-03-28x86: don't show suffixes for to-scalar-int conversion insnsJan Beulich1-24/+14
2018-03-22x86: fix swapped operand handling for BNDMOVJan Beulich1-3/+11
2018-03-08x86/Intel: correct disassembly of fsub*/fdiv*Jan Beulich1-8/+8
2018-01-23Enable Intel PCONFIG instruction.Igor Tsimbalist1-0/+1
2018-01-23Enable Intel WBNOINVD instruction.Igor Tsimbalist1-1/+8
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-11-24x86: don't omit disambiguating suffixes from "fi*"Jan Beulich1-12/+12
2017-11-23x86: fix AVX-512 16-bit addressingJan Beulich1-0/+2
2017-11-23x86: correct UDnJan Beulich1-4/+4
2017-11-16x86: ignore high register select bit(s) in 32- and 16-bit modesJan Beulich1-28/+36
2017-11-15x86: use correct register namesJan Beulich1-3/+3
2017-11-15x86: drop VEXI4_Fixup()Jan Beulich1-50/+37
2017-11-14x86: add disassembler support for XOP VPCOM* pseudo-opsJan Beulich1-8/+62
2017-10-23Enable Intel AVX512_BITALG instructions.Igor Tsimbalist1-0/+3
2017-10-23Enable Intel AVX512_VNNI instructions.Igor Tsimbalist1-0/+2
2017-10-23Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist1-12/+2
2017-10-23Enable Intel VAES instructions.Igor Tsimbalist1-48/+8
2017-10-23Enable Intel GFNI instructions.Igor Tsimbalist1-8/+78
2017-10-23Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist1-2/+32
2017-09-09x86: Remove restriction on NOTRACK prefix positionH.J. Lu1-16/+2
2017-07-18Fix spelling typos.Yuri Chornovian1-1/+1
2017-07-05X86: Disassemble primary opcode map's group 2 ModRM.reg == 6 aliases correctlyBorislav Petkov1-6/+6
2017-06-21x86: CET v2.0: Update incssp and setssbsyH.J. Lu1-11/+12
2017-06-21x86: CET v2.0: Rename savessp to saveprevsspH.J. Lu1-1/+1
2017-06-21x86: CET v2.0: Update NOTRACK prefixH.J. Lu1-8/+6
2017-06-15i386-dis: Check valid bnd registerH.J. Lu1-0/+10
2017-05-24Move print_insn_XXX to an opcodes internal headerYao Qi1-1/+1
2017-05-22x86: Add NOTRACK prefix supportH.J. Lu1-3/+41
2017-03-06Add support for Intel CET instructionsH.J. Lu1-10/+95
2017-02-28x86: fix handling of 64-bit operand size VPCMPESTR{I,M}Jan Beulich1-14/+26
2017-02-24x86: also correctly support TEST opcode aliasesJan Beulich1-2/+2
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