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2021-03-31Use bool in opcodesAlan Modra1-4/+4
cpu/ * frv.opc: Replace bfd_boolean with bool, FALSE with false, and TRUE with true throughout. opcodes/ * sysdep.h (POISON_BFD_BOOLEAN): Define. * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h, * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h, * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c, * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c, * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c, * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c, * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c, * microblaze-dis.h, * micromips-opc.c, * mips-dis.c, * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c, * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c, * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c, * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c, * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false, and TRUE with true throughout.
2021-03-25x86: flag bad S/G insn operand combinationsJan Beulich1-14/+70
For VEX-encoded ones, all three involved vector registers have to be distinct. For EVEX-encoded ones an actual mask register has to be in use and zeroing-masking cannot be used (violation of either will #UD). Additionally both involved vector registers have to be distinct for EVEX-encoded gathers.
2021-03-25x86: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clearJan Beulich1-0/+7
This combination makes no sense and is documented to cause #UD.
2021-03-22Add startswith function and use it instead of CONST_STRNEQ.Martin Liska1-12/+12
bfd/ChangeLog: * bfd-in.h (startswith): Add startswith function. (CONST_STRNEQ): Remove. * bfd-in2.h (startswith): Regenerate with make headers. * archive.c (bfd_slurp_armap): Replace usage of CONST_STRNEQ with startswith. (_bfd_slurp_extended_name_table): Likewise. * archive64.c (_bfd_archive_64_bit_slurp_armap): Likewise. * bfd.c (bfd_get_sign_extend_vma): Likewise. (bfd_convert_section_size): Likewise. (bfd_convert_section_contents): Likewise. * coff-stgo32.c (go32exe_create_stub): Likewise. (go32exe_check_format): Likewise. * coffcode.h (styp_to_sec_flags): Likewise. (GNU_DEBUGALTLINK): Likewise. * coffgen.c (_bfd_coff_section_already_linked): Likewise. (coff_gc_sweep): Likewise. (bfd_coff_gc_sections): Likewise. * cofflink.c (coff_link_add_symbols): Likewise. (process_embedded_commands): Likewise. * compress.c (bfd_is_section_compressed_with_header): Likewise. (bfd_init_section_decompress_status): Likewise. * dwarf2.c (find_debug_info): Likewise. (place_sections): Likewise. * ecoff.c (_bfd_ecoff_slurp_armap): Likewise. * elf-m10300.c (_bfd_mn10300_elf_size_dynamic_sections): Likewise. * elf.c (_bfd_elf_make_section_from_shdr): Likewise. (assign_section_numbers): Likewise. (elfcore_grok_win32pstatus): Likewise. * elf32-arm.c (cmse_scan): Likewise. (elf32_arm_gc_mark_extra_sections): Likewise. (elf32_arm_size_dynamic_sections): Likewise. (is_arm_elf_unwind_section_name): Likewise. * elf32-bfin.c (bfin_size_dynamic_sections): Likewise. * elf32-cr16.c (_bfd_cr16_elf_size_dynamic_sections): Likewise. * elf32-cris.c (elf_cris_size_dynamic_sections): Likewise. * elf32-csky.c (csky_elf_size_dynamic_sections): Likewise. * elf32-hppa.c (elf32_hppa_size_dynamic_sections): Likewise. * elf32-iq2000.c (iq2000_elf_check_relocs): Likewise. * elf32-lm32.c (lm32_elf_size_dynamic_sections): Likewise. * elf32-m32r.c (m32r_elf_size_dynamic_sections): Likewise. * elf32-m68k.c (elf_m68k_size_dynamic_sections): Likewise. * elf32-metag.c (elf_metag_size_dynamic_sections): Likewise. * elf32-msp430.c (msp430_elf_relax_delete_bytes): Likewise. * elf32-nios2.c (nios2_elf32_size_dynamic_sections): Likewise. * elf32-or1k.c (or1k_elf_size_dynamic_sections): Likewise. * elf32-ppc.c (ppc_elf_size_dynamic_sections): Likewise. * elf32-s390.c (elf_s390_size_dynamic_sections): Likewise. * elf32-score.c (s3_bfd_score_elf_size_dynamic_sections): Likewise. * elf32-score7.c (s7_bfd_score_elf_size_dynamic_sections): Likewise. * elf32-sh.c (sh_elf_size_dynamic_sections): Likewise. * elf32-tic6x.c (is_tic6x_elf_unwind_section_name): Likewise. (elf32_tic6x_size_dynamic_sections): Likewise. * elf32-vax.c (elf_vax_size_dynamic_sections): Likewise. * elf32-xtensa.c (elf_xtensa_size_dynamic_sections): Likewise. (xtensa_is_insntable_section): Likewise. (xtensa_is_littable_section): Likewise. (xtensa_is_proptable_section): Likewise. (xtensa_property_section_name): Likewise. (xtensa_callback_required_dependence): Likewise. * elf64-alpha.c (elf64_alpha_size_dynamic_sections): Likewise. * elf64-hppa.c (elf64_hppa_size_dynamic_sections): Likewise. * elf64-ia64-vms.c (is_unwind_section_name): Likewise. (get_reloc_section): Likewise. (elf64_ia64_size_dynamic_sections): Likewise. (elf64_ia64_object_p): Likewise. * elf64-mmix.c (mmix_elf_add_symbol_hook): Likewise. * elf64-ppc.c (ppc64_elf_size_dynamic_sections): Likewise. * elf64-s390.c (elf_s390_size_dynamic_sections): Likewise. * elflink.c (elf_link_add_object_symbols): Likewise. (_bfd_elf_gc_mark_extra_sections): Likewise. (bfd_elf_parse_eh_frame_entries): Likewise. (_bfd_elf_section_already_linked): Likewise. * elfnn-aarch64.c (elfNN_aarch64_size_dynamic_sections): Likewise. * elfnn-ia64.c (is_unwind_section_name): Likewise. (elfNN_ia64_size_dynamic_sections): Likewise. (elfNN_ia64_object_p): Likewise. * elfxx-mips.c (FN_STUB_P): Likewise. (CALL_STUB_P): Likewise. (CALL_FP_STUB_P): Likewise. (_bfd_mips_elf_section_from_shdr): Likewise. (_bfd_mips_elf_fake_sections): Likewise. (_bfd_mips_elf_size_dynamic_sections): Likewise. (_bfd_mips_final_write_processing): Likewise. (_bfd_mips_elf_final_link): Likewise. * elfxx-sparc.c (_bfd_sparc_elf_size_dynamic_sections): Likewise. * elfxx-x86.c (elf_i386_is_reloc_section): Likewise. (elf_x86_64_is_reloc_section): Likewise. * hpux-core.c (thread_section_p): Likewise. * libcoff.h (bfd_pei_p): Likewise. * linker.c (REAL): Likewise. (unwrap_hash_lookup): Likewise. (_bfd_generic_link_add_one_symbol): Likewise. * mmo.c (mmo_internal_write_section): Likewise. * osf-core.c (osf_core_core_file_p): Likewise. * pef.c (bfd_pef_print_symbol): Likewise. * pei-x86_64.c (pex64_print_all_pdata_sections): Likewise. * som.c (som_slurp_symbol_table): Likewise. (som_slurp_armap): Likewise. * wasm-module.c (wasm_compute_custom_section_file_position): Likewise. binutils/ChangeLog: * dlltool.c (scan_drectve_symbols): Replace usage of CONST_STRNEQ with startswith. * emul_aix.c (ar_emul_aix_parse_arg): Likewise. * objcopy.c (is_mergeable_note_section): Likewise. * objdump.c (dump_dwarf_section): Likewise. * prdbg.c (pr_method_type): Likewise. (pr_class_baseclass): Likewise. (tg_class_baseclass): Likewise. * readelf.c (process_lto_symbol_tables): Likewise. * stabs.c (ULLHIGH): Likewise. (parse_stab_argtypes): Likewise. (stab_demangle_function_name): Likewise. gas/ChangeLog: * config/tc-i386.c (md_parse_option): Replace usage of CONST_STRNEQ with startswith. (x86_64_section_word): Likewise. * config/tc-sparc.c (md_parse_option): Likewise. gdb/ChangeLog: * arm-tdep.c (show_disassembly_style_sfunc): Replace usage of CONST_STRNEQ with startswith. (_initialize_arm_tdep): Likewise. ld/ChangeLog: * emultempl/aix.em: Replace usage of CONST_STRNEQ with startswith. * emultempl/beos.em: Likewise. * emultempl/elf.em: Likewise. * emultempl/pe.em: Likewise. * emultempl/pep.em: Likewise. * emultempl/xtensaelf.em: Likewise. * ldctor.c (ctor_prio): Likewise. * ldelf.c (ldelf_try_needed): Likewise. (ldelf_parse_ld_so_conf): Likewise. (ldelf_after_open): Likewise. (output_rel_find): Likewise. (ldelf_place_orphan): Likewise. * ldfile.c (ldfile_add_library_path): Likewise. * ldlang.c (lang_add_input_file): Likewise. * ldmain.c (get_sysroot): Likewise. (get_emulation): Likewise. (add_archive_element): Likewise. * ldwrite.c (unsplittable_name): Likewise. (clone_section): Likewise. * lexsup.c (parse_args): Likewise. * pe-dll.c (is_import): Likewise. (pe_implied_import_dll): Likewise. opcodes/ChangeLog: * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith. * arc-dis.c (parse_option): Likewise. * arm-dis.c (parse_arm_disassembler_options): Likewise. * cris-dis.c (print_with_operands): Likewise. * h8300-dis.c (bfd_h8_disassemble): Likewise. * i386-dis.c (print_insn): Likewise. * ia64-gen.c (fetch_insn_class): Likewise. (parse_resource_users): Likewise. (in_iclass): Likewise. (lookup_specifier): Likewise. (insert_opcode_dependencies): Likewise. * mips-dis.c (parse_mips_ase_option): Likewise. (parse_mips_dis_option): Likewise. * s390-dis.c (disassemble_init_s390): Likewise. * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
2021-03-12Re: x86: correct decoding of nop/reserved space (0f18 ... 0x1f)Alan Modra1-1/+1
* i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
2021-03-11x86: re-order logic in OP_XMM()Jan Beulich1-35/+31
Instead of excluding an increasing number of modes in the initial if(), check the special modes first.
2021-03-11x86: drop a few redundant EVEX-related checksJan Beulich1-4/+3
vex.b can only be set when vex.evex is also set. Similarly vex.evex can only be set when need_vex is also set.
2021-03-11x86: remove stray uses of xmmq_modeJan Beulich1-4/+1
xmmq_mode is documented to not allow for broadcast - don't include it in respective checks in OP_E_memory().
2021-03-10x86/Intel: correct AVX512 S/G disassemblyJan Beulich1-70/+12
Commit 6ff00b5e12e7 ("x86/Intel: correct permitted operand sizes for AVX512 scatter/gather") brought the assembler side of AVX512 S/G insn handling in line with AVX2's, but the disassembler side was forgotten. This has the benefit of - allowing to fold a number of table entries, - rendering a few #define-s and enumerators unused.
2021-03-10x86: re-arrange enumerator and table entry orderJan Beulich1-77/+79
Some of the enumerators have ended up misplaced under the general current ordering scheme. Move them (and their table entries) around accordingly. Add a couple of blank lines as separators when close to code being touched anyway. Also drop the odd 0F from 0FXOP (there's no "0f" involved there anywhere) infixes where the respective enum gets played with anyway.
2021-03-10x86: reuse further VEX entries for EVEXJan Beulich1-17/+11
When the VEX.L=1 decode matches that of both EVEX.L'L=1 and EVEX.L'L=2 (typically when all three are invalid) the (smaller) VEX table entry can be reused by EVEX, instead of duplicating data. (Note that XM and XMM as well as EXxmm_md and EXd are equivalent at least for the purposes here.)
2021-03-10x86: reuse VEX entries for EVEX vperm{q,pd}Jan Beulich1-4/+2
By matching VEX decode order (L before W), some EVEX entries can refer back to VEX ones instead of carrying duplicates.
2021-03-10x86: re-arrange order of decode for various EVEX opcodesJan Beulich1-79/+42
The order of decodes influences the overall number of table entries. Reduce table size quite a bit by first decoding few-alternatives attributes common to all valid leaves. This also adds a PREFIX_DATA 7531c61332db ("x86: simplify decode of opcodes valid with (embedded) 66 prefix only") missed to apply to vbroadcastf64x4.
2021-03-10x86: re-arrange order of decode for various mask reg opcodesJan Beulich1-600/+328
The order of decodes influences the overall number of table entries. Reduce table size quite a bit by first decoding few-alternatives attributes common to all valid leaves.
2021-03-10x86: re-arrange order of decode for various VEX opcodesJan Beulich1-154/+70
The order of decodes influences the overall number of table entries. Reduce table size quite a bit by first decoding few-alternatives attributes common to all valid leaves.
2021-03-10x86: re-arrange order of decode for various legacy opcodesJan Beulich1-70/+28
The order of decodes influences the overall number of table entries. Reduce table size quite a bit by first decoding few-alternatives attributes common to all valid leaves.
2021-03-10x86: correct decoding of nop/reserved space (0f18 ... 0x1f)Jan Beulich1-48/+45
All encodings not used in this range are (reserved) NOPs. Hence their decoding should be fully consistent. For this to work the PREFIX_IGNORED logic needs slightly extending, such that the attribute will also - have an effect when used inside prefix_table[], yet without always falling back to using slot 0, - cause prefixes marked as ignored while decoding through prefix_table[] to no longer be considered decoded, when encountered in a subsequent decoding step. In adjacent code also drop meaningless PREFIX_OPCODE.
2021-03-09x86-64: make SYSEXIT handling similar to SYSRET'sJan Beulich1-1/+1
Despite SYSEXIT being an Intel-only insn in long mode, its behavior there is similar to SYSRET's: Depending on REX.W execution continues in either 64-bit or compatibility mode. Hence distinguishing by suffix is as necessary here as it is there.
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-11-29x86: Do not dump DS/CS segment overrides for branch hintsBorislav Petkov1-2/+11
The previous change "x86: Ignore CS/DS/ES/SS segment-override prefixes in 64-bit mode" to ignore segment override prefixes in 64-bit mode lead to dumping branch hints as excessive prefixes: ffffffff8109d5a0 <vmx_get_rflags>: ... ffffffff8109d601: 3e 77 0a ds ja,pt ffffffff8109d60e <vmx_get_rflags+0x6e> ^^^^^ In this particular case, those prefixes are not excessive but are used to provide branch hints - taken/not-taken - to the CPU. Assign active_seg_prefix in that particular case to consume them. gas/ 2002-11-29 Borislav Petkov <bp@suse.de> * testsuite/gas/i386/branch.d: Add new branch insns test. * testsuite/gas/i386/branch.s: Likewise. * testsuite/gas/i386/i386.exp: Insert the new branch test. * testsuite/gas/i386/x86-64-branch.d: Test for branch hints insns. * testsuite/gas/i386/x86-64-branch.s: Likewise. * testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise. opcodes/ 2020-11-28 Borislav Petkov <bp@suse.de> * i386-dis.c (print_insn): Set active_seg_prefix for branch hint insns to not dump branch hint prefixes 0x2E and 0x3E as unused prefixes.
2020-11-14x86: Ignore CS/DS/ES/SS segment-override prefixes in 64-bit modeBorislav Petkov1-5/+20
"In 64-bit mode, the CS, DS, ES, and SS segment-override prefixes have no effect. These four prefixes are not treated as segment-override prefixes for the purposes of multiple-prefix rules. Instead, they are treated as null prefixes." (AMD APM v2). However, objdump disassembles instructions containing those ignored prefixes by still generating that segment override: 66 66 2e 0f 1f 84 00 data16 nopw %cs:0x0(%rax,%rax,1) 00 00 00 00 Print those segment override prefixes as excessive ones: 66 66 2e 0f 1f 84 00 data16 cs nopw 0x0(%rax,%rax,1) 00 00 00 00 which is what they actually are - they have no effect and the decoding hardware ignores them. gas/ 2020-11-14 Borislav Petkov <bp@suse.de> * testsuite/gas/i386/x86-64-segovr.d: Adjust regexes. * testsuite/gas/i386/x86-64-nops.d: Likewise. * testsuite/gas/i386/x86-64-nops-1.d: Likewise. * testsuite/gas/i386/x86-64-nops-1-g64.d: Likewise. * testsuite/gas/i386/x86-64-nops-1-core2.d: Likewise. * testsuite/gas/i386/x86-64-nops-1-k8.d: Likewise. * testsuite/gas/i386/x86-64-nops-2.d: Likewise. * testsuite/gas/i386/x86-64-nops-3.d: Likewise. * testsuite/gas/i386/x86-64-nops-4.d: Likewise. * testsuite/gas/i386/x86-64-nops-4-core2.d: Likewise. * testsuite/gas/i386/x86-64-nops-4-k8.d: Likewise. * testsuite/gas/i386/x86-64-nops-5.d: Likewise. * testsuite/gas/i386/x86-64-nops-5-k8.d: Likewise. * testsuite/gas/i386/x86-64-nops-7.d: Likewise. * testsuite/gas/i386/x86-64-nop-1.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1a.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1b.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1c.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1d.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-1g.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-2c.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-6.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-7.d: Likewise. * testsuite/gas/i386/x86-64-align-branch-8.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-1-core2.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-1-k8.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-1.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-2.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-3.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-4-core2.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-4-k8.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-4.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-5-k8.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops-5.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops.d:: Likewise. ld/ 2020-11-14 Borislav Petkov <bp@suse.de> * testsuite/ld-x86-64/pe-x86-64-4.od: Adjust regexes. * testsuite/ld-x86-64/tlsld3.dd: Likewise. * testsuite/ld-x86-64/tlsld4.dd: Likewise. opcodes/ 2020-11-14 Borislav Petkov <bp@suse.de> * i386-dis.c (ckprefix): Do not assign active_seg_prefix in 64-bit addressing mode. (NOTRACK_Fixup): Test prefixes for PREFIX_DS, instead of active_seg_prefix.
2020-10-26Change avxvnni disassembler output from {vex3} to {vex}Cui,Lili1-1/+0
gas/ * testsuite/gas/i386/avx-vnni.d: Change psuedo prefix from {vex3} to {vex} * testsuite/gas/i386/x86-64-avx-vnni.d: Likewise. opcodes/ * i386-dis.c: Change "XV" to print "{vex}" pseudo prefix.
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian1-0/+41
gas/ * config/tc-i386.c (cpu_arch): Add CPU_ZNVER3_FLAGS flags. (i386_align_code): Add PROCESSOR_ZNVER cases. * doc/c-i386.texi: Add znver3, snp, invlpgb and tlbsync. * gas/i386/i386.exp: Add new znver3 test cases. * gas/i386/arch-14-znver3.d: New. * gas/i386/arch-14.d: New. * gas/i386/arch-14.s: New. * gas/i386/invlpgb.d: New. * gas/i386/invlpgb64.d: New. * gas/i386/invlpgb.s: New. * gas/i386/snp.d: New. * gas/i386/snp64.d: New. * gas/i386/snp.s: New. * gas/i386/tlbsync.d: New. * gas/i386/tlbsync.s: New. * gas/i386/x86-64-arch-4-znver3.d: New. * gas/i386/x86-64-arch-4.d: New. * gas/i386/x86-64-arch-4.s: New. opcodes/ * i386-dis.c (rm_table): Add tlbsync, snp, invlpgb. * i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS, CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS. Add CPU_ZNVER3_FLAGS. (cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP. * i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP. * i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate, rmpupdate, rmpadjust. * i386-init.h: Re-generated. * i386-tbl.h: Re-generated.
2020-10-14x86: Support Intel AVX VNNIH.J. Lu1-6/+37
Intel AVX VNNI instructions are marked with CpuVEX_PREFIX. Without the pseudo {vex} prefix, mnemonics of Intel VNNI instructions are encoded with the EVEX prefix. The pseudo {vex} prefix can be used to encode mnemonics of Intel VNNI instructions with the VEX prefix. gas/ * NEWS: Add Intel AVX VNNI. * config/tc-i386.c (cpu_arch): Add .avx_vnni and noavx_vnni. (cpu_flags_match): Support CpuVEX_PREFIX. * doc/c-i386.texi: Document .avx_vnni, noavx_vnni and how to encode Intel VNNI instructions with VEX prefix. * testsuite/gas/i386/avx-vnni.d: New file. * testsuite/gas/i386/avx-vnni.s: Likewise. * testsuite/gas/i386/x86-64-avx-vnni.d: Likewise. * testsuite/gas/i386/x86-64-avx-vnni.s: Likewise. * testsuite/gas/i386/i386.exp: Run AVX VNNI tests. opcodes/ * i386-dis.c (PREFIX_VEX_0F3850): New. (PREFIX_VEX_0F3851): Likewise. (PREFIX_VEX_0F3852): Likewise. (PREFIX_VEX_0F3853): Likewise. (VEX_W_0F3850_P_2): Likewise. (VEX_W_0F3851_P_2): Likewise. (VEX_W_0F3852_P_2): Likewise. (VEX_W_0F3853_P_2): Likewise. (prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851, PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853. (vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2, VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2. (putop): Add support for "XV" to print "{vex3}" pseudo prefix. * i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in CPU_UNKNOWN_FLAGS. Add CPU_AVX_VNNI_FLAGS and CPU_ANY_AVX_VNNI_FLAGS. (cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX. * i386-opc.h (CpuAVX_VNNI): New. (CpuVEX_PREFIX): Likewise. (i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix. * i386-opc.tbl: Add Intel AVX VNNI instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2020-10-14x86: Add support for Intel HRESET instructionLili Cui1-1/+24
gas/ * NEWS: Add Intel HRESET. * config/tc-i386.c (cpu_arch): Add .hreset. (cpu_noarch): Likewise. * doc/c-i386.texi: Document .hreset, nohreset. * testsuite/gas/i386/i386.exp: Run HRESET tests. * testsuite/gas/i386/hreset.d: New file. * testsuite/gas/i386/x86-64-hreset.d: Likewise. * testsuite/gas/i386/hreset.s: Likewise. opcodes/ * i386-dis.c (PREFIX_0F3A0F): New. (MOD_0F3A0F_PREFIX_1): Likewise. (REG_0F3A0F_PREFIX_1_MOD_3): Likewise. (RM_0F3A0F_P_1_MOD_3_REG_0): Likewise. (prefix_table): Add PREFIX_0F3A0F. (mod_table): Add MOD_0F3A0F_PREFIX_1. (reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3. (rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0. * i386-gen.c (cpu_flag_init): Add HRESET_FLAGS, CPU_ANY_HRESET_FLAGS. (cpu_flags): Add CpuHRESET. (output_i386_opcode): Allow 4 byte base_opcode. * i386-opc.h (enum): Add CpuHRESET. (i386_cpu_flags): Add cpuhreset. * i386-opc.tbl: Add Intel HRESET instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-10-14x86: Support Intel UINTRLili Cui1-6/+69
gas/ * NEWS: Add Intel UINTR. * config/tc-i386.c (cpu_arch): Add .uintr. (cpu_noarch): Likewise. * doc/c-i386.texi: Document .uintr and nouintr. * testsuite/gas/i386/i386.exp: Run UINTR tests. * testsuite/gas/i386/x86-64-uintr.d: Likewise. * testsuite/gas/i386/x86-64-uintr.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_MOD_3_0F01_REG_5_RM_4, PREFIX_MOD_3_0F01_REG_5_RM_5, PREFIX_MOD_3_0F01_REG_5_RM_6, PREFIX_MOD_3_0F01_REG_5_RM_7, X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1, X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1, X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1, X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1, X86_64_0FC7_REG_6_MOD_3_PREFIX_1. (prefix_table): New instructions (see prefixes above). (rm_table): Likewise * i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS, CPU_ANY_UINTR_FLAGS. (cpu_flags): Add CpuUINTR. * i386-opc.h (enum): Add CpuUINTR. (i386_cpu_flags): Add cpuuintr. * i386-opc.tbl: Add UINTR insns. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-10-05x86-64: Always display suffix for %LQ in 64bitH.J. Lu1-1/+1
In 64bit, assembler generates a warning for "sysret": $ echo sysret | as --64 -o x.o - {standard input}: Assembler messages: {standard input}:1: Warning: no instruction mnemonic suffix given and no register operands; using default for `sysret' Always display suffix for %LQ in 64bit to display "sysretl". gas/ PR binutils/26704 * testsuite/gas/i386/noreg64-data16.d: Expect sysretl instead of sysret. * testsuite/gas/i386/noreg64.d: Likewise. * testsuite/gas/i386/x86-64-intel64.d: Likewise. * testsuite/gas/i386/x86-64-opcode.d: Likewise. opcodes/ PR binutils/26704 * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
2020-10-05x86: Clear modrm if not neededH.J. Lu1-4/+8
The MODRM byte can be checked to display the instruction name only if the MODRM byte needed. Clear modrm if the MODRM byte isn't needed so that modrm field checks in putop like, modrm.mod == N with N != 0, can be done without checking need_modrm. gas/ PR binutils/26705 * testsuite/gas/i386/x86-64-suffix.s: Add "mov %rsp,%rbp" before sysretq. * testsuite/gas/i386/x86-64-suffix-intel.d: Updated. * testsuite/gas/i386/x86-64-suffix.d: Likewise. opcodes/ PR binutils/26705 * i386-dis.c (print_insn): Clear modrm if not needed. (putop): Check need_modrm for modrm.mod != 3. Don't check need_modrm for modrm.mod == 3.
2020-09-25Put together MOD_VEX_0F38* in i386-dis.c,Cui,Lili1-62/+62
There are 11 MOD_VEX_0F38* inserted in MOD_0F38* group, which should be placed in MOD_VEX_0F38* group. opcode/ PR 26654 *i386-dis.c (enum): Put MOD_VEX_0F38* together.
2020-09-24Add support for Intel TDX instructions.Cui,Lili1-4/+61
gas/ * NEWS: Add TDX. * config/tc-i386.c (cpu_arch): Add .tdx. (cpu_noarch): Likewise. * doc/c-i386.texi: Document tdx. * testsuite/gas/i386/i386.exp: Run tdx tests. * testsuite/gas/i386/tdx.d: Likewise. * testsuite/gas/i386/tdx.s: Likewise. * testsuite/gas/i386/x86-64-tdx.d: Likewise. * testsuite/gas/i386/x86-64-tdx.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5, PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7, X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2, X86_64_0F01_REG_1_RM_7_P_2. (prefix_table): Likewise. (x86_64_table): Likewise. (rm_table): Likewise. * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS and CPU_ANY_TDX_FLAGS. (cpu_flags): Add CpuTDX. * i386-opc.h (enum): Add CpuTDX. (i386_cpu_flags): Add cputdx. * i386-opc.tbl: Add TDX insns. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo1-7/+100
gas/ * NEWS: Add Key Locker. * config/tc-i386.c (cpu_arch): Add .kl and .wide_kl. (cpu_noarch): Likewise. * doc/c-i386.texi: Document kl and wide_kl. * testsuite/gas/i386/i386.exp: Run keylocker tests. * testsuite/gas/i386/keylocker-intel.d: New test. * testsuite/gas/i386/keylocker.d: Likewise. * testsuite/gas/i386/keylocker.s: Likewise. * testsuite/gas/i386/x86-64-keylocker-intel.d: Likewise. * testsuite/gas/i386/x86-64-keylocker.d: Likewise. * testsuite/gas/i386/x86-64-keylocker.s: Likewise. * testsuite/gas/i386/x86-64-property-10.d: Likewise. * testsuite/gas/i386/property-10.d: Likewise. * testsuite/gas/i386/property-10.s: Likewise. opcodes/ * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1, MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1, MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1, MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1, PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB. (reg_table): New instructions (see prefixes above). (prefix_table): Likewise. (three_byte_table): Likewise. (mod_table): Likewise * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS, CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS. (cpu_flags): Likewise. (operand_type_init): Likewise. * i386-opc.h (enum): Add CpuKL and CpuWide_KL. (i386_cpu_flags): Add cpukl and cpuwide_kl. * i386-opc.tbl: Add KL and WIDE_KL insns. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2020-09-02ubsan: i386-dis.cAlan Modra1-13/+13
i386-dis.c:12207 left shift of 128 by 24 places cannot be represented in type 'long int' i386-dis.c:12220 left shift of 128 by 24 places cannot be represented in type 'long int' i386-dis.c:12222 left shift of 1 by 31 places cannot be represented in type 'long int' i386-dis.c:12222 signed integer overflow: 162254319 - -2147483648 cannot be represented in type 'long int' * i386-dis.c (OP_E_memory): Don't cast to signed type when negating. (get32, get32s): Use unsigned types in shift expressions.
2020-07-21Revert "x86: Don't display eiz with no scale"Jan Beulich1-1/+1
This reverts commit 04c662e2b66bedd050f97adec19afe0fcfce9ea7. In my underlying suggestion I neglected the fact that in those cases (,%eiz,1) is the only visible indication that 32-bit addressing is in effect.
2020-07-15x86: Don't display eiz with no scaleH.J. Lu1-1/+1
Change 67 48 8b 1c 25 ef cd ab 89 mov 0x89abcdef(,%eiz,1),%rbx to 67 48 8b 1c 25 ef cd ab 89 mov 0x89abcdef,%rbx in AT&T syntax and 67 48 8b 1c 25 ef cd ab 89 mov rbx,QWORD PTR [eiz*1+0x89abcdef] to 67 48 8b 1c 25 ef cd ab 89 mov rbx,QWORD PTR ds:0x89abcdef in Intel syntax. gas/ PR gas/26237 * testsuite/gas/i386/evex-no-scale-64.d: Updated. * testsuite/gas/i386/addr32.d: Likewise. * testsuite/gas/i386/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/x86-64-addr32.d: Likewise. opcodes/ PR gas/26237 * i386-dis.c (OP_E_memory): Don't display eiz with no scale without base nor index registers.
2020-07-15x86: move putop() case labels to restore alphabetic sortingJan Beulich1-49/+48
... as far as non-fall-through behavior permits.
2020-07-15x86: make PUSH/POP disassembly uniformJan Beulich1-30/+20
Irrespective of their encoding the resulting output should look the same. Therefore wire the handling of PUSH/POP with GPR operands encoded in the main opcode byte to the same logic used for other operands. This frees up yet another macro character.
2020-07-15x86: avoid attaching suffixes to unambiguous insnsJan Beulich1-99/+44
"Unambiguous" is is in particular taking as reference the assembler, which also accepts certain insns - despite them allowing for varying operand size, and hence in principle being ambiguous - without any suffix. For example, from the very beginning of the life of x86-64 I had trouble understanding why a plain and simple RET had to be printed as RETQ. In case someone really used the 16-bit form, RETW disambiguates the two quite fine.
2020-07-14x86-64: Zero-extend lower 32 bits displacement to 64 bitsH.J. Lu1-2/+7
Since the addr32 (0x67) prefix zero-extends the lower 32 bits address to 64 bits, change disassembler to zero-extend the lower 32 bits displacement to 64 bits when there is no base nor index registers. gas/ PR gas/26237 * testsuite/gas/i386/addr32.s: Add tests for 32-bit wrapped around address. * testsuite/gas/i386/x86-64-addr32.s: Likewise. * testsuite/gas/i386/addr32.d: Updated. * testsuite/gas/i386/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/x86-64-addr32.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-addr32.d: Likewise. opcodes/ PR gas/26237 * i386-dis.c (OP_E_memory): Without base nor index registers, 32-bit displacement to 64 bits.
2020-07-14x86/Intel: debug registers are named DRnJan Beulich1-1/+1
%db<n> is an AT&T invention; the Intel documentation and MASM have only ever specified DRn (in line with CRn and TRn). (In principle gas also shouldn't accept the names in Intel mode, but at least for now I've kept things as they are. Perhaps as a first step this should just be warned about.)
2020-07-14x86: drop Rm and the 'L' macroJan Beulich1-74/+54
Rm (and hence OP_R()) can be dropped by making 'Z' force modrm.mod to 3 (for OP_E()) instead of ignoring it. While at it move 'Z' handling to its designated place (after 'Y'; 'W' handling will be moved by a later change). Moves to/from TRn are illegal in 64-bit mode and thus get converted to honor this at the same time (also getting them in line with moves to/from CRn/DRn ModRM.mod handling wise). This then also frees up the L macro.
2020-07-14x86: drop Rdq, Rd, and MaskRJan Beulich1-56/+60
Rdq, Rd, and MaskR can be replaced by Edq, Ed / Rm, and MaskE respectively, as OP_R() doesn't enforce ModRM.mod == 3, and hence where MOD matters but hasn't been decoded yet it needs to be anyway. (The case of converting to Rm is temporary until a subsequent change.)
2020-07-14x86: simplify decode of opcodes valid only without any (embedded) prefixJan Beulich1-135/+42
In this case there's no need to go through prefix_table[] at all - the .prefix_requirement == PREFIX_OPCODE machinery takes care of this case already. A couple of further adjustments are needed though: - Gv / Ev and alike then can't be used (needs to be Gdq / Edq instead), - dq_mode and friends shouldn't lead to PREFIX_DATA getting set in used_prefixes.
2020-07-14x86: also use %BW / %DQ for kshift*Jan Beulich1-65/+17
2020-07-14x86: simplify decode of opcodes valid with (embedded) 66 prefix onlyJan Beulich1-3474/+788
The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14x86: drop further EVEX table entries that can be served by VEX onesJan Beulich1-12/+8
A few cases were missed by 6df22cf64c93 ("x86: drop EVEX table entries that can be served by VEX ones").
2020-07-14x86: drop need_vex_regJan Beulich1-48/+15
It was quite odd for the prior operand handling to have to clear this flag for the actual operand handling to print nothing. Have the actual operand handling determine whether the operand is actually present. With this {d,q}_scalar_swap_mode become unused and hence also get dropped.
2020-07-14x86: drop Vex128 and Vex256Jan Beulich1-53/+45
These are only used when VEX.L or EVEX.L'L have already been decoded, and hence the "normal" length dependent name determination is quite fine. Adjust a few enumerators to make clear that vex_len_table[] has been consulted; be consistent and do so for all *f128 and *i128 insns in one go.
2020-07-14x86: replace %LW by %DQJan Beulich1-9/+9
This makes more visible what the two alternatives will be that result from this macro.
2020-07-14x86: merge/move logic determining the EVEX disp8 shiftJan Beulich1-29/+16
Fold redundant case blocks and move the extra adjustments logic into the single case block that actually needs it - there's no need to go through the extra logic for all the other cases. Also utilize there that vex.b cannot be set at this point, due to earlier logic. Reduce the comment there, which was partly stale anyway.
2020-07-14x86: extend %BW use to VP{COMPRESS,EXPAND}{B,W}Jan Beulich1-12/+7
Unlike the earlier ones these also need their operands adjusted. Replace the (mis-described: there's nothing "scalar" here) {b,w}_scalar_mode by a single new mode, with the actual unit width controlled by EVEX.W.
generated by cgit v1.1 at 2024-11-19 20:12:43 +0000