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path: root/opcodes/i386-dis.c
AgeCommit message (Expand)AuthorFilesLines
2021-08-19x86: Put back 3 aborts in OP_E_memoryH.J. Lu1-3/+3
2021-08-19x86: Avoid abort on invalid broadcastH.J. Lu1-4/+4
2021-08-05[PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili1-27/+225
2021-07-23x86: express unduly set rounding control bits in disassemblyJan Beulich1-37/+53
2021-07-22x86: drop dq{b,d}_modeJan Beulich1-30/+13
2021-07-22x86: drop vex_scalar_w_dq_modeJan Beulich1-28/+18
2021-07-22x86: drop xmm_m{b,w,d,q}_modeJan Beulich1-127/+54
2021-07-22x86: fold duplicate vector register printing codeJan Beulich1-74/+33
2021-07-22x86: drop vex_mode and vex_scalar_modeJan Beulich1-11/+7
2021-07-22x86: correct EVEX.V' handling outside of 64-bit modeJan Beulich1-4/+16
2021-07-22x86: fold duplicate code in MOVSXD_Fixup()Jan Beulich1-16/+10
2021-07-22x86: fold duplicate register printing codeJan Beulich1-105/+14
2021-07-22x86-64: properly bounds-check %bnd<N> in OP_G()Jan Beulich1-1/+1
2021-07-22x86-64: generalize OP_G()'s EVEX.R' handlingJan Beulich1-1/+8
2021-07-22x86: correct VCVT{,U}SI2SD rounding mode handlingJan Beulich1-3/+1
2021-07-22x86: drop OP_Mask()Jan Beulich1-22/+2
2021-07-14x86: Add int1 as one byte opcode 0xf1H.J. Lu1-1/+1
2021-03-31Use bool in opcodesAlan Modra1-4/+4
2021-03-25x86: flag bad S/G insn operand combinationsJan Beulich1-14/+70
2021-03-25x86: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clearJan Beulich1-0/+7
2021-03-22Add startswith function and use it instead of CONST_STRNEQ.Martin Liska1-12/+12
2021-03-12Re: x86: correct decoding of nop/reserved space (0f18 ... 0x1f)Alan Modra1-1/+1
2021-03-11x86: re-order logic in OP_XMM()Jan Beulich1-35/+31
2021-03-11x86: drop a few redundant EVEX-related checksJan Beulich1-4/+3
2021-03-11x86: remove stray uses of xmmq_modeJan Beulich1-4/+1
2021-03-10x86/Intel: correct AVX512 S/G disassemblyJan Beulich1-70/+12
2021-03-10x86: re-arrange enumerator and table entry orderJan Beulich1-77/+79
2021-03-10x86: reuse further VEX entries for EVEXJan Beulich1-17/+11
2021-03-10x86: reuse VEX entries for EVEX vperm{q,pd}Jan Beulich1-4/+2
2021-03-10x86: re-arrange order of decode for various EVEX opcodesJan Beulich1-79/+42
2021-03-10x86: re-arrange order of decode for various mask reg opcodesJan Beulich1-600/+328
2021-03-10x86: re-arrange order of decode for various VEX opcodesJan Beulich1-154/+70
2021-03-10x86: re-arrange order of decode for various legacy opcodesJan Beulich1-70/+28
2021-03-10x86: correct decoding of nop/reserved space (0f18 ... 0x1f)Jan Beulich1-48/+45
2021-03-09x86-64: make SYSEXIT handling similar to SYSRET'sJan Beulich1-1/+1
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-11-29x86: Do not dump DS/CS segment overrides for branch hintsBorislav Petkov1-2/+11
2020-11-14x86: Ignore CS/DS/ES/SS segment-override prefixes in 64-bit modeBorislav Petkov1-5/+20
2020-10-26Change avxvnni disassembler output from {vex3} to {vex}Cui,Lili1-1/+0
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian1-0/+41
2020-10-14x86: Support Intel AVX VNNIH.J. Lu1-6/+37
2020-10-14x86: Add support for Intel HRESET instructionLili Cui1-1/+24
2020-10-14x86: Support Intel UINTRLili Cui1-6/+69
2020-10-05x86-64: Always display suffix for %LQ in 64bitH.J. Lu1-1/+1
2020-10-05x86: Clear modrm if not neededH.J. Lu1-4/+8
2020-09-25Put together MOD_VEX_0F38* in i386-dis.c,Cui,Lili1-62/+62
2020-09-24Add support for Intel TDX instructions.Cui,Lili1-4/+61
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo1-7/+100
2020-09-02ubsan: i386-dis.cAlan Modra1-13/+13
2020-07-21Revert "x86: Don't display eiz with no scale"Jan Beulich1-1/+1
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