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AgeCommit message (Expand)AuthorFilesLines
2013-10-12Only allow 32-bit/64-bit registers for bndcl/bndcu/bndcnH.J. Lu1-2/+2
2013-10-11opcodes/Roland McGrath1-20/+28
2013-08-19Remove PREFIX_EVEX_0F3A3E and PREFIX_EVEX_0F3A3FH.J. Lu1-2/+0
2013-07-26Add Intel AVX-512 supportH.J. Lu1-31/+1306
2013-07-25Support Intel SHAH.J. Lu1-7/+49
2013-07-24Support Intel MPXH.J. Lu1-47/+126
2013-03-27Properly check address mode for SIBH.J. Lu1-4/+4
2013-02-19Implement Intel SMAP instructionsH.J. Lu1-0/+2
2012-10-24gas/testsuite/Roland McGrath1-58/+61
2012-08-07gas/testsuite/Roland McGrath1-0/+30
2012-08-06gas/testsuite/Roland McGrath1-6/+12
2012-08-06gas/testsuite/Roland McGrath1-30/+34
2012-07-19Use vex_len_table in xop_tableH.J. Lu1-8/+56
2012-07-16Implement RDRSEED, ADX and PRFCHW instructionsH.J. Lu1-1/+11
2012-02-08Implement Intel Transactional Synchronization ExtensionsH.J. Lu1-60/+175
2012-01-13Add vmfuncH.J. Lu1-0/+3
2011-10-26 PR binutils/13348Nick Clifton1-1/+1
2011-08-02opcodes/Quentin Neill1-1/+1
2011-08-01Check R_X86_64_32 overflow and allow R_X86_64_64 for x32.H.J. Lu1-33/+11
2011-07-22Add initial Intel K1OM support.H.J. Lu1-3/+8
2011-07-01Update rorxS.H.J. Lu1-1/+1
2011-06-30Fix rorx in BMI2.H.J. Lu1-1/+1
2011-06-21Re-indent prefix_table.H.J. Lu1-2/+2
2011-06-10Support AVX Programming Reference (June, 2011).H.J. Lu1-960/+840
2011-02-092011-02-09 Michael Snyder <msnyder@vmware.com>Michael Snyder1-5/+5
2011-01-18Properly sign-extend byte.H.J. Lu1-3/+28
2011-01-17Add support for TBM instructions.Quentin Neill1-5/+28
2011-01-05Implement BMI instructions.H.J. Lu1-4/+80
2011-01-04Add VexGdq.H.J. Lu1-2/+8
2010-12-31Add x86-64 ILP32 support.H.J. Lu1-0/+5
2010-10-02Remove duplicated RMAL.H.J. Lu1-1/+0
2010-08-31Fix "pushw imm16" for x86-64 disassembler.H.J. Lu1-38/+30
2010-08-17Replace Eb with Mb on prefetch and prefetchw.H.J. Lu1-2/+2
2010-08-06Add ud1 to x86.H.J. Lu1-2/+2
2010-07-28Add 0F to VEX opcode enums.H.J. Lu1-2259/+2259
2010-07-05Replace rdrnd with rdrand.H.J. Lu1-1/+1
2010-07-01Support AVX Programming Reference (June, 2010)H.J. Lu1-3/+52
2010-05-26Add SIB.H.J. Lu1-4/+28
2010-04-16Remove extra breack.H.J. Lu1-1/+0
2010-04-16Return bad_opcode on unknown bits in opcode.H.J. Lu1-5/+17
2010-04-09bfd/ChangeLogNick Clifton1-8/+0
2010-03-232010-03-22 Sebastian Pop <sebastian.pop@amd.com>Sebastian Pop1-18/+4
2010-02-11Update copyright.H.J. Lu1-1/+1
2010-02-112010-02-10 Quentin Neill <quentin.neill@amd.com>Sebastian Pop1-2/+73
2010-01-28Allow VL=1 on scalar FMA instructions.H.J. Lu1-13/+18
2010-01-27Allow VL=1 on AVX scalar instructions.H.J. Lu1-44/+125
2010-01-24Remove trailing { Bad_Opcode }.H.J. Lu1-1/+0
2010-01-24Remove trailing { Bad_Opcode } in vex_len_table.H.J. Lu1-1/+0
2010-01-24Remove trailing { Bad_Opcode }.H.J. Lu1-1/+0
2010-01-24Remove trailing "(bad)" entries and replace { "(bad)", { XX } }H.J. Lu1-3561/+2647
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