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2020-02-12x86-64: Intel64 adjustments for insns dealing with far pointersJan Beulich1-2/+8
AMD and Intel differ in their handling of far indirect branches as well as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note how the latter three were hybrids so far, while far branches were fully AMD-like.)
2020-01-31x86: replace EXxmm_mdq by EXVexWdqScalarJan Beulich1-7/+1
There's no need to have two operand specifiers / enumerators for the same purpose. This then renders xmm_mdq_mode unused.
2020-01-31x86: drop unused EXVexWdq / vex_w_dq_modeJan Beulich1-7/+3
2020-01-30x86-64: honor vendor specifics for near RETJan Beulich1-2/+16
While vendors agree about default operand size (64 bits) and hence unavilability of a 32-bit form, AMD honors a 16-bit operand size override (0x66) while Intel doesn't.
2020-01-27x86-64: Properly encode and decode movsxdH.J. Lu1-2/+59
movsxd is a 64-bit only instruction. It supports both 16-bit and 32-bit destination registers. Its AT&T mnemonic is movslq which only supports 64-bit destination register. There is also a discrepancy between AMD64 and Intel64 on movsxd with 16-bit destination register. AMD64 supports 32-bit source operand and Intel64 supports 16-bit source operand. This patch updates movsxd encoding and decoding to alow 16-bit and 32-bit destination registers. It also handles movsxd with 16-bit destination register for AMD64 and Intel 64. gas/ PR binutils/25445 * config/tc-i386.c (check_long_reg): Also convert to QWORD for movsxd. * doc/c-i386.texi: Add a node for AMD64 vs. Intel64 ISA differences. Document movslq and movsxd. * testsuite/gas/i386/i386.exp: Run PR binutils/25445 tests. * testsuite/gas/i386/x86-64-movsxd-intel.d: New file. * testsuite/gas/i386/x86-64-movsxd-intel64-intel.d: Likewise. * testsuite/gas/i386/x86-64-movsxd-intel64-inval.l: Likewise. * testsuite/gas/i386/x86-64-movsxd-intel64-inval.s: Likewise. * testsuite/gas/i386/x86-64-movsxd-intel64.d: Likewise. * testsuite/gas/i386/x86-64-movsxd-intel64.s: Likewise. * testsuite/gas/i386/x86-64-movsxd-inval.l: Likewise. * testsuite/gas/i386/x86-64-movsxd-inval.s: Likewise. * testsuite/gas/i386/x86-64-movsxd.d: Likewise. * testsuite/gas/i386/x86-64-movsxd.s: Likewise. opcodes/ PR binutils/25445 * i386-dis.c (MOVSXD_Fixup): New function. (movsxd_mode): New enum. (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd. (intel_operand_size): Handle movsxd_mode. (OP_E_register): Likewise. (OP_G): Likewise. * i386-opc.tbl: Remove Rex64 and allow 32-bit destination register on movsxd. Add movsxd with 16-bit destination register for AMD64 and Intel64 ISAs. * i386-tbl.h: Regenerated.
2020-01-13Add an option to objdump's disassembler to generate ascii art diagrams ↵Thomas Troeger1-1/+60
showing the destinations of flow control instructions. binutils* objdump.c (visualize_jumps, color_output, extended_color_output) (detected_jumps): New variables. (usage): Add the new jump visualization options. (option_values): Add new option value. (long_options): Add the new option. (jump_info_new, jump_info_free): New functions. (jump_info_min_address, jump_info_max_address): Likewise. (jump_info_end_address, jump_info_is_start_address): Likewise. (jump_info_is_end_address, jump_info_size): Likewise. (jump_info_unlink, jump_info_insert): Likewise. (jump_info_add_front, jump_info_move_linked): Likewise. (jump_info_intersect, jump_info_merge): Likewise. (jump_info_sort, jump_info_visualize_address): Likewise. (disassemble_jumps): New function - used to locate jumps. (disassemble_bytes): Add ascii art generation. (disassemble_section): Add scan to locate jumps. (main): Parse the new visualization option. * doc/binutils.texi: Document the new feature. * NEWS: Mention the new feature. opcodes * arm-dis.c (print_insn_arm): Fill in insn info fields for control flow instructions. (print_insn_thumb16, print_insn_thumb32): Likewise. (print_insn): Initialize the insn info. * i386-dis.c (print_insn): Initialize the insn info fields, and detect jumps.
2020-01-09x86: SYSENTER/SYSEXIT are unavailable in 64-bit mode on AMDJan Beulich1-6/+20
The disassembler change is such that in default mode we'd disassemble the insns (for there not ebing any conflicts), but when AMD64 mode was explicitly requested, we'd show them as "(bad)".
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-12-27x86-64: fix Intel64 handling of branch with data16 prefixJan Beulich1-3/+7
The expectation of x86-64-branch-3 for "call" / "jmp" with an obvious direct destination to translate to an indirect _far_ branch is plain wrong. The operand size prefix should have no effect at all on the interpretation of the operand. The main underlying issue here is that the Intel64 templates of the direct branches don't include Disp16, yet various assumptions exist that it would always be there when there's also Disp32/Disp32S, toggled by the operand size prefix (which is being ignored by direct branches in Intel64 mode). Along these lines it was also wrong to base the displacement width decision solely on the operand size prefix: REX.W cancels this effect and hence needs taking into consideration, too. A disassembler change is needed here as well: XBEGIN was wrongly treated the same as direct CALL/JMP, which isn't the case - the operand size prefix does affect displacement size there, it's merely ignored when it comes to updating [ER]IP.
2019-12-04x86/Intel: extend MOVDIRI testingJan Beulich1-1/+1
Test also memory operands with operand size specifier, which was broken prior to dc2be329b950 ("i386: Only check suffix in instruction mnemonic"), due to the template not permitting any suffixes. Note that this uncovered a disassembler issue, which is being fixed here as well.
2019-11-07x86: support further AMD Zen2 instructionsJan Beulich1-0/+2
Both RDPRU and MCOMMIT have been publicly documented meanwhile: https://www.amd.com/system/files/TechDocs/24594.pdf.
2019-11-07x86: adjust register names printed for MONITOR/MWAITJan Beulich1-16/+12
As the comments (here: almost, in the opcode table: fully) correctly state - all register operands except MONITOR's address one are fixed at 32 bit size. Don't print 64-bit registers there. Also adjust x86-64-suffix.d's name such that it wouldn't be identical to x86-64-rep-suffix.d's, but instead resemble that of its sibling x86-64-suffix-intel.d.
2019-11-05x86: fold OP_Mwaitx() into OP_Mwait()Jan Beulich1-24/+5
There's no need to have separate functions, the difference can easily be expressed using the function arguments.
2019-11-05x86: split MONITORX/MWAITX entriesJan Beulich1-2/+14
Both encodings do not ignore the 66/F3/F2 prefixes, so don't have the disassembler ignore them either.
2019-11-05x86: consolidate disassembler enum naming a littleJan Beulich1-75/+75
The original idea looks to have been for names to be composed in the order that decoding gets done, which helps both reading and modifying the code. Switch (back) to this model for some of the affected non- vector insn enumerators.
2019-07-01x86: remove ModRM.mod decoding layer from AVX512F VMOVS{S,D}Jan Beulich1-13/+4
Just like their AVX counterparts they can utilize XMVexScalar / EXdVexScalarS / EXqVexScalarS taking care of dropping the middle operand for their memory forms.
2019-07-01x86: drop a few dead macrosJan Beulich1-5/+0
2019-06-27i386: Check vector length for scatter/gather prefetch instructionsH.J. Lu1-0/+12
Since not all vector lengths are supported by scatter/gather prefetch instructions, decode them only with supported vector lengths. gas/ PR binutils/24719 * testsuite/gas/i386/disassem.s: Add test for vgatherpf0dps with invalid vector length. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24719 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and EVEX_LEN_0F38C7_R_6_P_2_W_1. * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and PREFIX_EVEX_0F38C6_REG_6 entries. * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and EVEX_W_0F38C7_R_6_P_2 entries. * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
2019-06-27x86: fold AVX scalar to/from int conversion insnsJan Beulich1-48/+6
There's no point doing a separate decode of the VEX.L bit - both decoded forms are identical.
2019-06-27x86: allow VEX et al encodings in 16-bit (protected) modeJan Beulich1-33/+30
These encodings aren't valid in real and VM86 modes, but they are very well usable in 16-bit protected mode. A few adjustments in the disassembler tables are needed where Ev or Gv were wrongly used. Additionally an adjustment is needed to avoid printing "addr32" when that's already recognizable by the use of %eiz. Furthermore the Iq operand template was wrong for XOP:0Ah encoding insns: They're having a uniform 32-bit immediate. Drop Iq and introduce Id instead. Clone a few existing test cases to exercise assembler and disassembler.
2019-06-25x86: drop dqa_modeJan Beulich1-10/+0
I assume this mode was needed when EVEX.W handling wasn't really correct yet for other than 64-bit mode. It's clearly not needed anymore. Its elimination also allows dropping the EVEX.W split of VCVT{,U}SI2SS. (For the record, the dropped mode would have been wrong if used in any table entry not already guaranteeing EVEX.W=1.)
2019-06-25x86: simplify OP_I64()Jan Beulich1-40/+3
The only meaningful difference from OP_I() is the handling of the VEX.W=1 case in 64-bit mode for bytemode being v_mode. Funnel everything else into OP_I(), and drop no longer needed local variables.
2019-06-25x86: fix (dis)assembly of certain SSE2 insns in 16-bit modeJan Beulich1-7/+7
MOVNTI was wrongly assembled with a 66h prefix. Add IgnoreSize to address this. It and the scalar to/from integer conversion insns also were also wrongly using Ev / Gv, leading to 16-bit register names being printed when 32-bit ones were meant. Clone the 32-bit SSE2 test to cover both assembler and disassembler.
2019-06-21i386: Break i386-dis-evex.h into small filesH.J. Lu1-19/+9
Break i386-dis-evex.h into small files such that each file is included just once. * i386-dis-evex.h: Break into ... * i386-dis-evex-len.h: New file. * i386-dis-evex-mod.h: Likewise. * i386-dis-evex-prefix.h: Likewise. * i386-dis-evex-reg.h: Likewise. * i386-dis-evex-w.h: Likewise. * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h, i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and i386-dis-evex-mod.h.
2019-06-19i386: Check vector length for EVEX broadcast instructionsH.J. Lu1-0/+10
Since not all vector lengths are supported by EVEX broadcast instructions, decode them only with supported vector lengths. gas/ PR binutils/24700 * testsuite/gas/i386/disassem.s: Add test for vbroadcasti32x8 with invalid vector length. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24700 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and EVEX_W_0F385B_P_2. (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0, EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and EVEX_LEN_0F385B_P_2_W_1. * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum. (EVEX_LEN_0F3819_P_2_W_1): Likewise. (EVEX_LEN_0F381A_P_2_W_0): Likewise. (EVEX_LEN_0F381A_P_2_W_1): Likewise. (EVEX_LEN_0F381B_P_2_W_0): Likewise. (EVEX_LEN_0F381B_P_2_W_1): Likewise. (EVEX_LEN_0F385A_P_2_W_0): Likewise. (EVEX_LEN_0F385A_P_2_W_1): Likewise. (EVEX_LEN_0F385B_P_2_W_0): Likewise. (EVEX_LEN_0F385B_P_2_W_1): Likewise.
2019-06-17i386: Check vector length for vshufXXX/vinsertXXX/vextractXXXH.J. Lu1-1/+13
Since not all vector lengths are supported by vshufXXX, vinsertXXX and vextractXXX, decode them only with supported vector lengths. gas/ PR binutils/24691 * testsuite/gas/i386/disassem.s: Add test for vshuff32x4 with invalid vector length. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24691 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2. (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and EVEX_LEN_0F3A43_P_2_W_1. * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum. (EVEX_LEN_0F3A23_P_2_W_1): Likewise. (EVEX_LEN_0F3A38_P_2_W_0): Likewise. (EVEX_LEN_0F3A38_P_2_W_1): Likewise. (EVEX_LEN_0F3A39_P_2_W_0): Likewise. (EVEX_LEN_0F3A39_P_2_W_1): Likewise. (EVEX_LEN_0F3A3A_P_2_W_0): Likewise. (EVEX_LEN_0F3A3A_P_2_W_1): Likewise. (EVEX_LEN_0F3A3B_P_2_W_0): Likewise. (EVEX_LEN_0F3A3B_P_2_W_1): Likewise. (EVEX_LEN_0F3A43_P_2_W_0): Likewise. (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
2019-06-05i386: Check vector length for EVEX vextractfXX and vinsertfXXH.J. Lu1-1/+9
Since not all vector lengths are supported by EVEX vextractfXX and vinsertfXX, decode them only with supported vector lengths. gas/ PR binutils/24633 * testsuite/gas/i386/disassem.s: Add tests for invalid vector lengths for EVEX vextractfXX and vinsertfXX. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24633 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2. (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0, EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0, EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0, EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0, EVEX_LEN_0F3A1B_P_2_W_1. * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum. (EVEX_LEN_0F3A18_P_2_W_1): Likewise. (EVEX_LEN_0F3A19_P_2_W_0): Likewise. (EVEX_LEN_0F3A19_P_2_W_1): Likewise. (EVEX_LEN_0F3A1A_P_2_W_0): Likewise. (EVEX_LEN_0F3A1A_P_2_W_1): Likewise. (EVEX_LEN_0F3A1B_P_2_W_0): Likewise. (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
2019-06-04i386: Check for reserved VEX.vvvv and EVEX.vvvvH.J. Lu1-10/+14
If VEX.vvvv and EVEX.vvvv are reserved, they must be all 1s, which are all 0s in inverted form. Add check for unused VEX.vvvv and EVEX.vvvv when disassembling VEX and EVEX instructions. gas/ PR binutils/24626 * testsuite/gas/i386/disassem.s: Add tests for reserved VEX.vvvv and EVEX.vvvv. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24626 * i386-dis.c (print_insn): Check for unused VEX.vvvv and EVEX.vvvv when disassembling VEX and EVEX instructions. (OP_VEX): Set vex.register_specifier to 0 after readding vex.register_specifier. (OP_Vex_2src_1): Likewise. (OP_Vex_2src_2): Likewise. (OP_LWP_E): Likewise. (OP_EX_Vex): Don't check vex.register_specifier. (OP_XMM_Vex): Likewise.
2019-06-04Enable Intel AVX512_VP2INTERSECT insnH.J. Lu1-0/+2
This patch enables support for VP2INTERSECT in binutils. Please refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf for VP2INTERSECT details. Make check-gas is ok. gas/ 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_vp2intersect. (cpu_noarch): Likewise. * doc/c-i386.texi: Document avx512_vp2intersect. * testsuite/gas/i386/i386.exp: Run vp2intersect tests. * testsuite/gas/i386/vp2intersect-intel.d: New test. * testsuite/gas/i386/vp2intersect.d: Likewise. * testsuite/gas/i386/vp2intersect.s: Likewise. * testsuite/gas/i386/vp2intersect-inval-bcast.l: Likewise. * testsuite/gas/i386/vp2intersect-inval-bcast.s: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-intel.d: Likewise. * testsuite/gas/i386/x86-64-vp2intersect.d: Likewise. * testsuite/gas/i386/x86-64-vp2intersect.s: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.l: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.s: Likewise. opcodes/ 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3. * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT instructions. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS, CPU_ANY_AVX512_VP2INTERSECT_FLAGS. (cpu_flags): Add CpuAVX512_VP2INTERSECT. * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT. (i386_cpu_flags): Add cpuavx512_vp2intersect. * i386-opc.tbl: Add AVX512_VP2INTERSECT insns. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2019-06-04Add support for Intel ENQCMD[S] instructionsH.J. Lu1-1/+12
This patch enables support for ENQCMD[S] in binutils. Please refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf for ENQCMD[S] details. Make check-gas is ok. gas/ChangeLog: 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com> Lili Cui <lili.cui@intel.com> * doc/c-i386.texi: Document enqcmd. * testsuite/gas/i386/enqcmd-intel.d: New file. * testsuite/gas/i386/enqcmd-inval.l: Likewise. * testsuite/gas/i386/enqcmd-inval.s: Likewise. * testsuite/gas/i386/enqcmd.d: Likewise. * testsuite/gas/i386/enqcmd.s: Likewise. * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise. * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise. * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd.s: Likewise. * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval, enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval, and x86-64-enqcmd. opcodes/ChangeLog: 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (enum): Add MOD_0F38F8_PREFIX_1 and MOD_0F38F8_PREFIX_3. (prefix_table): New instructions (see prefix above). (mod_table): New instructions (see prefix above). * i386-gen.c (cpu_flag_init): Add entries for enqcmd. (cpu_flags): Add a bitfield for enqmcd. * i386-init.h: Regenerated. * i386-opc.h (enum): Add CpuENQCMD. (i386_cpu_flags): Add a bitfield for cpuenqcmd. * i386-opc.tbl: Add enqcmd and enqcmds instructions. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.
2019-04-05x86: Support Intel AVX512 BF16Xuepeng Guo1-0/+3
Add assembler and disassembler support Intel AVX512 BF16: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference gas/ 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_bf16. (cpu_noarch): Add noavx512_bf16. * doc/c-i386.texi: Document avx512_bf16. * testsuite/gas/i386/avx512_bf16.d: New file. * testsuite/gas/i386/avx512_bf16.s: Likewise. * testsuite/gas/i386/avx512_bf16_vl-inval.l: Likewise. * testsuite/gas/i386/avx512_bf16_vl-inval.s: Likewise. * testsuite/gas/i386/avx512_bf16_vl.d: Likewise. * testsuite/gas/i386/avx512_bf16_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16.d: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l: Likesie. * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Likewise. * testsuite/gas/i386/i386.exp: Add BF16 related tests. opcodes/ 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> * i386-dis-evex.h (evex_table): Updated to support BF16 instructions. * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1 and EVEX_W_0F3872_P_3. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS. (cpu_flags): Add bitfield for CpuAVX512_BF16. * i386-opc.h (enum): Add CpuAVX512_BF16. (i386_cpu_flags): Add bitfield for cpuavx512_bf16. * i386-opc.tbl: Add AVX512 BF16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-11-06x86: correctly handle VMOVD with EVEX.W set outside of 64-bit modeJan Beulich1-2/+0
For the flavors having a GPR operand EVEX.W is ignored outside of 64-bit mode. The mnemonic should therefore not be KMOVQ, the GPR operand should not name a non-existing 64-bit register, just like is already the case for the AVX counterparts, and the Disp8 scaling factor should be 4 rather than 8.
2018-11-06x86: correctly handle KMOVD with VEX.W set outside of 64-bit modeJan Beulich1-32/+8
For the flavors having a GPR operand VEX.W is ignored outside of 64-bit mode. The mnemonic should therefore not be KMOVQ.
2018-11-06x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*Jan Beulich1-32/+12
PEXTR{B,W} and PINSR{B,W}, just like for AVX512BW, are WIG, no matter that the SDM uses a nonstandard description of that fact. PEXTRD, even with EVEX.W set, ignores that bit outside of 64-bit mode, just like its AVX counterpart.
2018-10-05x86: Add Intel ENCLV to assembler and disassemblerH.J. Lu1-1/+1
gas/ * testsuite/gas/i386/se1.s: Add enclv. * testsuite/gas/i386/x86-64-se1.s: Likewise. * testsuite/gas/i386/se1.d: Updated. * testsuite/gas/i386/x86-64-se1.d: Likewise. opcodes/ * i386-dis.c (rm_table): Add enclv. * i386-opc.tbl: Add enclv. * i386-tbl.h: Regenerated.
2018-09-17x86: Set EVex=2 on EVEX.128 only vmovd and vmovqH.J. Lu1-1/+40
EVEX "VMOVD xmm1, r32/m32", "VMOVD r32/m32, xmm2", "VMOVQ xmm1, r64/m64", "VMOVD r64/m64, xmm2", "VMOVQ xmm1, xmm2/m64" and "VMOVQ xmm1/m64, xmm2" can only be encoded with EVEX.128. Set EVex=2 on EVEX.128 only vmovd and vmovq. gas/ PR gas/23670 * testsuite/gas/i386/evex-lig-2.d: New file. * testsuite/gas/i386/evex-lig-2.s: Likewise. * testsuite/gas/i386/x86-64-evex-lig-2.d: Likewise. * testsuite/gas/i386/x86-64-evex-lig-2.s: Likewise. * testsuite/gas/i386/i386.exp: Run evex-lig-2 and x86-64-evex-lig-2. opcodes/ PR gas/23670 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2, EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2. (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry. (EVEX_LEN_0F7E_P_1): Likewise. (EVEX_LEN_0F7E_P_2): Likewise. (EVEX_LEN_0FD6_P_2): Likewise. * i386-dis.c (USE_EVEX_LEN_TABLE): New. (EVEX_LEN_TABLE): Likewise. (EVEX_LEN_0F6E_P_2): New enum. (EVEX_LEN_0F7E_P_1): Likewise. (EVEX_LEN_0F7E_P_2): Likewise. (EVEX_LEN_0FD6_P_2): Likewise. (evex_len_table): New. (get_valid_dis386): Handle USE_EVEX_LEN_TABLE. * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq. * i386-tbl.h: Regenerated.
2018-09-17x86: Set Vex=1 on VEX.128 only vmovd and vmovqH.J. Lu1-2/+0
AVX "VMOVD xmm1, r32/m32", "VMOVD r32/m32, xmm2", "VMOVQ xmm1, r64/m64" and "VMOVD r64/m64, xmm2" can only be encoded with VEX.128. Set Vex=1 on VEX.128 only vmovd and vmovq. gas/ PR gas/23665 * testsuite/gas/i386/avx-scalar.s: Remove vmovq and vmovd tests. * testsuite/gas/i386/x86-64-avx-scalar.s: Likewise. * testsuite/gas/i386/avx-scalar-intel.d: Updated. * testsuite/gas/i386/avx-scalar.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar.d: Likewise. * testsuite/gas/i386/i386.exp: Run avx-scalar2 and x86-64-avx-scalar2. * testsuite/gas/i386/avx-scalar-2.d: New file. * testsuite/gas/i386/avx-scalar-2.s: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-2.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-2.s: Likewise. opcodes/ PR gas/23665 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and VEX_LEN_0F7E_P_2 entries. * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq. * i386-tbl.h: Regenerated.
2018-09-17x86: Update disassembler for VexWIGH.J. Lu1-1563/+232
The VEX.W bit is ignored by some VEX instructions, aka WIG instructions. Update x86 disassembler to handle VEX WIG instructions. * i386-dis.c (VZERO_Fixup): Removed. (VZERO): Likewise. (VEX_LEN_0F10_P_1): Likewise. (VEX_LEN_0F10_P_3): Likewise. (VEX_LEN_0F11_P_1): Likewise. (VEX_LEN_0F11_P_3): Likewise. (VEX_LEN_0F2E_P_0): Likewise. (VEX_LEN_0F2E_P_2): Likewise. (VEX_LEN_0F2F_P_0): Likewise. (VEX_LEN_0F2F_P_2): Likewise. (VEX_LEN_0F51_P_1): Likewise. (VEX_LEN_0F51_P_3): Likewise. (VEX_LEN_0F52_P_1): Likewise. (VEX_LEN_0F53_P_1): Likewise. (VEX_LEN_0F58_P_1): Likewise. (VEX_LEN_0F58_P_3): Likewise. (VEX_LEN_0F59_P_1): Likewise. (VEX_LEN_0F59_P_3): Likewise. (VEX_LEN_0F5A_P_1): Likewise. (VEX_LEN_0F5A_P_3): Likewise. (VEX_LEN_0F5C_P_1): Likewise. (VEX_LEN_0F5C_P_3): Likewise. (VEX_LEN_0F5D_P_1): Likewise. (VEX_LEN_0F5D_P_3): Likewise. (VEX_LEN_0F5E_P_1): Likewise. (VEX_LEN_0F5E_P_3): Likewise. (VEX_LEN_0F5F_P_1): Likewise. (VEX_LEN_0F5F_P_3): Likewise. (VEX_LEN_0FC2_P_1): Likewise. (VEX_LEN_0FC2_P_3): Likewise. (VEX_LEN_0F3A0A_P_2): Likewise. (VEX_LEN_0F3A0B_P_2): Likewise. (VEX_W_0F10_P_0): Likewise. (VEX_W_0F10_P_1): Likewise. (VEX_W_0F10_P_2): Likewise. (VEX_W_0F10_P_3): Likewise. (VEX_W_0F11_P_0): Likewise. (VEX_W_0F11_P_1): Likewise. (VEX_W_0F11_P_2): Likewise. (VEX_W_0F11_P_3): Likewise. (VEX_W_0F12_P_0_M_0): Likewise. (VEX_W_0F12_P_0_M_1): Likewise. (VEX_W_0F12_P_1): Likewise. (VEX_W_0F12_P_2): Likewise. (VEX_W_0F12_P_3): Likewise. (VEX_W_0F13_M_0): Likewise. (VEX_W_0F14): Likewise. (VEX_W_0F15): Likewise. (VEX_W_0F16_P_0_M_0): Likewise. (VEX_W_0F16_P_0_M_1): Likewise. (VEX_W_0F16_P_1): Likewise. (VEX_W_0F16_P_2): Likewise. (VEX_W_0F17_M_0): Likewise. (VEX_W_0F28): Likewise. (VEX_W_0F29): Likewise. (VEX_W_0F2B_M_0): Likewise. (VEX_W_0F2E_P_0): Likewise. (VEX_W_0F2E_P_2): Likewise. (VEX_W_0F2F_P_0): Likewise. (VEX_W_0F2F_P_2): Likewise. (VEX_W_0F50_M_0): Likewise. (VEX_W_0F51_P_0): Likewise. (VEX_W_0F51_P_1): Likewise. (VEX_W_0F51_P_2): Likewise. (VEX_W_0F51_P_3): Likewise. (VEX_W_0F52_P_0): Likewise. (VEX_W_0F52_P_1): Likewise. (VEX_W_0F53_P_0): Likewise. (VEX_W_0F53_P_1): Likewise. (VEX_W_0F58_P_0): Likewise. (VEX_W_0F58_P_1): Likewise. (VEX_W_0F58_P_2): Likewise. (VEX_W_0F58_P_3): Likewise. (VEX_W_0F59_P_0): Likewise. (VEX_W_0F59_P_1): Likewise. (VEX_W_0F59_P_2): Likewise. (VEX_W_0F59_P_3): Likewise. (VEX_W_0F5A_P_0): Likewise. (VEX_W_0F5A_P_1): Likewise. (VEX_W_0F5A_P_3): Likewise. (VEX_W_0F5B_P_0): Likewise. (VEX_W_0F5B_P_1): Likewise. (VEX_W_0F5B_P_2): Likewise. (VEX_W_0F5C_P_0): Likewise. (VEX_W_0F5C_P_1): Likewise. (VEX_W_0F5C_P_2): Likewise. (VEX_W_0F5C_P_3): Likewise. (VEX_W_0F5D_P_0): Likewise. (VEX_W_0F5D_P_1): Likewise. (VEX_W_0F5D_P_2): Likewise. (VEX_W_0F5D_P_3): Likewise. (VEX_W_0F5E_P_0): Likewise. (VEX_W_0F5E_P_1): Likewise. (VEX_W_0F5E_P_2): Likewise. (VEX_W_0F5E_P_3): Likewise. (VEX_W_0F5F_P_0): Likewise. (VEX_W_0F5F_P_1): Likewise. (VEX_W_0F5F_P_2): Likewise. (VEX_W_0F5F_P_3): Likewise. (VEX_W_0F60_P_2): Likewise. (VEX_W_0F61_P_2): Likewise. (VEX_W_0F62_P_2): Likewise. (VEX_W_0F63_P_2): Likewise. (VEX_W_0F64_P_2): Likewise. (VEX_W_0F65_P_2): Likewise. (VEX_W_0F66_P_2): Likewise. (VEX_W_0F67_P_2): Likewise. (VEX_W_0F68_P_2): Likewise. (VEX_W_0F69_P_2): Likewise. (VEX_W_0F6A_P_2): Likewise. (VEX_W_0F6B_P_2): Likewise. (VEX_W_0F6C_P_2): Likewise. (VEX_W_0F6D_P_2): Likewise. (VEX_W_0F6F_P_1): Likewise. (VEX_W_0F6F_P_2): Likewise. (VEX_W_0F70_P_1): Likewise. (VEX_W_0F70_P_2): Likewise. (VEX_W_0F70_P_3): Likewise. (VEX_W_0F71_R_2_P_2): Likewise. (VEX_W_0F71_R_4_P_2): Likewise. (VEX_W_0F71_R_6_P_2): Likewise. (VEX_W_0F72_R_2_P_2): Likewise. (VEX_W_0F72_R_4_P_2): Likewise. (VEX_W_0F72_R_6_P_2): Likewise. (VEX_W_0F73_R_2_P_2): Likewise. (VEX_W_0F73_R_3_P_2): Likewise. (VEX_W_0F73_R_6_P_2): Likewise. (VEX_W_0F73_R_7_P_2): Likewise. (VEX_W_0F74_P_2): Likewise. (VEX_W_0F75_P_2): Likewise. (VEX_W_0F76_P_2): Likewise. (VEX_W_0F77_P_0): Likewise. (VEX_W_0F7C_P_2): Likewise. (VEX_W_0F7C_P_3): Likewise. (VEX_W_0F7D_P_2): Likewise. (VEX_W_0F7D_P_3): Likewise. (VEX_W_0F7E_P_1): Likewise. (VEX_W_0F7F_P_1): Likewise. (VEX_W_0F7F_P_2): Likewise. (VEX_W_0FAE_R_2_M_0): Likewise. (VEX_W_0FAE_R_3_M_0): Likewise. (VEX_W_0FC2_P_0): Likewise. (VEX_W_0FC2_P_1): Likewise. (VEX_W_0FC2_P_2): Likewise. (VEX_W_0FC2_P_3): Likewise. (VEX_W_0FD0_P_2): Likewise. (VEX_W_0FD0_P_3): Likewise. (VEX_W_0FD1_P_2): Likewise. (VEX_W_0FD2_P_2): Likewise. (VEX_W_0FD3_P_2): Likewise. (VEX_W_0FD4_P_2): Likewise. (VEX_W_0FD5_P_2): Likewise. (VEX_W_0FD6_P_2): Likewise. (VEX_W_0FD7_P_2_M_1): Likewise. (VEX_W_0FD8_P_2): Likewise. (VEX_W_0FD9_P_2): Likewise. (VEX_W_0FDA_P_2): Likewise. (VEX_W_0FDB_P_2): Likewise. (VEX_W_0FDC_P_2): Likewise. (VEX_W_0FDD_P_2): Likewise. (VEX_W_0FDE_P_2): Likewise. (VEX_W_0FDF_P_2): Likewise. (VEX_W_0FE0_P_2): Likewise. (VEX_W_0FE1_P_2): Likewise. (VEX_W_0FE2_P_2): Likewise. (VEX_W_0FE3_P_2): Likewise. (VEX_W_0FE4_P_2): Likewise. (VEX_W_0FE5_P_2): Likewise. (VEX_W_0FE6_P_1): Likewise. (VEX_W_0FE6_P_2): Likewise. (VEX_W_0FE6_P_3): Likewise. (VEX_W_0FE7_P_2_M_0): Likewise. (VEX_W_0FE8_P_2): Likewise. (VEX_W_0FE9_P_2): Likewise. (VEX_W_0FEA_P_2): Likewise. (VEX_W_0FEB_P_2): Likewise. (VEX_W_0FEC_P_2): Likewise. (VEX_W_0FED_P_2): Likewise. (VEX_W_0FEE_P_2): Likewise. (VEX_W_0FEF_P_2): Likewise. (VEX_W_0FF0_P_3_M_0): Likewise. (VEX_W_0FF1_P_2): Likewise. (VEX_W_0FF2_P_2): Likewise. (VEX_W_0FF3_P_2): Likewise. (VEX_W_0FF4_P_2): Likewise. (VEX_W_0FF5_P_2): Likewise. (VEX_W_0FF6_P_2): Likewise. (VEX_W_0FF7_P_2): Likewise. (VEX_W_0FF8_P_2): Likewise. (VEX_W_0FF9_P_2): Likewise. (VEX_W_0FFA_P_2): Likewise. (VEX_W_0FFB_P_2): Likewise. (VEX_W_0FFC_P_2): Likewise. (VEX_W_0FFD_P_2): Likewise. (VEX_W_0FFE_P_2): Likewise. (VEX_W_0F3800_P_2): Likewise. (VEX_W_0F3801_P_2): Likewise. (VEX_W_0F3802_P_2): Likewise. (VEX_W_0F3803_P_2): Likewise. (VEX_W_0F3804_P_2): Likewise. (VEX_W_0F3805_P_2): Likewise. (VEX_W_0F3806_P_2): Likewise. (VEX_W_0F3807_P_2): Likewise. (VEX_W_0F3808_P_2): Likewise. (VEX_W_0F3809_P_2): Likewise. (VEX_W_0F380A_P_2): Likewise. (VEX_W_0F380B_P_2): Likewise. (VEX_W_0F3817_P_2): Likewise. (VEX_W_0F381C_P_2): Likewise. (VEX_W_0F381D_P_2): Likewise. (VEX_W_0F381E_P_2): Likewise. (VEX_W_0F3820_P_2): Likewise. (VEX_W_0F3821_P_2): Likewise. (VEX_W_0F3822_P_2): Likewise. (VEX_W_0F3823_P_2): Likewise. (VEX_W_0F3824_P_2): Likewise. (VEX_W_0F3825_P_2): Likewise. (VEX_W_0F3828_P_2): Likewise. (VEX_W_0F3829_P_2): Likewise. (VEX_W_0F382A_P_2_M_0): Likewise. (VEX_W_0F382B_P_2): Likewise. (VEX_W_0F3830_P_2): Likewise. (VEX_W_0F3831_P_2): Likewise. (VEX_W_0F3832_P_2): Likewise. (VEX_W_0F3833_P_2): Likewise. (VEX_W_0F3834_P_2): Likewise. (VEX_W_0F3835_P_2): Likewise. (VEX_W_0F3837_P_2): Likewise. (VEX_W_0F3838_P_2): Likewise. (VEX_W_0F3839_P_2): Likewise. (VEX_W_0F383A_P_2): Likewise. (VEX_W_0F383B_P_2): Likewise. (VEX_W_0F383C_P_2): Likewise. (VEX_W_0F383D_P_2): Likewise. (VEX_W_0F383E_P_2): Likewise. (VEX_W_0F383F_P_2): Likewise. (VEX_W_0F3840_P_2): Likewise. (VEX_W_0F3841_P_2): Likewise. (VEX_W_0F38DB_P_2): Likewise. (VEX_W_0F3A08_P_2): Likewise. (VEX_W_0F3A09_P_2): Likewise. (VEX_W_0F3A0A_P_2): Likewise. (VEX_W_0F3A0B_P_2): Likewise. (VEX_W_0F3A0C_P_2): Likewise. (VEX_W_0F3A0D_P_2): Likewise. (VEX_W_0F3A0E_P_2): Likewise. (VEX_W_0F3A0F_P_2): Likewise. (VEX_W_0F3A21_P_2): Likewise. (VEX_W_0F3A40_P_2): Likewise. (VEX_W_0F3A41_P_2): Likewise. (VEX_W_0F3A42_P_2): Likewise. (VEX_W_0F3A62_P_2): Likewise. (VEX_W_0F3A63_P_2): Likewise. (VEX_W_0F3ADF_P_2): Likewise. (VEX_LEN_0F77_P_0): New. (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11, PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E, PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52, PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59, PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C, PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F, PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F, PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4, PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2, PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6, PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C, PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2, PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2, PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5, PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE, PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1, PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4, PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8, PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB, PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE, PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2, PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5, PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832, PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries. (vex_table): Update VEX 0F28 and 0F29 entries. (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3, VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0, VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2, VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1, VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3, VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1, VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3, VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1, VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3, VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and VEX_LEN_0F3A0B_P_2 entries. (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1, VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1, VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0, VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2, VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15, VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1, VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29, VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0, VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1, VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1, VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1, VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1, VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1, VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2, VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3, VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3, VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3, VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3, VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2, VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2, VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2, VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2, VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3, VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2, VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2, VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2, VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2, VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3, VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1, VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0, VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3, VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2, VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2, VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2, VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2, VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2, VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2, VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3, VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2, VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2, VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0, VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2, VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2, VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2, VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2, VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2, VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2, VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2, VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2, VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2, VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2, VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2, VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0, VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2, VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2, VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2, VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2, VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2, VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2, VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2, VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2, VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2, VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2, VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and VEX_W_0F3ADF_P_2 entries. (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50, MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2, MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
2018-09-15x86: Set Vex=1 on VEX.128 only vmovqH.J. Lu1-2/+0
AVX "VMOVQ xmm1, xmm2/m64" and "VMOVQ xmm1/m64, xmm2" can only be encoded with VEX.128. Set Vex=1 on VEX.128 only vmovq and update assembler tests. gas/ PR gas/23665 * testsuite/gas/i386/avx-scalar-intel.d: Updated. * testsuite/gas/i386/avx-scalar.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar.d: Likewise. opcodes/ PR gas/23665 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and VEX_LEN_0FD6_P_2 entries. * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq. * i386-tbl.h: Regenerated.
2018-09-14x86: Handle unsupported static rounding in vcvt[u]si2sd in 32-bit modeH.J. Lu1-0/+11
Update x86 disassembler to handle the unsupported static rounding in vcvt[u]si2sd in 32-bit mode. gas/ PR binutils/23655 * testsuite/gas/i386/evex.d: Updated. opcodes/ PR binutils/23655 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for vcvtsi2sd%LQ and vcvtusi2sd%LQ. * i386-dis.c (EXxEVexR64): New. (evex_rounding_64_mode): Likewise. (OP_Rounding): Handle evex_rounding_64_mode.
2018-09-14x86: Properly decode EVEX.W in vcvt[u]si2s[sd] in 32-bit modeH.J. Lu1-0/+8
Update x86 disassembler to ignore the EVEX.W bit in EVEX vcvt[u]si2s[sd] instructions in 32-bit mode. gas/ PR binutils/23655 * testsuite/gas/i386/evex.d: New file. * testsuite/gas/i386/evex.s: Likewise. * testsuite/gas/i386/i386.exp: Run evex. opcodes/ PR binutils/23655 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ. * i386-dis.c (Edqa): New. (dqa_mode): Likewise. (intel_operand_size): Handle dqa_mode as m_mode. (OP_E_register): Handle dqa_mode as dq_mode. (OP_E_memory): Set shift for dqa_mode based on address_mode.
2018-09-14i386: Reformat OP_E_memoryH.J. Lu1-2/+2
* i386-dis.c (OP_E_memory): Reformat.
2018-09-13x86-64: bndmk, bndldx, and bndstx don't allow RIP-relative addressingJan Beulich1-3/+14
2018-08-14x86-64: Display eiz for address with the addr32 prefixH.J. Lu1-7/+23
In 64-bit mode, display eiz for address with the addr32 prefix and without base nor index registers. For mov -0xccddef(,%eiz,), %rax disassembler now displays: 67 48 8b 04 25 11 22 33 ff mov -0xccddef(,%eiz,1),%rax instead of 67 48 8b 04 25 11 22 33 ff addr32 mov 0xffffffffff332211,%rax gas/ * testsuite/gas/i386/evex-no-scale-64.d: Updated. * testsuite/gas/i386/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/x86-64-addr32.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-addr32.d: Likewise. * testsuite/gas/i386/x86-64-addr32.s: Add %eiz tests. opcodes/ * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for address with the addr32 prefix and without base nor index registers.
2018-05-07Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu1-2/+46
gas/ * config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b. (cpu_noarch): Likewise. (process_suffix): Add check for register size. * doc/c-i386.texi: Document movdiri, movdir64b. * testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests. * testsuite/gas/i386/movdir-intel.d: New file. * testsuite/gas/i386/movdir.d: Likewise. * testsuite/gas/i386/movdir.s: Likewise. * testsuite/gas/i386/movdir64b-reg.s: Likewise. * testsuite/gas/i386/movdir64b-reg.l: Likewise. * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise. * testsuite/gas/i386/x86-64-movdir.d: Likewise. * testsuite/gas/i386/x86-64-movdir.s: Likewise. * testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise. * testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise. opcodes/ * i386-dis.c (Gva): New. (enum): Add PREFIX_0F38F8, PREFIX_0F38F9, MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0. (prefix_table): New instructions (see prefix above). (mod_table): New instructions (see prefix above). (OP_G): Handle va_mode. * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS, CPU_MOVDIR64B_FLAGS. (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B. * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B. (i386_cpu_flags): Add cpumovdiri and cpumovdir64b. * i386-opc.tbl: Add movidir{i,64b}. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2018-04-27Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist1-50/+4
This reverts commit a914a7c95895161c99533d5919b8504b37ea54a0.
2018-04-26Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist1-4/+50
gas/ * config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b. (cpu_noarch): Likewise. (process_suffix): Add check for register size. * doc/c-i386.texi: Document movdiri, movdir64b. * testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests. * testsuite/gas/i386/movdir-intel.d: New test. * testsuite/gas/i386/movdir.d: Likewise. * testsuite/gas/i386/movdir.s: Likewise. * testsuite/gas/i386/movdir64b-reg.s: Likewise. * testsuite/gas/i386/movdir64b-reg.l: Likewise. * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise. * testsuite/gas/i386/x86-64-movdir.d: Likewise. * testsuite/gas/i386/x86-64-movdir.s: Likewise. * testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise. * testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F38F8, PREFIX_0F38F9. (prefix_table): New instructions (see prefix above). Add Gva macro and handling in OP_G. * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS, CPU_MOVDIR64B_FLAGS. (cpu_flags): Likewise. (opcode_modifiers): Add AddrPrefixOpReg. (i386_opcode_modifier): Likewise. * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B. (i386_cpu_flags): Likewise. * i386-opc.tbl: Add movidir{i,64b}. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-04-17Enable Intel CLDEMOTE instruction.Igor Tsimbalist1-1/+28
gas/ * config/tc-i386.c (cpu_arch): Add .cldemote. * doc/c-i386.texi: Document cldemote/.cldemote. * testsuite/gas/i386/cldemote-intel.d: New. * testsuite/gas/i386/cldemote.d: Likewise. * testsuite/gas/i386/cldemote.s: Likewise. * testsuite/gas/i386/i386.exp: Run new tests. * testsuite/gas/i386/x86-64-cldemote-intel.d: New. * testsuite/gas/i386/x86-64-cldemote.d: Likewise. * testsuite/gas/i386/x86-64-cldemote.s: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops.d: Remove 0x0f1c NOP encoding that maps to cldemote. * testsuite/gas/i386/nops.d: Likewise. * testsuite/gas/i386/nops.s: Likewise. * testsuite/gas/i386/x86-64-nops.d: Likewise. * testsuite/gas/i386/x86-64-nops.s: Likewise. opcode/ * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0, PREFIX_0F1C. * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS, (cpu_flags): Add CpuCLDEMOTE. * i386-init.h: Regenerate. * i386-opc.h (enum): Add CpuCLDEMOTE, (i386_cpu_flags): Add cpucldemote. * i386-opc.tbl: Add cldemote. * i386-tbl.h: Regenerate.
2018-04-15x86: Allow 32-bit registers for tpause and umwaitH.J. Lu1-2/+2
Since only the first 32 bits of input operand are used for tpause and umwait, the REX.W bit is skipped. Both 32-bit registers and 64-bit registers are allowed. gas/ * testsuite/gas/i386/x86-64-waitpkg.s: Add 32-bit registers tests for tpause and umwait. * testsuite/gas/i386/x86-64-waitpkg-intel.d: Updated. * testsuite/gas/i386/x86-64-waitpkg.d: Likewise. opcodes/ * i386-dis.c (prefix_table): Replace Em with Edq on tpause and umwait. * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in 64-bit mode. * i386-tbl.h: Regenerated.
generated by cgit v1.1 at 2025-01-02 07:12:14 +0000