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path: root/opcodes/i386-dis.c
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2015-12-09Implement Intel OSPKE instructionsH.J. Lu1-1/+19
2015-08-24Fix the partial disassembly of a broken three byte instruction at the end of ...Jan Stancek1-2/+4
2015-08-21PR binutils/18257: Properly decode x86/Intel mask instructions.Alexander Fomin1-59/+413
2015-07-30Properly disassemble movnti in Intel modeH.J. Lu1-5/+10
2015-07-23Fix ubsan signed integer overflowAlan Modra1-2/+2
2015-06-30Add support for monitorx/mwaitx instructionsAmit Pawar1-2/+22
2015-06-01x86/Intel: disassemble vcvt{,u}si2s{d,s} with correct operand orderJan Beulich1-0/+7
2015-05-15Support AMD64/Intel ISAs in assembler/disassemblerH.J. Lu1-5/+40
2015-05-09Ignore 0x66 prefix for call/jmp/jcc in 64-bit modeH.J. Lu1-10/+40
2015-04-23x86: disambiguate disassembly of certain AVX512 insnsJan Beulich1-4/+36
2015-04-15Remove the unused PREFIX_UD_XXXH.J. Lu1-6/+0
2015-04-15Check dp->prefix_requirement insteadH.J. Lu1-5/+1
2015-04-15Handle invalid prefixes for rdrand and rdseedH.J. Lu1-5/+21
2015-04-15Replace mandatory_prefix with prefix_requirementH.J. Lu1-310/+315
2015-04-06x86: Use individual prefix control for each opcode.Ilya Tocar1-1442/+1440
2015-03-17Add znver1 processorGanesh Gopalasubramanian1-0/+3
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-11-17Add AVX512VBMI instructionsIlya Tocar1-0/+2
2014-11-17Add AVX512IFMA instructionsIlya Tocar1-0/+2
2014-11-17Add pcommit instructionIlya Tocar1-1/+9
2014-11-17Add clwb instructionIlya Tocar1-1/+9
2014-09-22Ignore MOD field for control/debug register moveH.J. Lu1-32/+8
2014-09-10Properly handle suffix for iret and sysretH.J. Lu1-21/+54
2014-07-22Add AVX512DQ instructions and their AVX512VL variants.Ilya Tocar1-21/+81
2014-07-22Add support for AVX512BW instructions and their AVX512VL versions.Ilya Tocar1-17/+437
2014-07-22Add support for AVX512VL. Add AVX512VL versions of AVX512F instructions.Ilya Tocar1-7/+63
2014-06-10Only print prefixes before fwaitH.J. Lu1-2/+4
2014-05-09Properly display extra data/address size prefixesH.J. Lu1-55/+13
2014-05-05Properly handle multiple opcode prefixesH.J. Lu1-114/+135
2014-05-02Use sigsetjmp/siglongjmp in opcodesH.J. Lu1-3/+3
2014-05-01Handle prefixes before fwaitH.J. Lu1-1/+7
2014-04-04Add support for Intel SGX instructionsIlya Tocar1-1/+5
2014-03-20Fix memory size for gather/scatter instructionsIlya Tocar1-3/+29
2014-03-05Update copyright yearsAlan Modra1-3/+1
2014-02-12Add clflushopt, xsaves, xsavec, xrstorsIlya Tocar1-4/+27
2014-01-30Fix shift for AVX512F gather/scatter instructionsMichael Zolotukhin1-3/+1
2014-01-09Fix buffer underrun in i386-dis.c.Roland McGrath1-1/+1
2013-12-17Properly handle ljmp/lcall with invalid MODRM byteMichael Zolotukhin1-2/+12
2013-10-12Only allow 32-bit/64-bit registers for bndcl/bndcu/bndcnH.J. Lu1-2/+2
2013-10-11opcodes/Roland McGrath1-20/+28
2013-08-19Remove PREFIX_EVEX_0F3A3E and PREFIX_EVEX_0F3A3FH.J. Lu1-2/+0
2013-07-26Add Intel AVX-512 supportH.J. Lu1-31/+1306
2013-07-25Support Intel SHAH.J. Lu1-7/+49
2013-07-24Support Intel MPXH.J. Lu1-47/+126
2013-03-27Properly check address mode for SIBH.J. Lu1-4/+4
2013-02-19Implement Intel SMAP instructionsH.J. Lu1-0/+2
2012-10-24gas/testsuite/Roland McGrath1-58/+61
2012-08-07gas/testsuite/Roland McGrath1-0/+30
2012-08-06gas/testsuite/Roland McGrath1-6/+12
2012-08-06gas/testsuite/Roland McGrath1-30/+34
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