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2020-07-14x86: drop Rdq, Rd, and MaskRJan Beulich1-4/+4
Rdq, Rd, and MaskR can be replaced by Edq, Ed / Rm, and MaskE respectively, as OP_R() doesn't enforce ModRM.mod == 3, and hence where MOD matters but hasn't been decoded yet it needs to be anyway. (The case of converting to Rm is temporary until a subsequent change.)
2020-07-14x86: simplify decode of opcodes valid with (embedded) 66 prefix onlyJan Beulich1-134/+134
The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14x86: drop need_vex_regJan Beulich1-5/+5
It was quite odd for the prior operand handling to have to clear this flag for the actual operand handling to print nothing. Have the actual operand handling determine whether the operand is actually present. With this {d,q}_scalar_swap_mode become unused and hence also get dropped.
2020-07-14x86: extend %BW use to VP{COMPRESS,EXPAND}{B,W}Jan Beulich1-10/+0
Unlike the earlier ones these also need their operands adjusted. Replace the (mis-described: there's nothing "scalar" here) {b,w}_scalar_mode by a single new mode, with the actual unit width controlled by EVEX.W.
2020-07-14x86-64: fix {,V}PCMPESTR{I,M} disassembly in Intel modeJan Beulich1-4/+4
The operands don't allow disambiguating the insn in 64-bit mode, and hence suffixes need to be emitted not just in AT&T mode. Achieve this by re-using %LQ while dropping PCMPESTR_Fixup().
2020-07-14x86: fold VCMP_Fixup() into CMP_Fixup()Jan Beulich1-2/+2
There's no reason to have two functions and two tables, when the AVX functionality here is a proper superset of the SSE one.
2020-07-07x86: introduce %BW to avoid going through vex_w_table[]Jan Beulich1-55/+0
This parallels %LW and %XW.
2020-07-06x86: use %LW / %XW instead of going through vex_w_table[]Jan Beulich1-75/+0
Since we have these macros, there's no point having unnecessary table depth. VFPCLASSP{S,D} are now the first instance of using two %-prefixed macros, which has pointed out a problem with the implementation. Instead of using custom code in various case blocks, do the macro accumulation centralized at the top of the main loop of putop(), and zap the accumulated macros at the bottom of that loop once it has been processed.
2020-07-06x86: most VBROADCAST{F,I}{32,64}x* only accept memory operandsJan Beulich1-8/+8
VBROADCAST{F,I}32x2 are the only exceptions here.
2020-07-06x86: drop EVEX table entries that can be made served by VEX onesJan Beulich1-30/+30
By doing the EVEX.W decode first, in various cases VEX table entries can be re-used.
2020-07-06x86: AVX512 VPERM{D,Q,PS,PD} insns need to honor EVEX.L'LJan Beulich1-2/+2
Just like (where they exist) their AVX counterparts do for VEX.L. For all of them the 128-bit forms are invalid.
2020-07-06x86: AVX512 extract/insert insns need to honor EVEX.L'LJan Beulich1-1/+1
Just like their AVX counterparts do for VEX.L. At this occasion also make EVEX.W have the same effect as VEX.W on the printing of VPINSR{B,W}'s operands, bringing them also in sync with VPEXTR{B,W}.
2020-07-06x86: honor VEX.W for VCVT{PH2PS,PS2PH}Jan Beulich1-4/+0
Unlike for the EVEX-encoded versions, the VEX ones failed to decode VEX.W. Once the necessary adjustments are done, it becomes obvious that the EVEX and VEX table entries for VCVTPS2PH are identical and can hence be folded.
2020-07-06x86: drop EVEX table entries that can be served by VEX onesJan Beulich1-34/+0
The duplication is not only space inefficient, but also risks entries going out of sync (some of which that I became aware of while doing this work will get addressed subsequently). Right here note that for VGF2P8MULB this also addresses the prior lack of EVEX.W decoding (i.e. a first example of out of sync entries). This introduces EXxEVexR to some VEX templates, on the basis that this operand is benign there and only relevant when EVEX encoding ends up reaching these entries.
2020-07-06x86: replace EXqScalarS by EXqVexScalarSJan Beulich1-1/+1
There's only a single user, that that one can do fine with the alternative, as the "Vex" aspect of the other operand kind is meaningful only on 3-operand insns. While doing this I noticed that I didn't need to do the same adjustment in the EVEX tables, and voilà - there was a bug, which gets fixed at the same time (see the testsuite changes).
2020-07-06x86: replace EX{d,q}Scalar by EXxmm_m{d,q}Jan Beulich1-2/+2
Along the lines of 4102be5cf925 ("x86: replace EXxmm_mdq by EXVexWdqScalar"), but in the opposite direction, replace EXdScalar/ EXqScalar by EXxmm_md/EXxmm_mq respectively, rendering d_scalar_mode and q_scalar_mode unused. The change is done this way to improve telling apart operands affected here from ones using EXbScalar/EXwScalar, which work sufficiently differently. Additionally this increases similarity between several VEX-encoded insns and their EVEX-encoded counterparts.
2020-06-09x86: utilize X macro in EVEX decodingJan Beulich1-234/+0
For major opcodes allowing only packed FP kinds of operands, i.e. the ones where legacy and AVX decoding uses the X macro, we can do so for AVX512 as well, by attaching to the checking logic the "EVEX.W must match presence of embedded 66 prefix" rule. (Encodings not following this general pattern simply may not gain the PREFIX_OPCODE attribute.) Note that testing of the thus altered decoding has already been put in place by "x86: correct decoding of packed-FP-only AVX encodings". This can also be at least partly applied to scalar-FP-only insns (i.e. V{,U}COMIS{S,D}) as well as the vector-FP forms of insns also allowing scalar encodings (e.g. VADDP{S,D}). Take the opportunity and also fix EVEX-encoded VMOVNTP{S,D} as well as to-memory forms of VMOV{L,H}PS and both forms of VMOV{L,H}PD to wrongly disassemble with only register operands.
2019-07-01x86: remove ModRM.mod decoding layer from AVX512F VMOVS{S,D}Jan Beulich1-26/+8
Just like their AVX counterparts they can utilize XMVexScalar / EXdVexScalarS / EXqVexScalarS taking care of dropping the middle operand for their memory forms.
2019-06-27i386: Check vector length for scatter/gather prefetch instructionsH.J. Lu1-8/+8
Since not all vector lengths are supported by scatter/gather prefetch instructions, decode them only with supported vector lengths. gas/ PR binutils/24719 * testsuite/gas/i386/disassem.s: Add test for vgatherpf0dps with invalid vector length. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24719 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and EVEX_LEN_0F38C7_R_6_P_2_W_1. * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and PREFIX_EVEX_0F38C6_REG_6 entries. * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and EVEX_W_0F38C7_R_6_P_2 entries. * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
2019-06-25x86: drop dqa_modeJan Beulich1-12/+2
I assume this mode was needed when EVEX.W handling wasn't really correct yet for other than 64-bit mode. It's clearly not needed anymore. Its elimination also allows dropping the EVEX.W split of VCVT{,U}SI2SS. (For the record, the dropped mode would have been wrong if used in any table entry not already guaranteeing EVEX.W=1.)
2019-06-21i386: Break i386-dis-evex.h into small filesH.J. Lu1-0/+1138
Break i386-dis-evex.h into small files such that each file is included just once. * i386-dis-evex.h: Break into ... * i386-dis-evex-len.h: New file. * i386-dis-evex-mod.h: Likewise. * i386-dis-evex-prefix.h: Likewise. * i386-dis-evex-reg.h: Likewise. * i386-dis-evex-w.h: Likewise. * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h, i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and i386-dis-evex-mod.h.
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