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2024-04-17Add W table for USER_MSR under MAP4.Hu, Lin11-2/+2
opcodes/ChangeLog: * i386-dis-evex-mod.h: Modify MOD_EVEX_MAP4_F8_P1, MOD_EVEX_MAP4_F8_P3. * i386-dis-evex-w.h (EVEX_W_MAP4_F8_P1_M_1): New. (EVEX_W_MAP4_F8_P3_M_1): Ditto. * i386-dis.c (vex_w_table): Add EVEX_W_MAP4_F8_P1_M_1, EVEX_W_MAP4_F8_P3_M_1. * i386-opc.tbl: Remove redundant '|'.
2024-01-19x86: support APX forms of U{RD,WR}MSRJan Beulich1-1/+10
This was missed in 6177c84d5edc ("Support APX GPR32 with extend evex prefix").
2023-08-02Revert "2.41 Release sources"Sam James1-59/+1
This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton1-1/+59
2023-07-11x86: misc further register-only insns don't need to go through mod_table[]Jan Beulich1-15/+1
Several already use OP_R(), which rejects the memory forms of insns, and a few others can easily be converted to do so as well. Note that for it to be able to use BadOp() without forward declaration, OP_Skip_MODRM() is moved down. While there add the previously missing PREFIX_OPCODE to legacy opcode 0FD7.
2023-07-11x86: various operations on mask registers can avoid going through mod_table[]Jan Beulich1-20/+0
Now that we have OP_R(), use it here as well, while wiring memory-only operands to OP_M() at the same time. To keep the number of consumed opcode bytes similar to before, make BadOp() also account for VEX/XOP/ EVEX prefix bytes. To keep that change simple, convert need_vex to an actual count of prefix bytes (keeping intact all prior boolean uses of the field). Note how this improves disassembly of such bad encodings, by at least leaving a hint towards what a "nearby" instruction is. (For KSHIFT* change the immediates test testcases use, such that disassembly remains sufficiently in sync.) While there also use Ux for VPMOV{B,W,D,Q}2M, where decoding through mod_table[] was missing in the earlier scheme.
2023-07-11x86: misc further memory-only insns don't need to go through mod_table[]Jan Beulich1-24/+0
Several already use OP_M(), which rejects the register forms of insns, and a few others can easily be converted to do so as well. (Note that FXSAVE_Fixup() wires through to OP_M(). Note further that OP_IndirE(), which wasn't placed very well anyway, is moved down to avoid the need to forward-declare BadOp().) Also adjust formatting of and drop PREFIX_OPCODE from a few adjacent entries.
2023-07-04x86: flag bad EVEX masking for miscellaneous insnsJan Beulich1-4/+4
Masking is not permitted for certain further insns, not falling in any of the earlier categories. Introduce the Y macro (not expanding to any output) to flag such cases. Note that in a few cases entries already covered otherwise are converted as well, to continue to allow sharing of the string literals.
2022-01-14x86: share yet more VEX table entries with EVEX decodingJan Beulich1-30/+0
On top of prior similar work more opportunities have appeared in the meantime. Note that this also happens to address the prior lack of decoding of EVEX.L'L for VMOV{L,H}P{S,D} and VMOV{LH,HL}PS.
2022-01-14x86: reduce AVX512 FP set of insns decoded through vex_w_table[]Jan Beulich1-2/+2
Like for AVX512-FP16, there's not that many FP insns where going through this table is easier / cheaper than using suitable macros. Utilize %XS and %XD more to eliminate a fair number of table entries. While doing this I noticed a few anomalies. Where lines get touched / moved anyway, these are being addressed right here: - vmovshdup used EXx for its 2nd operand, thus displaying seemingly valid broadcast when EVEX.b is set with a memory operand; use EXEvexXNoBcst instead just like vmovsldup already does - vmovlhps used EXx for its 3rd operand, when all sibling entries use EXq; switch to EXq there for consistency (the two differ only for memory operands)
2021-07-22x86: drop xmm_m{b,w,d,q}_modeJan Beulich1-6/+6
They're effectively redundant with {b,w,d,q}_mode.
2021-03-10x86: re-arrange order of decode for various EVEX opcodesJan Beulich1-52/+12
The order of decodes influences the overall number of table entries. Reduce table size quite a bit by first decoding few-alternatives attributes common to all valid leaves. This also adds a PREFIX_DATA 7531c61332db ("x86: simplify decode of opcodes valid with (embedded) 66 prefix only") missed to apply to vbroadcastf64x4.
2020-07-14x86: drop Rdq, Rd, and MaskRJan Beulich1-0/+35
Rdq, Rd, and MaskR can be replaced by Edq, Ed / Rm, and MaskE respectively, as OP_R() doesn't enforce ModRM.mod == 3, and hence where MOD matters but hasn't been decoded yet it needs to be anyway. (The case of converting to Rm is temporary until a subsequent change.)
2020-07-14x86: simplify decode of opcodes valid with (embedded) 66 prefix onlyJan Beulich1-24/+24
The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-06x86: most VBROADCAST{F,I}{32,64}x* only accept memory operandsJan Beulich1-0/+32
VBROADCAST{F,I}32x2 are the only exceptions here.
2020-06-09x86: utilize X macro in EVEX decodingJan Beulich1-2/+22
For major opcodes allowing only packed FP kinds of operands, i.e. the ones where legacy and AVX decoding uses the X macro, we can do so for AVX512 as well, by attaching to the checking logic the "EVEX.W must match presence of embedded 66 prefix" rule. (Encodings not following this general pattern simply may not gain the PREFIX_OPCODE attribute.) Note that testing of the thus altered decoding has already been put in place by "x86: correct decoding of packed-FP-only AVX encodings". This can also be at least partly applied to scalar-FP-only insns (i.e. V{,U}COMIS{S,D}) as well as the vector-FP forms of insns also allowing scalar encodings (e.g. VADDP{S,D}). Take the opportunity and also fix EVEX-encoded VMOVNTP{S,D} as well as to-memory forms of VMOV{L,H}PS and both forms of VMOV{L,H}PD to wrongly disassemble with only register operands.
2019-07-01x86: remove ModRM.mod decoding layer from AVX512F VMOVS{S,D}Jan Beulich1-20/+0
Just like their AVX counterparts they can utilize XMVexScalar / EXdVexScalarS / EXqVexScalarS taking care of dropping the middle operand for their memory forms.
2019-06-21i386: Break i386-dis-evex.h into small filesH.J. Lu1-0/+62
Break i386-dis-evex.h into small files such that each file is included just once. * i386-dis-evex.h: Break into ... * i386-dis-evex-len.h: New file. * i386-dis-evex-mod.h: Likewise. * i386-dis-evex-prefix.h: Likewise. * i386-dis-evex-reg.h: Likewise. * i386-dis-evex-w.h: Likewise. * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h, i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and i386-dis-evex-mod.h.