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2016-04-05[ARM] Add ARMv8.2 FP16 vmul/vmla/vmls (by scalar)Jiong Wang1-6/+18
gas/ * config/tc-arm.c (do_neon_mac_maybe_scalar): Allow F16. * testsuite/gas/arm/armv8-2-fp16-simd.s: New tests. * testsuite/gas/arm/armv8-2-fp16-simd.d: New expected results. * testsuite/gas/arm/armv8-2-fp16-simd-thum.d: Likewise for Thumb. * testsuite/gas/arm/armv8-2-fp16-simd-warning.l: New warning results. * testsuite/gas/arm/simd_by_scalar_low_regbank.s: New test source. * testsuite/gas/arm/simd_by_scalar_low_regbank.d: New testcase. * testsuite/gas/arm/simd_by_scalar_low_regbank_thumb.d: Likewise for Thumb. * testsuite/gas/arm/simd_by_scalar_low_regbank.l: New warning results. opcodes/ * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
2016-03-16[ARM] Support ARMv8.2 FP16 simd instructionsJiong Wang1-23/+81
gas/ * config/tc-arm.c (N_S_32): New. (N_F_16_32): Likewise. (N_SUF_32): Support N_F16. (N_IF_32): Likewise. (neon_dyadic_misc): Likewise. (do_neon_cmp): Likewise. (do_neon_cmp_inv): Likewise. (do_neon_mul): Likewise. (do_neon_fcmp_absolute): Likewise. (do_neon_step): Likewise. (do_neon_abs_neg): Likewise. (CVT_FLAVOR_VAR): Likewise. (do_neon_cvt_1): Likewise. (do_neon_recip_est): Likewise. (do_vmaxnm): Likewise. (do_vrint_1): Likewise. (neon_check_type): Check architecture support for FP16 extension. (insns): Update comments. * testsuite/gas/arm/armv8-2-fp16-simd.s: New test source. * testsuite/gas/arm/armv8-2-fp16-simd.d: New testcase for arm mode. * testsuite/gas/arm/armv8-2-fp16-simd-thumb.d: Likewise for thumb mode. * testsuite/gas/arm/armv8-2-fp16-simd-warning.d: New rejection test for arm mode. * testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb.d: Likewise for thumb mode. * testsuite/gas/arm/armv8-2-fp16-simd-warning.l: New expected rejection error file. opcode/ * arm-dis.c (neon_opcodes): Support new FP16 instructions.
2016-02-24[OPCODES][ARM][1/3]Add armv8.2 fp16 instruction dissembler support.Renlin Li1-4/+87
opcodes/ 2016-02-24 Renlin Li <renlin.li@arm.com> * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries. (print_insn_coprocessor): Support fp16 instruction. gas/ 2016-02-24 Renlin Li <renlin.li@arm.com> * testsuite/gas/arm/copro.d: Adjust output. * testsuite/gas/arm/copro.s: Adjust co-processor num.
2016-02-24[OPCODES][ARM]Fix mask for a few coprocessor opcodes.Renlin Li1-8/+8
opcodes/ 2016-02-24 Renlin Li <renlin.li@arm.com> * arm-dis.c (coprocessor_opcodes): Fix mask for vsel, vmaxnm, vminnm, vrint(mpna). gas/ 2016-02-24 Renlin Li <renlin.li@arm.com> * testsuite/gas/arm/mask_1.d: New. * testsuite/gas/arm/mask_1.s: New.
2016-02-24[OPCODE][ARM]Correct disassembler for cdp/cdp2, mcr/mcr2, mrc/mrc2, ↵Renlin Li1-0/+23
ldc/ldc2, stc/stc2 opcodes/ 2016-02-24 Renlin Li <renlin.li@arm.com> * arm-dis.c (print_insn_coprocessor): Check co-processor number for cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2. gas/ 2016-02-24 Renlin Li <renlin.li@arm.com> * testsuite/gas/arm/copro.s: Use coprocessor other than 10, 11. * testsuite/gas/arm/copro.d: Update.
2016-01-25[PATCH[ARM]Check mapping symbol while backward searching for IT block.Renlin Li1-3/+78
opcodes/ * arm-dis.c (mapping_symbol_for_insn): New function. (find_ifthen_state): Call mapping_symbol_for_insn(). gas/ * testsuite/gas/arm/thumb2_it_search.d: New. * testsuite/gas/arm/thumb2_it_search.s: New.
2016-01-12[ARM] Support ARMv8.2 RAS extension.Matthew Wahab1-0/+8
The ARMv8.2 architecture includes the RAS extension which adds an instruction, ESB, and a number of coprocessor registers. This patch adds the instruction to binutils, making it available when -march=armv8.2-a is selected. It also adds tests for the instruction and for the coprocessor registers. gas/ 2016-01-12 Matthew Wahab <matthew.wahab@arm.com> * config/tc-arm.c (arm_ext_v8_2): New. (insns): Add "esb". * testsuite/gas/arm/armv8_2-a.d: New. * testsuite/gas/arm/armv8_2-a.s: New. opcodes/ 2016-01-12 Matthew Wahab <matthew.wahab@arm.com> * arm-dis.c (arm_opcodes): Add "esb". (thumb_opcodes): Likewise. Change-Id: I67f3d70789db78d1c66a56c4994675f99ac15e34
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-12-24Add assembler support for ARMv8-M BaselineThomas Preud'homme1-13/+15
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ (tag_cpu_arch_combine): Adjust comment in v4t_plus_v6_m with regards to merging with ARMv8-M Baseline. binutils/ * readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Baseline Tag_CPU_arch value. gas/ * config/tc-arm.c (arm_ext_v6t2_v8m): New feature for instructions shared between ARMv6T2 and ARMv8-M. (move_or_literal_pool): Check mov.w/mvn and movw availability against arm_ext_v6t2 and arm_ext_v6t2_v8m respectively instead of checking arm_arch_t2. (do_t_branch): Error out for wide conditional branch instructions if targetting ARMv8-M Baseline. (non_v6t2_wide_only_insn): Add the logic for new wide-only instructions in ARMv8-M Baseline. (wide_insn_ok): New function. (md_assemble): Use wide_insn_ok instead of non_v6t2_wide_only_insn and adapt error message for unsupported wide instruction to ARMv8-M Baseline. (insns): Reorganize instructions shared by ARMv8-M Baseline and ARMv6t2 architecture. (arm_cpus): Set feature bit ARM_EXT2_V6T2_V8M for marvell-pj4 and marvell-whitney cores. (arm_archs): Define armv8-m.base architecture. (cpu_arch_ver): Define ARM_ARCH_V8M_BASE architecture version. (aeabi_set_public_attributes): Add logic to set Tag_CPU_arch to 17 for ARMv8-M Mainline. Set Tag_DIV_use for ARMv8-M Baseline as well. gas/testsuite/ * gas/arm/archv8m-base.d: New file. * gas/arm/attr-march-armv8m.base.d: Likewise. * gas/arm/armv8m.base-idiv.d: Likewise. * gas/arm/any-armv8m.d: Adapt to deal with ARMv8-M Baseline. include/elf/ * arm.h (TAG_CPU_ARCH_V8M_BASE): Declare. include/opcode/ * arm.h (ARM_EXT2_V6T2_V8M): New extension bit. (ARM_AEXT2_V8A): New architecture extension bitfield. (ARM_AEXT2_V8_1A): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS. (ARM_AEXT_V8M_BASE): New architecture extension bitfield. (ARM_AEXT2_V8M): Add extension bit ARM_EXT2_V6T2_V8M. (ARM_ARCH_V6T2): Use ARM_EXT2_V6T2_V8M for the second extension bitfield. (ARM_ARCH_V6KT2): Likewise. (ARM_ARCH_V6ZT2): Likewise. (ARM_ARCH_V6KZT2): Likewise. (ARM_ARCH_V7): Likewise. (ARM_ARCH_V7A): Likewise. (ARM_ARCH_V7VE): Likewise. (ARM_ARCH_V7R): Likewise. (ARM_ARCH_V7M): Likewise. (ARM_ARCH_V7EM): Likewise. (ARM_ARCH_V8A): Likewise. (ARM_ARCH_V8M_BASE): New architecture bitfield. (ARM_ARCH_THUMB2): Include instructions shared by ARMv6t2 and ARMv8-M. (ARM_ARCH_V7A_SEC): Use ARM_EXT2_V6T2_V8M for the second extension bitfield and reindent. (ARM_ARCH_V7A_MP_SEC): Likewise. (ARM_ARCH_V7R_IDIV): Likewise. (ARM_ARCH_V8A_FP): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS. (ARM_ARCH_V8A_SIMD): Likewise. (ARM_ARCH_V8A_CRYPTOV1): Likewise. opcodes/ * arm-dis.c (arm_opcodes): Guard movw, movt cbz, cbnz, clrex, ldrex, ldrexb, ldrexh, strex, strexb, strexh shared by ARMv6T2 and ARMv8-M by ARM_EXT2_V6T2_V8M instead of ARM_EXT_V6T2.
2015-12-24Add assembler support for ARMv8-M MainlineThomas Preud'homme1-12/+18
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ (tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in comb array. binutils/ * readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch value. (arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use value. gas/ * config/tc-arm.c (arm_ext_m): Include ARMv8-M. (arm_ext_v8m): New feature for ARMv8-M. (arm_ext_atomics): New feature for ARMv8 atomics. (do_tt): New encoding function for TT* instructions. (insns): Add new entries for ARMv8-M specific instructions and reorganize the ones shared by ARMv8-M Mainline and ARMv8-A. (arm_archs): Define armv8-m.main architecture. (cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and clarify the ordering rule. (aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile to 'A' if extension bit for atomic instructions is set, unless it is ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0 for ARMv8-M Mainline. gas/testsuite/ * gas/arm/archv8m.s: New file. * gas/arm/archv8m-main.d: Likewise. * gas/arm/attr-march-armv8m.main.d: Likewise. * gas/arm/any-armv8m.s: Likewise. * gas/arm/any-armv8m.d: Likewise. include/elf/ * arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare. (MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN. (TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15. include/opcode/ * arm.h (ARM_EXT2_ATOMICS): New extension bit. (ARM_EXT2_V8M): Likewise. (ARM_EXT_V8): Adjust comment with regards to atomics and remove mention of legacy use for that bit. (ARM_AEXT2_V8_1A): New architecture extension bitfield. (ARM_AEXT2_V8_2A): Likewise. (ARM_AEXT_V8M_MAIN): Likewise. (ARM_AEXT2_V8M): Likewise. (ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield. (ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A. (ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A. (ARM_ARCH_V8M_MAIN): New architecture feature bitfield. (ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield and reindent. (ARM_ARCH_V8A_SIMD): Likewise. (ARM_ARCH_V8A_CRYPTOV1): Likewise. (ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of feature bits. (ARM_ARCH_V8_1A_SIMD): Likewise. (ARM_ARCH_V8_1A_CRYPTOV1): Likewise. opcodes/ * arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl, stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of ARM_EXT_V8. (thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-02Fix ldah being disassembled as ldaexhAndre Vieira1-1/+1
2015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> opcodes/ * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo... <ldah>: ... to this. gas/testsuite/ * gas/arm/armv8-a.d: <ldaexh>: Rename mismatched mnemonics ... <ldah>: ... to this.
2015-11-23opcodes: handle mach-o for thumb/arm disambiguation.Tristan Gingold1-0/+8
opcodes/ * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
2015-08-13Fixes for unpredictable nops and 26-bit versions of teq,tst,cmn,cmp.Andre Vieira1-3/+11
opcodes * arm-dis.c (print_insn_arm): Disassembling for all targets V6 and higher with ARM instruction set will now mark the 26-bit versions of teq,tst,cmn and cmp as UNPREDICTABLE. (arm_opcodes): Fix for unpredictable nop being recognized as a teq. test * gas/arm/nops.d: New. * gas/arm/nops.s: New. * gas/arm/inst.d: Changed expectation file for 26-bit teq, tst, cmn and cmp.
2015-08-12Remove trailing spaces in opcodesH.J. Lu1-57/+57
2015-07-16Updates the ARM disassembler's output of floating point constants to include ↵Alessandro Marzocchi1-2/+33
the actual floating point value. opcodes * arm-dis.c (print_insn_coprocessor): Added support for quarter float bitfield format. (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new quarter float bitfield format. tests * gas/arm/vfpv3-const-conv.d: Update expected result due to change of comment for vmov reg,immediate with VFP coprocessor.
2015-06-16Fixes a compile time warnng about left shifting a negative value.Szabolcs Nagy1-1/+1
* arm-dis.c (print_insn_coprocessor): Avoid negative shift.
2015-06-02[ARM] Support for ARMv8.1 Adv.SIMD extensionMatthew Wahab1-0/+19
2015-06-02[ARM] Add support for ARMv8.1 PAN extensionMatthew Wahab1-0/+5
2015-06-02[ARM] Rework CPU feature selection in the disassemblerMatthew Wahab1-29/+26
include/opcode/ * arm.h (ARM_FEATURE_ALL): New. opcodes/ * arm-dis.c (select_arm_features): Rework to avoid used of redefined macros.
2015-04-15[ARM] Disassembles SSAT and SSAT16 instructions incorrectly for Thumb-2Renlin Li1-2/+8
2015-04-15 Renlin Li <renlin.li@arm.com> opcodes/: * arm-dis.c (thumb32_opcodes): Define 'D' format control code, use it for ssat and ssat16. (print_insn_thumb32): Add handle case for 'D' control code. gas/testsuite/: * gas/arm/arch7em.d: Adjust required ssat and ssat16 immediate field. * gas/arm/thumb32.d: Likewise.
2015-03-24Extend arm_feature_set struct to provide more bitsTerry Guo1-1294/+2530
gas/ChangeLog: 2015-03-24 Terry Guo <terry.guo@arm.com> * config/tc-arm.c (no_cpu_selected): Use new macro to compare features. (parse_psr): Likewise. (do_t_mrs): Likewise. (do_t_msr): Likewise. (static const arm_feature_set arm_ext_*): Defined with new macros. (static const arm_feature_set arm_cext_*): Likewise. (static const arm_feature_set fpu_fpa_ext_*): Likewise. (static const arm_feature_set fpu_vfp_ext_*): Likewise. (deprecated_coproc_regs): Likewise. (UL_BARRIER): Likewise. (barrier_opt_names): Likewise. (arm_cpus): Likewise. (arm_extensions): Likewise. include/opcode/ChangeLog: 2015-03-24 Terry Guo <terry.guo@arm.com> * arm.h (arm_feature_set): Extended to provide more available * bits. (ARM_ANY): Updated to follow above new definition. (ARM_CPU_HAS_FEATURE): Likewise. (ARM_CPU_IS_ANY): Likewise. (ARM_MERGE_FEATURE_SETS): Likewise. (ARM_CLEAR_FEATURE): Likewise. (ARM_FEATURE): Likewise. (ARM_FEATURE_COPY): New macro. (ARM_FEATURE_EQUAL): Likewise. (ARM_FEATURE_ZERO): Likewise. (ARM_FEATURE_CORE_EQUAL): Likewise. (ARM_FEATURE_LOW): Likewise. (ARM_FEATURE_CORE_LOW): Likewise. (ARM_FEATURE_CORE_COPROC): Likewise. opcodes/ChangeLog: 2015-03-24 Terry Guo <terry.guo@arm.com> * arm-dis.c (opcode32): Updated to use new arm feature struct. (opcode16): Likewise. (coprocessor_opcodes): Replace bit with feature struct. (neon_opcodes): Likewise. (arm_opcodes): Likewise. (thumb_opcodes): Likewise. (thumb32_opcodes): Likewise. (print_insn_coprocessor): Likewise. (print_insn_arm): Likewise. (select_arm_features): Follow new feature struct.
2015-03-03[ARM] Skip private symbol when doing objdumpJiong Wang1-2/+5
2015-03-03 Jiong Wang <jiong.wang@arm.com> opcode/ * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols. binutils/testsuite/ * binutils-all/arm/rvct_symbol.s: New testcase. * binutils-all/arm/objdump.exp: Run it.
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-08-22ARM/opcodes: Fix negative hexadecimal offset disassemblyMaciej W. Rozycki1-0/+2
2014-08-21 Nathan Sidwell <nathan@codesourcery.com> Maciej W. Rozycki <macro@codesourcery.com> opcodes/ * arm-dis.c (print_arm_address): Negate the GPR-relative offset returned if the U bit is set. 2014-08-21 Paul Brook <paul@codesourcery.com> gas/testsuite/ * gas/arm/arch7a-mp.d: Adjust according to `print_arm_address' offset fix. * gas/arm/arch7r-mp.d: Likewise.
2014-03-05Update copyright yearsAlan Modra1-1/+1
2013-10-15Fix neon vshll disassembly.Ramana Radhakrishnan1-3/+3
opcodes/ 2013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * arm-dis.c (neon_opcodes): Adjust print string for vshll. gas/testsuite/ 2013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * gas/arm/neon-cov.d: Adjust output.
2013-09-04 PR gas/15914Nick Clifton1-3/+16
* config/tc-arm.c (T16_32_TAB): Add _udf. (do_t_udf): New function. (insns): Add "udf". * gas/arm/udf-bad.s: New file. * gas/arm/udf-bad.d: New file. * gas/arm/udf-bad.l: New file. * gas/arm/udf.s: New file. * gas/arm/udf.d: New file. * gas/arm/udf.l: New file. * arm-dis.c (arm_opcodes): Add udf. (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION. (thumb32_opcodes): Add udf.w. (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
2013-03-11Add support for AArch32 CRC instruction in ARMv8.Kyrylo Tkachov1-1/+21
gas/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/tc-arm.c (crc_ext_armv8): New feature set. (UNPRED_REG): New macro. (do_crc32_1): New function. (do_crc32b, do_crc32h, do_crc32w, do_crc32cb, do_crc32ch, do_crc32cw): Likewise. (TUEc): New macro. (insns): Add entries for crc32 mnemonics. (arm_extensions): Add entry for crc. include/opcode/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * arm.h (CRC_EXT_ARMV8): New constant. (ARCH_CRC_ARMV8): New macro. opcodes/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * arm-dis.c (arm_opcodes): Add entries for CRC instructions. (thumb32_opcodes): Likewise. (print_insn_thumb32): Handle 'S' control char. gas/testsuite/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * gas/arm/crc32-bad.d: New file. * gas/arm/crc32-bad.l: Likewise. * gas/arm/crc32-bad.s: Likewise. * gas/arm/crc32.d: Likewise. * gas/arm/crc32.s: Likewise.
2013-02-112013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>Richard Earnshaw1-2/+2
* arm-dis.c: Update strht pattern. * gas/arm/archv6t2.s: Add strht and ldrht tests. * gas/arm/archv6t2.d: Add disassembly patterns for the above.
2012-10-112012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>Richard Earnshaw1-5/+5
* arm-dis.c: Use preferred form of vrint instruction variants for disassembly. 2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * gas/arm/armv8-a+fp.d: Use preferred form of vrint instruction variants for disassembly. * gas/arm/armv8-a+fp.s: Likewise. * gas/arm/armv8-a+simd.d: Likewise. * gas/arm/armv8-a+simd.s: Likewise.
2012-09-182012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>Richard Earnshaw1-28/+28
opcodes: * arm-dis.c: Changed ldra and strl-form mnemonics to lda and stl-form. gas: * config/tc-arm.c: Changed ldra and strl-form mnemonics to lda and stl-form for armv8. gas/testsuite: * gas/arm/armv8-a-bad.l: Updated for changed mnemonics. * gas/arm/armv8-a-bad.s: Likewise. * gas/arm/armv8-a.d: Likewise. * gas/arm/armv8-a.s: Likewise. * gas/arm/inst.s: Added test for ldrt encoding compatibly with ldralt. * gas/arm/inst.d: Updated.
2012-08-24 * gas/config/tc-arm.c (ARM_ENC_TAB): Add sha1h and sha2op entries.Matthew Gretton-Dann1-0/+3
(do_sha1h): New function. (do_sha1su1): Likewise. (do_sha256su0): Likewise. (insns): Add 2 operand SHA instructions. * gas/testsuite/gas/arm/armv8-a+crypto.s: Update testcase. * gas/testsuite/gas/arm/armv8-a+crypto.d: Likewise. * opcodes/arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
2012-08-24 * gas/config/tc-arm.c (NEON_ENC_TAB): Add sha3op entry.Matthew Gretton-Dann1-0/+7
(do_crypto_3op_1): New function. (do_sha1c): Likewise. (do_sha1p): Likewise. (do_sha1m): Likewise. (do_sha1su0): Likewise. (do_sha256h): Likewise. (do_sha256h2): Likewise. (do_sha256su1): Likewise. (insns): Add SHA 3 operand instructions. * gas/testsuite/gas/arm/armv8-a+crypto.d: Update testcase. * gas/testsuite/gas/arm/armv8-a+crypto.s: Likewise. * opcodes/arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
2012-08-24 * gas/config/tc-arm.c (neon_type_mask): Add P64 type.Matthew Gretton-Dann1-0/+1
(type_chk_of_el_type): Handle P64 type. (el_type_of_type_chk): Likewise. (do_neon_vmull): Handle VMULL.P64. * gas/testsuite/gas/arm/armv8-a+crypto.d: Update testcase. * gas/testsuite/gas/arm/armv8-a+crypto.s: Likewise. * opcodes/arm-dis.c (neon_opcodes): Handle VMULL.P64.
2012-08-24 * gas/config/tc-arm.c (NEON_ENC_TAB): Add aes entry.Matthew Gretton-Dann1-0/+4
(neon_type_mask): Add N_UNT. (neon_check_type): Don't always decay typed to untyped sizes. (do_crypto_2op_1): New function. (do_aese): Likewise. (do_aesd): Likewise. (do_aesmc.8): Likewise. (do_aesimc.8): Likewise. (insns): Add AES instructions. * gas/testsuite/gas/arm/armv8-a+crypto.d: New testcase. * gas/testsuite/gas/arm/armv8-a+crypto.s: Likewise. * opcodes/arm-dis.c (neon_opcodes): Add support for AES instructions.
2012-08-24 * gas/config/tc-arm.c (el_type_type_check): Add handling for 16-bitMatthew Gretton-Dann1-0/+2
floating point types. (do_neon_cvttb_2): New function. (do_neon_cvttb_1): Likewise. (do_neon_cvtb): Refactor to use do_neon_cvttb_1. (do_neon_cvtt): Likewise. * gas/testsuite/gas/arm/armv8-a+fp.d: Update testcase. * gas/testsuite/gas/arm/armv8-a+fp.s: Likewise. * gas/testsuite/gas/arm/half-prec-vfpv3.s: Likewise. * opcodes/arm-dis.c (coprocessor_opcodes): Add support for HP/DP conversions.
2012-08-24 * gas/config/tc-arm.c (NEON_ENC_TAB): Add vrint entries.Matthew Gretton-Dann1-0/+5
(neon_cvt_mode): Add neon_cvt_mode_r. (do_vrint_1): New function. (do_vrint_x): Likewise. (do_vrint_z): Likewise. (do_vrint_r): Likewise. (do_vrint_a): Likewise. (do_vrint_n): Likewise. (do_vrint_p): Likewise. (do_vrint_m): Likewise. (insns): Add VRINT instructions. * gas/testsuite/gas/arm/armv8-a+fpv5.d: Update testcase. * gas/testsuite/gas/arm/armv8-a+fpv5.s: Likewise. * gas/testsuite/gas/arm/armv8-a+simdv3.d: Likewise. * gas/testsuite/gas/arm/armv8-a+simdv3.s: Likewise. * opcodes/arm-dis.c (coprocessor_opcodes): Add VRINT. (neon_opcodes): Likewise.
2012-08-24 * gas/config/tc-arm.c (NEON_ENC_TAB): Add vcvta entry.Matthew Gretton-Dann1-1/+4
(neon_cvt_mode): New enumeration. (do_vfp_nsyn_cvt_fpv8): New function. (do_neon_cvt_1): Add support for new conversions. (do_neon_cvtr): Use neon_cvt_mode enumerator. (do_neon_cvt): Likewise. (do_neon_cvta): New function. (do_neon_cvtn): Likewise. (do_neon_cvtp): Likewise. (do_neon_cvtm): Likewise. (insns): Add new VCVT instructions. * gas/testsuite/gas/arm/armv8-a+fp.d: Update testcase. * gas/testsuite/gas/arm/armv8-a+fp.s: Likewise. * gas/testsuite/gas/arm/armv8-a+simd.d: Likewise. * gas/testsuite/gas/arm/armv8-a+simd.s: Likewise. * opcodes/arm-dis.c (coprocessor_opcodes): Add support for new VCVT variants. (neon_opcodes): Likewise.
2012-08-24 * gas/config/tc-arm.c (NEON_ENC_TAB): Add vmaxnm, vminnm entries.Matthew Gretton-Dann1-0/+6
(vfp_or_neon_is_neon_bits): Add NEON_CHECK_ARCH8 enumerator. (vfp_or_neon_is_neon): Add check for SIMD for ARMv8. (do_maxnm): New function. (insns): Add vmaxnm, vminnm entries. * gas/testsuite/gas/testsuite/gas/armv8-a+fp.d: Update testcase. * gas/testsuite/gas/testsuite/gas/armv8-a+fp.s: Likewise. * gas/testsuite/gas/testsuite/gas/armv8-a+simd.d: New testcase. * gas/testsuite/gas/testsuite/gas/armv8-a+simd.s: Likewise. * opcodes/arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM. (neon_opcodes): Likewise.
2012-08-24 * gas/config/tc-arm.c (NEON_ENC_TAB): Add entries for VSEL.Matthew Gretton-Dann1-0/+30
(NEON_ENC_FPV8_): New define. (do_vfp_nsyn_fpv8): New function. (do_vsel): Likewise. (insns): Add VSEL instructions. * gas/testsuite/gas/arm/armv8-a+fp.d: New testcase. * gas/testsuite/gas/arm/armv8-a+fp.s: Likewise. * opcodes/arm-dis.c (coprocessor_opcodes): Add VSEL. (print_insn_coprocessor): Add new %<>c bitfield format specifier.
2012-08-24 * gas/config/tc-arm.c (do_rm_rn): New function.Matthew Gretton-Dann1-1/+34
(do_strlex): Likewise. (do_t_strlex): Likewise. (insns): Add support for LDRA/STRL instructions. * gas/testsuite/gas/arm/armv8-a-bad.l: Update testcase. * gas/testsuite/gas/arm/armv8-a-bad.s: Likewise. * gas/testsuite/gas/arm/armv8-a.d: Likewise. * gas/testsuite/gas/arm/armv8-a.s: Likewise. * opcodes/arm-dis.c (arm_opcodes): Add LDRA/STRL instructions. (thumb32_opcodes): Likewise. (print_arm_insn): Add support for %<>T formatter.
2012-08-24 * gas/config/tc-arm.c (do_t_bkpt_hlt1): New function.Matthew Gretton-Dann1-0/+3
(do_t_hlt): New function. (do_t_bkpt): Use do_t_bkpt_hlt1. (insns): Add HLT. * gas/testsuite/gas/arm/armv8-a-bad.l: Update for HLT. * gas/testsuite/gas/arm/armv8-a-bad.s: Likewise. * gas/testsuite/gas/arm/armv8-a.d: Likewise. * gas/testsuite/gas/arm/armv8-a.s: Likewise. * opcodes/arm-dis.c (arm_opcodes): Add HLT. (thumb_opcodes): Likewise.
2012-08-24 * gas/config/tc-arm.c (insns): Add DCPS instruction.Matthew Gretton-Dann1-0/+1
* gas/testsuite/gas/arm/armv8-a.d: Update. * gas/testsuite/gas/arm/armv8-a.s: Likewise. * opcodes/arm-dis.c (thumb32_opcodes): Add DCPS instruction.
2012-08-24 * gas/config/tc-arm.c (T16_32_TAB): Add _sevl.Matthew Gretton-Dann1-0/+9
(insns): Add SEVL. * gas/testsuite/gas/arm/armv8-a.s: New testcase. * gas/testsuite/gas/arm/armv8-a.d: Likewise. * opcodes/arm-dis.c (arm_opcodes): Add SEVL. (thumb_opcodes): Likewise. (thumb32_opcodes): Likewise.
2012-08-24 * gas/config/tc-arm.c (asm_barrier_opt): Add arch field.Matthew Gretton-Dann1-27/+35
(mark_feature_used): New function. (parse_barrier): Check specified option is valid for the specified architecture. (UL_BARRIER): New macro. (barrier_opt_names): Update for new barrier options. * gas/testsuite/gas/arm/armv8-a-barrier.s: New testcase. * gas/testsuite/gas/arm/armv8-a-barrier-arm.d: Likewise. * gas/testsuite/gas/arm/armv8-a-barrier-thumb.d: Likewise. * opcodes/arm-dis.c (data_barrier_option): New function. (print_insn_arm): Use data_barrier_option. (print_insn_thumb32): Use data_barrier_option.
2012-08-24 * opcodes/arm-dis.c (COND_UNCOND): New constant.Matthew Gretton-Dann1-4/+24
(print_insn_coprocessor): Add support for %u format specifier. (print_insn_neon): Likewise.
2012-07-24 PR binutils/13135Nick Clifton1-28/+29
* arm-dis.c: Add necessary casts for printing integer values. Use %s when printing string values. * hppa-dis.c: Likewise. * m68k-dis.c: Likewise. * microblaze-dis.c: Likewise. * mips-dis.c: Likewise. * ppc-dis.c: Likewise. * sparc-dis.c: Likewise. * dis-asm.h (fprintf_ftype): Add ATTRIBUTE_FPTR_PRINTF_2.
2012-05-16 * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}Nick Clifton1-0/+34
to PUSH/POP {reg}. * binutils-all/arm/objdump.exp: STMFD/LDMIA sp!, {reg} don't disassemble to PUSH/POP {reg} any longer. * gas/arm/stm-ldm.d: STMFD/LDMIA sp!, {reg} don't disassemble to PUSH/POP {reg} any longer. Some new test cases have been added as well. * gas/arm/stm-ldm.s: Likewise.
2012-05-11 PR binutils/14006Nick Clifton1-3/+13
* arm-dis.c (print_insn): Fix detection of instruction mode in files containing multiple executable sections.
2011-10-18 Jie Zhang <jie@codesourcery.com>Julian Brown1-6/+16
Julian Brown <julian@codesourcery.com> gas/ * config/tc-arm.c (parse_shifter_operand): Fix handling of explicit rotation. (encode_arm_shifter_operand): Likewise. gas/testsuite/ * gas/arm/adrl.d: Adjust. * gas/arm/immed2.d: New test. * gas/arm/immed2.s: New test. ld/testsuite/ * ld-arm/cortex-a8-fix-b-plt.d: Adjust. * ld-arm/cortex-a8-fix-bcc-plt.d: Adjust. * ld-arm/cortex-a8-fix-bl-plt.d: Adjust. * ld-arm/cortex-a8-fix-bl-rel-plt.d: Adjust. * ld-arm/cortex-a8-fix-blx-plt.d: Adjust. * ld-arm/ifunc-1.dd: Adjust. * ld-arm/ifunc-2.dd: Adjust. * ld-arm/ifunc-3.dd: Adjust. * ld-arm/ifunc-4.dd: Adjust. * ld-arm/ifunc-5.dd: Adjust. * ld-arm/ifunc-6.dd: Adjust. * ld-arm/ifunc-7.dd: Adjust. * ld-arm/ifunc-8.dd: Adjust. * ld-arm/ifunc-9.dd: Adjust. * ld-arm/ifunc-10.dd: Adjust. * ld-arm/ifunc-14.dd: Adjust. * ld-arm/ifunc-15.dd: Adjust. * ld-arm/ifunc-16.dd: Adjust. opcodes/ * arm-dis.c (print_insn_arm): Explicitly specify rotation if needed.
generated by cgit v1.1 at 2025-01-15 07:19:25 +0000