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2017-08-09[ARM] Don't warn on REG_SP when used in CRC32 instructionsJiong Wang1-11/+6
According to ARMv8-A architecture manual, REG_SP is allowed in CRC32 instructions in Thumb mode. It is REG_PC that will cause unpredictable behaviours on both ARM and Thumb. This patch removes the incorrect warning on Thumb mode. Meanwhile the disassembler is updated to use format "<bitfield>R" instead of "<bitfield>S". "<bitfield>S" is not used elsewhere. so I have deleted related code from the disassembler. gas/ * config/tc-arm.c (do_crc32_1): Remove warning on REG_SP for thumb_mode. * testsuite/gas/arm/crc32-armv8-a-bad.d: Update exepcted result. * testsuite/gas/arm/crc32-armv8-r-bad.d: Likewise. * testsuite/gas/arm/crc32-armv8-a.d: Likewise. * testsuite/gas/arm/crc32-armv8-r.d: Likewise. * testsuite/gas/arm/crc32-armv8-ar-bad.s: Update test case. * testsuite/gas/arm/crc32-armv8-ar.s: Likewise. * testsuite/gas/arm/crc32-bad.l: Update expected error message. opcode/ * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for register operands in CRC instructions. (print_insn_thumb32): Remove "<bitfield>S" support. Updated the comments.
2017-07-04[Patch ARM] Support MVFR2 VFP Coprocessor register for ARMv8-ARamana Radhakrishnan1-0/+4
This patch adds support mvfr2 control registers for armv8-a as this was missed from the original port to armv8-a (documented at G6.2.109 in (Issue B.a) of the ARM-ARM. This was discovered by an internal user of the GNU toolchain. I'd like to backport this to the binutils 2.28 and binutils 2.29 release branch if possible (with suitable testing and basically checking removing the armv8-r parts). Tristan - are you ok with the backports ? Applied to trunk. regards Ramana 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * gas/config/tc-arm.c (arm_regs): Add MVFR2. (do_vmrs): Constraint for MVFR2 and armv8. (do_vmsr): Likewise. * gas/testsuite/gas/arm/armv8-a+fp.d: Update. * gas/testsuite/gas/arm/armv8-ar+fp.s: Likewise. * gas/testsuite/gas/arm/armv8-r+fp.d: Likewise. * gas/testsuite/gas/arm/vfp-bad.s: Likewise. * gas/testsuite/gas/arm/vfp-bad.l: Likewise. * opcodes/arm-dis.c: Support MVFR2 in disassembly with vmrs and vmsr.
2017-06-28[ARM] Assembler and disassembler support Dot Product ExtensionJiong Wang1-0/+6
This patch add assembler and disassembler support for new Dot Product Extension. The support can be enabled through the new "+dotprod" extension. include/ * opcode/arm.h (FPU_NEON_EXT_DOTPROD): New macro. (FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): New macro. gas/ * config/tc-arm.c (fpu_neon_ext_dotprod): New variable. (neon_scalar_for_mul): Improve comments. (do_neon_dotproduct): New function to encode Dot Product instructions. (do_neon_dotproduct_s): Wrapper function for signed Dot Product instructions. (do_neon_dotproduct_u): Wrapper function for unsigned Dot Product instructions. (insns): New entries for vsdot and vudot. (arm_extensions): New entry for "dotprod". * doc/c-arm.texi: Document new "dotprod" extension. * testsuite/gas/arm/dotprod.s: New test source. * testsuite/gas/arm/dotprod-illegal.s: New test source. * testsuite/gas/arm/dotprod.d: New test. * testsuite/gas/arm/dotprod-thumb2.d: New test. * testsuite/gas/arm/dotprod-illegal.d: New test. * testsuite/gas/arm/dotprod-legacy-arch.d: New test. * testsuite/gas/arm/dotprod-illegal.l: New error file. * testsuite/gas/arm/dotprod-legacy-arch.l: New error file. opcodes/ * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
2017-06-14Don't use print_insn_XXX in GDBYao Qi1-1/+1
This is a follow-up to [PATCH 0/6] Unify the disassembler selection in gdb and objdump https://sourceware.org/ml/binutils/2017-05/msg00192.html that is, opcodes is able to select the right disassembler, so gdb doesn't have to select them. Instead, gdb can just use default_print_insn. As a result, these print_insn_XXX are not used out of opcodes, so this patch also moves their declarations from include/dis-asm.h to opcodes/disassemble.h. With this change, GDB doesn't use any print_insn_XXX directly any more. gdb: 2017-06-14 Yao Qi <yao.qi@linaro.org> * aarch64-tdep.c (aarch64_gdb_print_insn): Call default_print_insn instead of print_insn_aarch64. * arm-tdep.c (gdb_print_insn_arm): Call default_print_insn instead of print_insn_big_arm and print_insn_little_arm. * i386-tdep.c (i386_print_insn): Call default_print_insn instead of print_insn_i386. * ia64-tdep.c (ia64_print_insn): Call default_print_insn instead of print_insn_ia64. * mips-tdep.c (gdb_print_insn_mips): Call default_print_insn instead of print_insn_big_mips and print_insn_little_mips. * spu-tdep.c (gdb_print_insn_spu): Call default_print_insn instead of print_insn_spu. include: 2017-06-14 Yao Qi <yao.qi@linaro.org> * dis-asm.h (print_insn_aarch64): Move it to opcodes/disassemble.h. (print_insn_big_arm, print_insn_big_mips): Likewise. (print_insn_i386, print_insn_ia64): Likewise. (print_insn_little_arm, print_insn_little_mips): Likewise. (print_insn_spu): Likewise. opcodes: 2017-06-14 Yao Qi <yao.qi@linaro.org> * aarch64-dis.c: Include disassemble.h instead of dis-asm.h. * arm-dis.c: Likewise. * ia64-dis.c: Likewise. * mips-dis.c: Likewise. * spu-dis.c: Likewise. * disassemble.h (print_insn_aarch64): New declaration, moved from include/dis-asm.h. (print_insn_big_arm, print_insn_big_mips): Likewise. (print_insn_i386, print_insn_ia64): Likewise. (print_insn_little_arm, print_insn_little_mips): Likewise.
2017-06-14[opcodes][arm] Remove bogus entry added by accident in former patchAndre Vieira1-2/+0
2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com> * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
2017-05-02Fix value in comment of disassembled ARM type A opcodes.Bernd Edlinger1-2/+2
* arm-dis.c (print_insn_thumb32): Fix value_in_comment.
2017-04-05-Wwrite-strings: Constify struct disassemble_info's disassembler_options fieldPedro Alves1-2/+2
The memory disassemble_info::disassembler_options points to is always owned by the client. I.e., that field is an non-owning, observing pointer. Thus const makes sense. Are the include/ and opcodes/ bits OK? Tested on x86_64 Fedora 23, built with --enable-targets=all. include/ChangeLog: 2017-04-05 Pedro Alves <palves@redhat.com> * dis-asm.h (disassemble_info) <disassembler_options>: Now a "const char *". (next_disassembler_option): Constify. opcodes/ChangeLog: 2017-04-05 Pedro Alves <palves@redhat.com> * arc-dis.c (parse_option, parse_disassembler_options): Constify. * arm-dis.c (parse_arm_disassembler_options): Constify. * ppc-dis.c (powerpc_init_dialect): Constify local. * vax-dis.c (parse_disassembler_options): Constify. gdb/ChangeLog: 2017-04-05 Pedro Alves <palves@redhat.com> * arm-tdep.c (show_disassembly_style_sfunc): Constify local. * disasm.c (set_disassembler_options): Constify local. * i386-tdep.c (i386_print_insn): Remove cast and FIXME comment.
2017-02-28GDB: Add support for the new set/show disassembler-options commands.Peter Bergner1-95/+74
This commit adds support to GDB so that it can modify the disassembler-options value that is passed to the disassembler, similar to objdump's -M option. Currently, the only supported targets are ARM, PowerPC and S/390, but adding support for a new target(s) is not difficult. include/ * dis-asm.h (disasm_options_t): New typedef. (parse_arm_disassembler_option): Remove prototype. (set_arm_regname_option): Likewise. (get_arm_regnames): Likewise. (get_arm_regname_num_options): Likewise. (disassemble_init_s390): New prototype. (disassembler_options_powerpc): Likewise. (disassembler_options_arm): Likewise. (disassembler_options_s390): Likewise. (remove_whitespace_and_extra_commas): Likewise. (disassembler_options_cmp): Likewise. (next_disassembler_option): New inline function. (FOR_EACH_DISASSEMBLER_OPTION): New macro. opcodes/ * disassemble.c Include "safe-ctype.h". (disassemble_init_for_target): Handle s390 init. (remove_whitespace_and_extra_commas): New function. (disassembler_options_cmp): Likewise. * arm-dis.c: Include "libiberty.h". (NUM_ELEM): Delete. (regnames): Use long disassembler style names. Add force-thumb and no-force-thumb options. (NUM_ARM_REGNAMES): Rename from this... (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE. (get_arm_regname_num_options): Delete. (set_arm_regname_option): Likewise. (get_arm_regnames): Likewise. (parse_disassembler_options): Likewise. (parse_arm_disassembler_option): Rename from this... (parse_arm_disassembler_options): ...to this. Make static. Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options. (print_insn): Use parse_arm_disassembler_options. (disassembler_options_arm): New function. (print_arm_disassembler_options): Handle updated regnames. * ppc-dis.c: Include "libiberty.h". (ppc_opts): Add "32" and "64" entries. (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp. (powerpc_init_dialect): Add break to switch statement. Use new FOR_EACH_DISASSEMBLER_OPTION macro. (disassembler_options_powerpc): New function. (print_ppc_disassembler_options): Use ARRAY_SIZE. Remove printing of "32" and "64". * s390-dis.c: Include "libiberty.h". (init_flag): Remove unneeded variable. (struct s390_options_t): New structure type. (options): New structure. (init_disasm): Rename from this... (disassemble_init_s390): ...to this. Add initializations for current_arch_mask and option_use_insn_len_bits_p. Remove init_flag. (print_insn_s390): Delete call to init_disasm. (disassembler_options_s390): New function. (print_s390_disassembler_options): Print using information from struct 'options'. * po/opcodes.pot: Regenerate. binutils/ * objdump.c (main): Use remove_whitespace_and_extra_commas. gdb/ * NEWS: Mention new set/show disassembler-options commands. * doc/gdb.texinfo: Document new set/show disassembler-options commands. * disasm.c: Include "arch-utils.h", "gdbcmd.h" and "safe-ctype.h". (prospective_options): New static variable. (gdb_disassembler::gdb_disassembler): Initialize m_di.disassembler_options. (gdb_buffered_insn_length_init_dis): Initilize di->disassembler_options. (get_disassembler_options): New function. (set_disassembler_options): Likewise. (set_disassembler_options_sfunc): Likewise. (show_disassembler_options_sfunc): Likewise. (disassembler_options_completer): Likewise. (_initialize_disasm): Likewise. * disasm.h (get_disassembler_options): New prototype. (set_disassembler_options): Likewise. * gdbarch.sh (gdbarch_disassembler_options): New variable. (gdbarch_verify_disassembler_options): Likewise. * gdbarch.c: Regenerate. * gdbarch.h: Likewise. * arm-tdep.c (num_disassembly_options): Delete. (set_disassembly_style): Likewise. (arm_disassembler_options): New static variable. (set_disassembly_style_sfunc): Convert short style name into long option name. Call set_disassembler_options. (show_disassembly_style_sfunc): New function. (arm_gdbarch_init): Call set_gdbarch_disassembler_options and set_gdbarch_verify_disassembler_options. (_initialize_arm_tdep): Delete regnames variable and update callers. (arm_disassembler_options): Initialize. (disasm_options): New variable. (num_disassembly_options): Rename from this... (num_disassembly_styles): ...to this. Compute by scanning through disasm_options. (valid_disassembly_styles): Initialize using disasm_options. Remove calls to parse_arm_disassembler_option, get_arm_regnames and set_arm_regname_option. Pass show_disassembly_style_sfunc to the "disassembler" setshow command. * rs6000-tdep.c (powerpc_disassembler_options): New static variable. (rs6000_gdbarch_init): Call set_gdbarch_disassembler_options and set_gdbarch_verify_disassembler_options. * s390-tdep.c (s390_disassembler_options): New static variable. (s390_gdbarch_init):all set_gdbarch_disassembler_options and set_gdbarch_verify_disassembler_options. gdb/testsuite/ * gdb.arch/powerpc-power.exp: Delete test. * gdb.arch/powerpc-power.s: Likewise. * gdb.disasm/disassembler-options.exp: New test. * gdb.arch/powerpc-altivec.exp: Likewise. * gdb.arch/powerpc-altivec.s: Likewise. * gdb.arch/powerpc-altivec2.exp: Likewise. * gdb.arch/powerpc-altivec2.s: Likewise. * gdb.arch/powerpc-altivec3.exp: Likewise. * gdb.arch/powerpc-altivec3.s: Likewise. * gdb.arch/powerpc-power7.exp: Likewise. * gdb.arch/powerpc-power7.s: Likewise. * gdb.arch/powerpc-power8.exp: Likewise. * gdb.arch/powerpc-power8.s: Likewise. * gdb.arch/powerpc-power9.exp: Likewise. * gdb.arch/powerpc-power9.s: Likewise. * gdb.arch/powerpc-vsx.exp: Likewise. * gdb.arch/powerpc-vsx.s: Likewise. * gdb.arch/powerpc-vsx2.exp: Likewise. * gdb.arch/powerpc-vsx2.s: Likewise. * gdb.arch/powerpc-vsx3.exp: Likewise. * gdb.arch/powerpc-vsx3.s: Likewise. * gdb.arch/arm-disassembler-options.exp: Likewise. * gdb.arch/powerpc-disassembler-options.exp: Likewise. * gdb.arch/s390-disassembler-options.exp: Likewise.
2017-01-18[ARM] Fix the decoding of indexed element VCMLA instructionSzabolcs Nagy1-4/+4
Bit 24 of the indexed element vcmla decode mask was incorrectly left unset. This could cause incorrect disassembly of some currently undefined instructions as vcmla. Rotatation immediates were not printed correctly in the disassembly (could print 170 and 280 instead of 180 and 270). opcodes/ * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly. gas/ * testsuite/gas/arm/armv8_3-a-simd.s: Add vcmla tests. * testsuite/gas/arm/armv8_3-a-simd.d: Update.
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-16Fix compile time warning building arm-dis.cNick Clifton1-2/+2
2016-12-05[ARM] Add ARMv8.3 VCMLA and VCADD instructionsSzabolcs Nagy1-0/+28
Add support for VCMLA and VCADD advanced SIMD complex number instructions. The command line option is -march=armv8.3-a+fp16+simd for enabling all instructions. In arm-dis.c the formatting syntax was abused a bit to select between 0 vs 90 or 180 vs 270 or 90 vs 270 based on a bit value instead of duplicating entries in the opcode table. gas/ * config/tc-arm.c (do_vcmla, do_vcadd): Define. (neon_scalar_for_vcmla): Define. (enum operand_parse_code): Add OP_IROT1 and OP_IROT2. (NEON_ENC_TAB): Add DDSI and QQSI variants. (insns): Add vcmla and vcadd. * testsuite/gas/arm/armv8_3-a-simd.d: New. * testsuite/gas/arm/armv8_3-a-simd.s: New. * testsuite/gas/arm/armv8_3-a-simd-bad.d: New. * testsuite/gas/arm/armv8_3-a-simd-bad.l: New. * testsuite/gas/arm/armv8_3-a-simd-bad.s: New. opcodes/ * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd. (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
2016-12-05[ARM] Add ARMv8.3 VJCVT instructionSzabolcs Nagy1-0/+4
Add support for VJCVT javascript conversion instruction. gas/ * config/tc-arm.c (arm_ext_v8_3, do_vjcvt): Define. (insns): Add vjcvt. * testsuite/gas/aarch64/armv8_3-a-fp.s: New. * testsuite/gas/aarch64/armv8_3-a-fp.d: New. * testsuite/gas/aarch64/armv8_3-a-fp-bad.s: New. * testsuite/gas/aarch64/armv8_3-a-fp-bad.d: New. * testsuite/gas/aarch64/armv8_3-a-fp-bad.l: New. opcodes/ * arm-dis.c (coprocessor_opcodes): Add vjcvt.
2016-10-06-Wimplicit-fallthrough warning fixesAlan Modra1-0/+1
Comment changes. bfd/ * coff-h8300.c: Spell fall through comments consistently. * coffgen.c: Likewise. * elf32-hppa.c: Likewise. * elf32-ppc.c: Likewise. * elf32-score.c: Likewise. * elf32-score7.c: Likewise. * elf64-ppc.c: Likewise. * elfxx-aarch64.c: Likewise. * elfxx-mips.c: Likewise. * cpu-ns32k.c: Add missing fall through comments. * elf-m10300.c: Likewise. * elf32-arm.c: Likewise. * elf32-avr.c: Likewise. * elf32-bfin.c: Likewise. * elf32-frv.c: Likewise. * elf32-i386.c: Likewise. * elf32-microblaze.c: Likewise. * elf32-nds32.c: Likewise. * elf32-ppc.c: Likewise. * elf32-rl78.c: Likewise. * elf32-rx.c: Likewise. * elf32-s390.c: Likewise. * elf32-sh.c: Likewise. * elf32-tic6x.c: Likewise. * elf64-ia64-vms.c: Likewise. * elf64-ppc.c: Likewise. * elf64-s390.c: Likewise. * elf64-x86-64.c: Likewise. * elflink.c: Likewise. * elfnn-aarch64.c: Likewise. * elfnn-ia64.c: Likewise. * ieee.c: Likewise. * oasys.c: Likewise. * pdp11.c: Likewise. * srec.c: Likewise. * versados.c: Likewise. opcodes/ * aarch64-opc.c: Spell fall through comments consistently. * i386-dis.c: Likewise. * aarch64-dis.c: Add missing fall through comments. * aarch64-opc.c: Likewise. * arc-dis.c: Likewise. * arm-dis.c: Likewise. * i386-dis.c: Likewise. * m68k-dis.c: Likewise. * mep-asm.c: Likewise. * ns32k-dis.c: Likewise. * sh-dis.c: Likewise. * tic4x-dis.c: Likewise. * tic6x-dis.c: Likewise. * vax-dis.c: Likewise. binutils/ * dlltool.c: Spell fall through comments consistently. * objcopy.c: Likewise. * readelf.c: Likewise. * dwarf.c: Add missing fall through comments. * elfcomm.c: Likewise. * sysinfo.y: Likewise. * readelf.c: Likewise. Also remove extraneous comments. gas/ * app.c: Add missing fall through comments. * dw2gencfi.c: Likewise. * expr.c: Likewise. * config/tc-alpha.c: Likewise. * config/tc-arc.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-crx.c: Likewise. * config/tc-dlx.c: Likewise. * config/tc-h8300.c: Likewise. * config/tc-hppa.c: Likewise. * config/tc-i370.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-i960.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-m68hc11.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-metag.c: Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mips.c: Likewise. * config/tc-ns32k.c: Likewise. * config/tc-rx.c: Likewise. * config/tc-score.c: Likewise. * config/tc-score7.c: Likewise. * config/tc-sh.c: Likewise. * config/tc-tic4x.c: Likewise. * config/tc-vax.c: Likewise. * config/tc-xstormy16.c: Likewise. * config/tc-z80.c: Likewise. * config/tc-z8k.c: Likewise. * config/obj-elf.c: Likewise. * config/tc-i386.c: Likewise. * depend.c: Spell fall through comments consistently. * config/tc-arm.c: Likewise. * config/tc-d10v.c: Likewise. * config/tc-i960.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-mcore.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-ns32k.c: Likewise. * config/tc-visium.c: Likewise. * config/tc-xstormy16.c: Likewise. * config/tc-z8k.c: Likewise. gprof/ * gprof.c: Add missing fall through comments. ld/ * lexsup.c: Spell fall through comments consistently and add missing fall through comments.
2016-08-26Add missing ARMv8-M special registersThomas Preud'homme1-14/+23
2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (v7m_psrs): Add MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS, FAULTMASK_NS, CONTROL_NS, SP_NS and their lowecase counterpart special registers. Write register identifier in hex. * testsuite/gas/arm/archv8m-cmse-msr.s: Reorganize tests per operation, special register and then case. Use different register for each operation. Add tests for new special registers. * testsuite/gas/arm/archv8m-cmse-msr-base.d: Adapt expected result accordingly. * testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise. opcodes/ * arm-dis.c (psr_name): Use hex as case labels. Add detection for MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS, FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
2016-06-30Fix typo in commentYao Qi1-1/+1
This patch fixes the typo "uf" in the comment. I'll push it in as the change is obvious. 2016-06-30 Yao Qi <yao.qi@linaro.org> * arm-dis.c (print_insn): Fix typo in comment.
2016-06-07[ARM] Add command line option for RAS extension.Matthew Wahab1-2/+2
This patch adds the architecture extension "+ras" to enable RAS support. It is enabled by default for -march=armv8.2-a and available but disabled by default for armv8-a and armv8.1-a. gas/ * config/tc-arm.c (arm_ext_v8_2): Rename to arm_ext_ras. (arm_ext_ras): Renamed from arm_ext_v8_2. (insns): Update for arm_ext_v8_2 renaming. (arm_extensions): Add "ras". * doc/c-arm.texi (ARM Options): Add an entry for "ras". * testsuite/gas/arm/armv8-a+ras.d: New. * testsuite/gas/arm/armv8_2-a.d: Add explicit command line options. include/ * opcode/arm.h (ARM_EXT2_RAS): New. Also align preceding entries. (ARM_AEXT_V8_2A): Add ARM_EXT2_RAS. opcodes/ * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with ARM_EXT_RAS in relevant entries.
2016-05-10Use getters/setters to access ARM branch typeThomas Preud'homme1-4/+5
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ * elf32-arm.c (elf32_arm_size_stubs): Use new macros ARM_GET_SYM_BRANCH_TYPE and ARM_SET_SYM_BRANCH_TYPE to respectively get and set branch type of a symbol. (bfd_elf32_arm_process_before_allocation): Likewise. (elf32_arm_relocate_section): Likewise and fix identation along the way. (allocate_dynrelocs_for_symbol): Likewise. (elf32_arm_finish_dynamic_symbol): Likewise. (elf32_arm_swap_symbol_in): Likewise. (elf32_arm_swap_symbol_out): Likewise. gas/ * config/tc-arm.c (arm_adjust_symtab): Use ARM_SET_SYM_BRANCH_TYPE to set branch type of a symbol. gdb/ * arm-tdep.c (arm_elf_make_msymbol_special): Use ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol. include/ * arm.h (enum arm_st_branch_type): Add new ST_BRANCH_ENUM_SIZE enumerator. (NUM_ENUM_ARM_ST_BRANCH_TYPE_BITS): New macro. (ENUM_ARM_ST_BRANCH_TYPE_BITMASK): Likewise. (ARM_SYM_BRANCH_TYPE): Replace by ... (ARM_GET_SYM_BRANCH_TYPE): This and ... (ARM_SET_SYM_BRANCH_TYPE): This in two versions depending on whether BFD_ASSERT is defined or not. ld/ * emultempl/armelf.em (gld${EMULATION_NAME}_finish): Use ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol. opcodes/ * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol. (print_insn): Likewise.
2016-05-10Add support for ARMv8-M security extensions instructionsThomas Preud'homme1-1/+18
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (arm_ext_m): Add feature bit ARM_EXT2_V8M_MAIN. (arm_ext_v8m_main): New feature set for bit ARM_EXT2_V8M_MAIN. (arm_ext_v8m_m_only): New feature set for instructions in ARMv8-M not shared with a non M profile architecture. (do_rn): New function. (known_t32_only_insn): Check opcode against arm_ext_v8m_m_only rather than arm_ext_v8m. (v7m_psrs): Add ARMv8-M security extensions new special registers. (insns): Add ARMv8-M Security Extensions instructions. (aeabi_set_public_attributes): Use arm_ext_v8m_m_only instead of arm_ext_v8m_m to decide the profile and the Thumb ISA. * testsuite/gas/arm/archv8m-cmse.s: New file. * testsuite/gas/arm/archv8m-cmse-main.s: Likewise.. * testsuite/gas/arm/archv8m-cmse-msr.s: Likewise. * testsuite/gas/arm/any-cmse.d: Likewise. * testsuite/gas/arm/any-cmse-main.d: Likewise. * testsuite/gas/arm/archv8m-cmse-base.d: Likewise. * testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise. * testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise. * testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise. * testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise. include/ * opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit. (ARM_AEXT2_V8M_MAIN): New architecture extension feature set. (ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M for the high core bits. opcodes/ * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M Mainline Security Extensions instructions. (thumb_opcodes): Add entries for narrow ARMv8-M Security Extensions instructions. (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions instructions. (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions special registers.
2016-04-05[ARM] Add ARMv8.2 FP16 vmul/vmla/vmls (by scalar)Jiong Wang1-6/+18
gas/ * config/tc-arm.c (do_neon_mac_maybe_scalar): Allow F16. * testsuite/gas/arm/armv8-2-fp16-simd.s: New tests. * testsuite/gas/arm/armv8-2-fp16-simd.d: New expected results. * testsuite/gas/arm/armv8-2-fp16-simd-thum.d: Likewise for Thumb. * testsuite/gas/arm/armv8-2-fp16-simd-warning.l: New warning results. * testsuite/gas/arm/simd_by_scalar_low_regbank.s: New test source. * testsuite/gas/arm/simd_by_scalar_low_regbank.d: New testcase. * testsuite/gas/arm/simd_by_scalar_low_regbank_thumb.d: Likewise for Thumb. * testsuite/gas/arm/simd_by_scalar_low_regbank.l: New warning results. opcodes/ * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
2016-03-16[ARM] Support ARMv8.2 FP16 simd instructionsJiong Wang1-23/+81
gas/ * config/tc-arm.c (N_S_32): New. (N_F_16_32): Likewise. (N_SUF_32): Support N_F16. (N_IF_32): Likewise. (neon_dyadic_misc): Likewise. (do_neon_cmp): Likewise. (do_neon_cmp_inv): Likewise. (do_neon_mul): Likewise. (do_neon_fcmp_absolute): Likewise. (do_neon_step): Likewise. (do_neon_abs_neg): Likewise. (CVT_FLAVOR_VAR): Likewise. (do_neon_cvt_1): Likewise. (do_neon_recip_est): Likewise. (do_vmaxnm): Likewise. (do_vrint_1): Likewise. (neon_check_type): Check architecture support for FP16 extension. (insns): Update comments. * testsuite/gas/arm/armv8-2-fp16-simd.s: New test source. * testsuite/gas/arm/armv8-2-fp16-simd.d: New testcase for arm mode. * testsuite/gas/arm/armv8-2-fp16-simd-thumb.d: Likewise for thumb mode. * testsuite/gas/arm/armv8-2-fp16-simd-warning.d: New rejection test for arm mode. * testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb.d: Likewise for thumb mode. * testsuite/gas/arm/armv8-2-fp16-simd-warning.l: New expected rejection error file. opcode/ * arm-dis.c (neon_opcodes): Support new FP16 instructions.
2016-02-24[OPCODES][ARM][1/3]Add armv8.2 fp16 instruction dissembler support.Renlin Li1-4/+87
opcodes/ 2016-02-24 Renlin Li <renlin.li@arm.com> * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries. (print_insn_coprocessor): Support fp16 instruction. gas/ 2016-02-24 Renlin Li <renlin.li@arm.com> * testsuite/gas/arm/copro.d: Adjust output. * testsuite/gas/arm/copro.s: Adjust co-processor num.
2016-02-24[OPCODES][ARM]Fix mask for a few coprocessor opcodes.Renlin Li1-8/+8
opcodes/ 2016-02-24 Renlin Li <renlin.li@arm.com> * arm-dis.c (coprocessor_opcodes): Fix mask for vsel, vmaxnm, vminnm, vrint(mpna). gas/ 2016-02-24 Renlin Li <renlin.li@arm.com> * testsuite/gas/arm/mask_1.d: New. * testsuite/gas/arm/mask_1.s: New.
2016-02-24[OPCODE][ARM]Correct disassembler for cdp/cdp2, mcr/mcr2, mrc/mrc2, ↵Renlin Li1-0/+23
ldc/ldc2, stc/stc2 opcodes/ 2016-02-24 Renlin Li <renlin.li@arm.com> * arm-dis.c (print_insn_coprocessor): Check co-processor number for cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2. gas/ 2016-02-24 Renlin Li <renlin.li@arm.com> * testsuite/gas/arm/copro.s: Use coprocessor other than 10, 11. * testsuite/gas/arm/copro.d: Update.
2016-01-25[PATCH[ARM]Check mapping symbol while backward searching for IT block.Renlin Li1-3/+78
opcodes/ * arm-dis.c (mapping_symbol_for_insn): New function. (find_ifthen_state): Call mapping_symbol_for_insn(). gas/ * testsuite/gas/arm/thumb2_it_search.d: New. * testsuite/gas/arm/thumb2_it_search.s: New.
2016-01-12[ARM] Support ARMv8.2 RAS extension.Matthew Wahab1-0/+8
The ARMv8.2 architecture includes the RAS extension which adds an instruction, ESB, and a number of coprocessor registers. This patch adds the instruction to binutils, making it available when -march=armv8.2-a is selected. It also adds tests for the instruction and for the coprocessor registers. gas/ 2016-01-12 Matthew Wahab <matthew.wahab@arm.com> * config/tc-arm.c (arm_ext_v8_2): New. (insns): Add "esb". * testsuite/gas/arm/armv8_2-a.d: New. * testsuite/gas/arm/armv8_2-a.s: New. opcodes/ 2016-01-12 Matthew Wahab <matthew.wahab@arm.com> * arm-dis.c (arm_opcodes): Add "esb". (thumb_opcodes): Likewise. Change-Id: I67f3d70789db78d1c66a56c4994675f99ac15e34
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-12-24Add assembler support for ARMv8-M BaselineThomas Preud'homme1-13/+15
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ (tag_cpu_arch_combine): Adjust comment in v4t_plus_v6_m with regards to merging with ARMv8-M Baseline. binutils/ * readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Baseline Tag_CPU_arch value. gas/ * config/tc-arm.c (arm_ext_v6t2_v8m): New feature for instructions shared between ARMv6T2 and ARMv8-M. (move_or_literal_pool): Check mov.w/mvn and movw availability against arm_ext_v6t2 and arm_ext_v6t2_v8m respectively instead of checking arm_arch_t2. (do_t_branch): Error out for wide conditional branch instructions if targetting ARMv8-M Baseline. (non_v6t2_wide_only_insn): Add the logic for new wide-only instructions in ARMv8-M Baseline. (wide_insn_ok): New function. (md_assemble): Use wide_insn_ok instead of non_v6t2_wide_only_insn and adapt error message for unsupported wide instruction to ARMv8-M Baseline. (insns): Reorganize instructions shared by ARMv8-M Baseline and ARMv6t2 architecture. (arm_cpus): Set feature bit ARM_EXT2_V6T2_V8M for marvell-pj4 and marvell-whitney cores. (arm_archs): Define armv8-m.base architecture. (cpu_arch_ver): Define ARM_ARCH_V8M_BASE architecture version. (aeabi_set_public_attributes): Add logic to set Tag_CPU_arch to 17 for ARMv8-M Mainline. Set Tag_DIV_use for ARMv8-M Baseline as well. gas/testsuite/ * gas/arm/archv8m-base.d: New file. * gas/arm/attr-march-armv8m.base.d: Likewise. * gas/arm/armv8m.base-idiv.d: Likewise. * gas/arm/any-armv8m.d: Adapt to deal with ARMv8-M Baseline. include/elf/ * arm.h (TAG_CPU_ARCH_V8M_BASE): Declare. include/opcode/ * arm.h (ARM_EXT2_V6T2_V8M): New extension bit. (ARM_AEXT2_V8A): New architecture extension bitfield. (ARM_AEXT2_V8_1A): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS. (ARM_AEXT_V8M_BASE): New architecture extension bitfield. (ARM_AEXT2_V8M): Add extension bit ARM_EXT2_V6T2_V8M. (ARM_ARCH_V6T2): Use ARM_EXT2_V6T2_V8M for the second extension bitfield. (ARM_ARCH_V6KT2): Likewise. (ARM_ARCH_V6ZT2): Likewise. (ARM_ARCH_V6KZT2): Likewise. (ARM_ARCH_V7): Likewise. (ARM_ARCH_V7A): Likewise. (ARM_ARCH_V7VE): Likewise. (ARM_ARCH_V7R): Likewise. (ARM_ARCH_V7M): Likewise. (ARM_ARCH_V7EM): Likewise. (ARM_ARCH_V8A): Likewise. (ARM_ARCH_V8M_BASE): New architecture bitfield. (ARM_ARCH_THUMB2): Include instructions shared by ARMv6t2 and ARMv8-M. (ARM_ARCH_V7A_SEC): Use ARM_EXT2_V6T2_V8M for the second extension bitfield and reindent. (ARM_ARCH_V7A_MP_SEC): Likewise. (ARM_ARCH_V7R_IDIV): Likewise. (ARM_ARCH_V8A_FP): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS. (ARM_ARCH_V8A_SIMD): Likewise. (ARM_ARCH_V8A_CRYPTOV1): Likewise. opcodes/ * arm-dis.c (arm_opcodes): Guard movw, movt cbz, cbnz, clrex, ldrex, ldrexb, ldrexh, strex, strexb, strexh shared by ARMv6T2 and ARMv8-M by ARM_EXT2_V6T2_V8M instead of ARM_EXT_V6T2.
2015-12-24Add assembler support for ARMv8-M MainlineThomas Preud'homme1-12/+18
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ (tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in comb array. binutils/ * readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch value. (arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use value. gas/ * config/tc-arm.c (arm_ext_m): Include ARMv8-M. (arm_ext_v8m): New feature for ARMv8-M. (arm_ext_atomics): New feature for ARMv8 atomics. (do_tt): New encoding function for TT* instructions. (insns): Add new entries for ARMv8-M specific instructions and reorganize the ones shared by ARMv8-M Mainline and ARMv8-A. (arm_archs): Define armv8-m.main architecture. (cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and clarify the ordering rule. (aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile to 'A' if extension bit for atomic instructions is set, unless it is ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0 for ARMv8-M Mainline. gas/testsuite/ * gas/arm/archv8m.s: New file. * gas/arm/archv8m-main.d: Likewise. * gas/arm/attr-march-armv8m.main.d: Likewise. * gas/arm/any-armv8m.s: Likewise. * gas/arm/any-armv8m.d: Likewise. include/elf/ * arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare. (MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN. (TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15. include/opcode/ * arm.h (ARM_EXT2_ATOMICS): New extension bit. (ARM_EXT2_V8M): Likewise. (ARM_EXT_V8): Adjust comment with regards to atomics and remove mention of legacy use for that bit. (ARM_AEXT2_V8_1A): New architecture extension bitfield. (ARM_AEXT2_V8_2A): Likewise. (ARM_AEXT_V8M_MAIN): Likewise. (ARM_AEXT2_V8M): Likewise. (ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield. (ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A. (ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A. (ARM_ARCH_V8M_MAIN): New architecture feature bitfield. (ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield and reindent. (ARM_ARCH_V8A_SIMD): Likewise. (ARM_ARCH_V8A_CRYPTOV1): Likewise. (ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of feature bits. (ARM_ARCH_V8_1A_SIMD): Likewise. (ARM_ARCH_V8_1A_CRYPTOV1): Likewise. opcodes/ * arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl, stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of ARM_EXT_V8. (thumb32_opcodes): Add entries for wide ARMv8-M instructions.
2015-12-02Fix ldah being disassembled as ldaexhAndre Vieira1-1/+1
2015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> opcodes/ * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo... <ldah>: ... to this. gas/testsuite/ * gas/arm/armv8-a.d: <ldaexh>: Rename mismatched mnemonics ... <ldah>: ... to this.
2015-11-23opcodes: handle mach-o for thumb/arm disambiguation.Tristan Gingold1-0/+8
opcodes/ * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
2015-08-13Fixes for unpredictable nops and 26-bit versions of teq,tst,cmn,cmp.Andre Vieira1-3/+11
opcodes * arm-dis.c (print_insn_arm): Disassembling for all targets V6 and higher with ARM instruction set will now mark the 26-bit versions of teq,tst,cmn and cmp as UNPREDICTABLE. (arm_opcodes): Fix for unpredictable nop being recognized as a teq. test * gas/arm/nops.d: New. * gas/arm/nops.s: New. * gas/arm/inst.d: Changed expectation file for 26-bit teq, tst, cmn and cmp.
2015-08-12Remove trailing spaces in opcodesH.J. Lu1-57/+57
2015-07-16Updates the ARM disassembler's output of floating point constants to include ↵Alessandro Marzocchi1-2/+33
the actual floating point value. opcodes * arm-dis.c (print_insn_coprocessor): Added support for quarter float bitfield format. (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new quarter float bitfield format. tests * gas/arm/vfpv3-const-conv.d: Update expected result due to change of comment for vmov reg,immediate with VFP coprocessor.
2015-06-16Fixes a compile time warnng about left shifting a negative value.Szabolcs Nagy1-1/+1
* arm-dis.c (print_insn_coprocessor): Avoid negative shift.
2015-06-02[ARM] Support for ARMv8.1 Adv.SIMD extensionMatthew Wahab1-0/+19
2015-06-02[ARM] Add support for ARMv8.1 PAN extensionMatthew Wahab1-0/+5
2015-06-02[ARM] Rework CPU feature selection in the disassemblerMatthew Wahab1-29/+26
include/opcode/ * arm.h (ARM_FEATURE_ALL): New. opcodes/ * arm-dis.c (select_arm_features): Rework to avoid used of redefined macros.
2015-04-15[ARM] Disassembles SSAT and SSAT16 instructions incorrectly for Thumb-2Renlin Li1-2/+8
2015-04-15 Renlin Li <renlin.li@arm.com> opcodes/: * arm-dis.c (thumb32_opcodes): Define 'D' format control code, use it for ssat and ssat16. (print_insn_thumb32): Add handle case for 'D' control code. gas/testsuite/: * gas/arm/arch7em.d: Adjust required ssat and ssat16 immediate field. * gas/arm/thumb32.d: Likewise.
2015-03-24Extend arm_feature_set struct to provide more bitsTerry Guo1-1294/+2530
gas/ChangeLog: 2015-03-24 Terry Guo <terry.guo@arm.com> * config/tc-arm.c (no_cpu_selected): Use new macro to compare features. (parse_psr): Likewise. (do_t_mrs): Likewise. (do_t_msr): Likewise. (static const arm_feature_set arm_ext_*): Defined with new macros. (static const arm_feature_set arm_cext_*): Likewise. (static const arm_feature_set fpu_fpa_ext_*): Likewise. (static const arm_feature_set fpu_vfp_ext_*): Likewise. (deprecated_coproc_regs): Likewise. (UL_BARRIER): Likewise. (barrier_opt_names): Likewise. (arm_cpus): Likewise. (arm_extensions): Likewise. include/opcode/ChangeLog: 2015-03-24 Terry Guo <terry.guo@arm.com> * arm.h (arm_feature_set): Extended to provide more available * bits. (ARM_ANY): Updated to follow above new definition. (ARM_CPU_HAS_FEATURE): Likewise. (ARM_CPU_IS_ANY): Likewise. (ARM_MERGE_FEATURE_SETS): Likewise. (ARM_CLEAR_FEATURE): Likewise. (ARM_FEATURE): Likewise. (ARM_FEATURE_COPY): New macro. (ARM_FEATURE_EQUAL): Likewise. (ARM_FEATURE_ZERO): Likewise. (ARM_FEATURE_CORE_EQUAL): Likewise. (ARM_FEATURE_LOW): Likewise. (ARM_FEATURE_CORE_LOW): Likewise. (ARM_FEATURE_CORE_COPROC): Likewise. opcodes/ChangeLog: 2015-03-24 Terry Guo <terry.guo@arm.com> * arm-dis.c (opcode32): Updated to use new arm feature struct. (opcode16): Likewise. (coprocessor_opcodes): Replace bit with feature struct. (neon_opcodes): Likewise. (arm_opcodes): Likewise. (thumb_opcodes): Likewise. (thumb32_opcodes): Likewise. (print_insn_coprocessor): Likewise. (print_insn_arm): Likewise. (select_arm_features): Follow new feature struct.
2015-03-03[ARM] Skip private symbol when doing objdumpJiong Wang1-2/+5
2015-03-03 Jiong Wang <jiong.wang@arm.com> opcode/ * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols. binutils/testsuite/ * binutils-all/arm/rvct_symbol.s: New testcase. * binutils-all/arm/objdump.exp: Run it.
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-08-22ARM/opcodes: Fix negative hexadecimal offset disassemblyMaciej W. Rozycki1-0/+2
2014-08-21 Nathan Sidwell <nathan@codesourcery.com> Maciej W. Rozycki <macro@codesourcery.com> opcodes/ * arm-dis.c (print_arm_address): Negate the GPR-relative offset returned if the U bit is set. 2014-08-21 Paul Brook <paul@codesourcery.com> gas/testsuite/ * gas/arm/arch7a-mp.d: Adjust according to `print_arm_address' offset fix. * gas/arm/arch7r-mp.d: Likewise.
2014-03-05Update copyright yearsAlan Modra1-1/+1
2013-10-15Fix neon vshll disassembly.Ramana Radhakrishnan1-3/+3
opcodes/ 2013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * arm-dis.c (neon_opcodes): Adjust print string for vshll. gas/testsuite/ 2013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * gas/arm/neon-cov.d: Adjust output.
2013-09-04 PR gas/15914Nick Clifton1-3/+16
* config/tc-arm.c (T16_32_TAB): Add _udf. (do_t_udf): New function. (insns): Add "udf". * gas/arm/udf-bad.s: New file. * gas/arm/udf-bad.d: New file. * gas/arm/udf-bad.l: New file. * gas/arm/udf.s: New file. * gas/arm/udf.d: New file. * gas/arm/udf.l: New file. * arm-dis.c (arm_opcodes): Add udf. (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION. (thumb32_opcodes): Add udf.w. (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
2013-03-11Add support for AArch32 CRC instruction in ARMv8.Kyrylo Tkachov1-1/+21
gas/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/tc-arm.c (crc_ext_armv8): New feature set. (UNPRED_REG): New macro. (do_crc32_1): New function. (do_crc32b, do_crc32h, do_crc32w, do_crc32cb, do_crc32ch, do_crc32cw): Likewise. (TUEc): New macro. (insns): Add entries for crc32 mnemonics. (arm_extensions): Add entry for crc. include/opcode/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * arm.h (CRC_EXT_ARMV8): New constant. (ARCH_CRC_ARMV8): New macro. opcodes/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * arm-dis.c (arm_opcodes): Add entries for CRC instructions. (thumb32_opcodes): Likewise. (print_insn_thumb32): Handle 'S' control char. gas/testsuite/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * gas/arm/crc32-bad.d: New file. * gas/arm/crc32-bad.l: Likewise. * gas/arm/crc32-bad.s: Likewise. * gas/arm/crc32.d: Likewise. * gas/arm/crc32.s: Likewise.
2013-02-112013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>Richard Earnshaw1-2/+2
* arm-dis.c: Update strht pattern. * gas/arm/archv6t2.s: Add strht and ldrht tests. * gas/arm/archv6t2.d: Add disassembly patterns for the above.
2012-10-112012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>Richard Earnshaw1-5/+5
* arm-dis.c: Use preferred form of vrint instruction variants for disassembly. 2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * gas/arm/armv8-a+fp.d: Use preferred form of vrint instruction variants for disassembly. * gas/arm/armv8-a+fp.s: Likewise. * gas/arm/armv8-a+simd.d: Likewise. * gas/arm/armv8-a+simd.s: Likewise.
2012-09-182012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>Richard Earnshaw1-28/+28
opcodes: * arm-dis.c: Changed ldra and strl-form mnemonics to lda and stl-form. gas: * config/tc-arm.c: Changed ldra and strl-form mnemonics to lda and stl-form for armv8. gas/testsuite: * gas/arm/armv8-a-bad.l: Updated for changed mnemonics. * gas/arm/armv8-a-bad.s: Likewise. * gas/arm/armv8-a.d: Likewise. * gas/arm/armv8-a.s: Likewise. * gas/arm/inst.s: Added test for ldrt encoding compatibly with ldralt. * gas/arm/inst.d: Updated.
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