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2009-09-02update copyright datesAlan Modra1-1/+1
2009-07-20 PR 10288Nick Clifton1-2/+4
* arm-dis.c (arm_opcodes): Catch non-zero bits 8-11 in register offset or indexed based addressing mode 3.
2009-07-14 PR 10288Nick Clifton1-18/+69
* arm-dis.c (arm_opcodes): Catch illegal Addressing Mode 1 patterns. (arm_decode_shift): Catch illegal register based shifts. (print_insn_arm): Properly handle negative register r0 post-indexed addressing.
2009-07-102009-07-10 Doug Kwan <dougkwan@google.com>Doug Kwan1-3/+3
* arm-disc.c (print_insn_coprocessor, print_insn_arm): Print only lower 32 bits of long types to make hexadecimal output consistent on both 32-bit and 64-bit hosts.
2009-07-07gas/Nick Clifton1-2/+2
* config/tc-arm.c (insns): Fix encoding for torvsc. gas/testsuite/ * gas/arm/iwmmxt2.d: Fix insn pattern for torvsc, add patterns for waddsubhx. * gas/arm/iwmmxt2.s: Add tests for waddsubhx. opcodes/ * arm-dis.c (coprocessor_opcodes): Fix mask for waddbhus.
2009-07-07 PR 10288Nick Clifton1-6/+7
* arm-dis.c (arm_opcodes): Be more strict about decoding scaled addressing modes.
2009-06-30 PR 10288Nick Clifton1-103/+133
* arm-dis.c (coprocessor): Print the LDC and STC versions of the LFM and SFM instructions as comments,. Improve consistency of formatting for instructions displayed as comments and decimal values displayed with their hexadecimal equivalents. Formatting tidy ups. Updated expected disassembler regexps.
2009-06-29 PR 10288Nick Clifton1-106/+210
* arm-dis.c (enum opcode_sentinels): New: Used to mark the boundary between variaant and generic coprocessor instuctions. (coprocessor): Use it. Fix architecture version of MCRR and MRRC instructions. (arm_opcdes): Fix patterns for STRB and STRH instructions. (print_insn_coprocessor): Check architecture and extension masks. Print a hexadecimal version of any decimal constant that is outside of the range of -16 to +32. (print_arm_address): Add a return value of the offset used in the adress, if it is worth printing a hexadecimal version of it. (print_insn_neon): Print a hexadecimal version of any decimal constant that is outside of the range of -16 to +32. (print_insn_arm): Likewise. (print_insn_thumb16): Likewise. (print_insn_thumb32): Likewise. PR 10297 * arm-dis.c (UNDEFINED_INSTRUCTION): New macro for a description of an undefined instruction. (arm_opcodes): Use it. (thumb_opcod): Use it. (thumb32_opc): Use it. Update expected disassembly regrexps in GAS and LD testsuites.
2009-06-18 PR 10288Nick Clifton1-383/+465
* arm-dis.c (print_insn_coprocessor): Check that a user specified ARM architecture supports the matched instruction. (print_insn_arm): Likewise. (select_arm_features): New function. Fills in the fields of an arm_feature_set structure based on a given arm machine number. (print_insn): Initialise an arm_feature_set structure. * objdump.c (disassemble_bytes): Set the USER_SPECIFIED_MACHINE_TYPE flag in the disassemble_info structure if the user has invoked the -m switch. * doc/binutils.texi: Document the additional behaviour of objdump's -m switch for ARM targets. * dis-asm.h (USER_SPECIFIED_MACHINE_TYPE): New value for the flags field of struct disassemble_info. * gas/arm/align.s: Add labels so that COFF based targets can correctly locate THUMB code. * gas/arm/copro.d: Do not pass --architecture switch to objdump.
2009-06-15 PR 10186Nick Clifton1-1/+1
* arm-dis.c (thumb32_opcodes): Fix binary value of SEV.W instruction. * gas/arm/thumb32.d: Fix expected binary value of SEV.W instruction. * config/tc-arm.c (T16_32_TAB): Fix binary value of SEV.W instruction.
2009-06-15 PR 10263Nick Clifton1-4/+5
* arm-dis.c (print_insn): Ignore is_data if the user has requested the disassembly of data as well as instructions. * objdump.c (disassemble_bytes): Set the DISASSEMBLE_DATA bit in the flags field of the disassemble_info structure if the -D switch is in operation. * dis-asm.h (struct disassemble_info): New value for the flags field.
2009-04-012009-04-01 Christophe Lyon <christophe.lyon@st.com>Christophe Lyon1-1/+5
opcodes/ * arm-dis.c (print_insn): Print BE8 opcodes in little endianness. ld/testsuite/ * ld-arm/arm-elf.exp: BE8 tests expect the same output as the default ones. * ld-arm/arm-be8.d: Print opcodes in little endian. * ld-arm/farcall-thumb-arm-be8.d: Removed useless expected result. * ld-arm/farcall-arm-arm-be8.d: Likewise.
2009-03-30gas/testsuite:Joseph Myers1-1/+3
* gas/arm/mapsecs.d, gas/arm/mapsecs.s: New. opcodes: * arm-dis.c (print_insn): Also check section matches in backwards search for mapping symbol.
2009-02-23 * arm-dis.c (neon_opcodes): Correct bit-mask and patterns forRichard Earnshaw1-4/+4
vq{r}shr{u}n.s64 insnstructions.
2009-01-29gas:Joseph Myers1-4/+4
2009-01-29 Mark Mitchell <mark@codesourcery.com> * config/tc-arm.c (insns): Correct encoding of qadd, qdadd, qsub, qdsub in Thumb-2 mode. gas/testsuite: 2009-01-29 Mark Mitchell <mark@codesourcery.com> * gas/arm/thumb32.s (qadd): Add qadd, qdadd, qsub, and qdsub. * gas/arm/thumb32.d: Likewise. opcodes: 2009-01-29 Mark Mitchell <mark@codesourcery.com> * arm-dis.c (thumb32_opcodes): Correct decoding for qadd, qdadd, qsub, and qdsub.
2008-12-15opcodes:Richard Earnshaw1-93/+90
* arm-dis.c (coprocessor_opcodes): Disassemble VFP instructions using unified syntax. gas/testsuite: * gas/arm/group-reloc-ldc.d: Disassembly of VFP instructions now uses unified syntax. * gas/arm/vfp-non-overlap.d: Likewise. * gas/arm/vfp-neon-syntax.d: Likewise. * gas/arm/vfp-neon-syntax_t2.d: Likewise. * gas/arm/vfp1.d: Likewise. * gas/arm/vfp1_t2.d: Likewise. * gas/arm/vfp1xD.d: Likewise. * gas/arm/vfp1xD_t2.d: Likewise. * gas/arm/vfp2.d: Likewise. * gas/arm/vfp2_t2.d: Likewise. * gas/arm/vfpv3-32drs.d: Likewise. * gas/arm/vfpv3-const-conv.d: Likewise. ld/testsuite: * ld-arm/vfp11-fix-scalar.d: Disassembly of VFP instructions now uses unified syntax. * ld-arm/vfp11-fix-vector.d: Likewise.
2008-11-18Add support for ARM half-precision conversion instructions.Catherine Moore1-0/+7
2008-07-072008-07-07 Stan Shebs <stan@codesourcery.com>Stan Shebs1-4/+15
* dis-init.c (init_disassemble_info): Init endian_code field. * arm-dis.c (print_insn): Disassemble code according to setting of endian_code. (print_insn_big_arm): Detect when BE8 extension flag has been set.
2007-11-07* arm-dis.c (arm_opcodes): Remove superflous escapes of percent operators.Nick Clifton1-4/+4
2007-10-26* arm-dis.c (print_insn): Check for a symtab that exists but is empty.Nick Clifton1-0/+1
2007-07-05Change source files over to GPLv3.Nick Clifton1-9/+10
2007-06-262007-06-26 Paul Brook <paul@codesourcery.com>Paul Brook1-0/+4
gas/ * config/tc-arm.c (parse_operands): Accept generic coprocessor regs for OP_RVC. (reg_names): Add fpinst, pfinst2, mvfr0 and mvfr1. gas/testsuite/ * gas/arm/vfp1xD.d: Add new fmrx/fmxr tests. * gas/arm/vfp1xD.s: Ditto. * gas/arm/vfp1xD_t2.d: Ditto. * gas/arm/vfp1xD_t2.s: Ditto. opcodes/ * arm-dis.c (coprocessor_opcodes): Add fmxr/fmrx mvfr0/mvfr1.
2007-06-052007-06-05 Paul Brook <paul@codesourcery.com>Paul Brook1-2/+4
gas/ * config/tc-arm.c (insns): Correct Thumb-2 ldrd/strd opcodes. gas/testsuite/ * gas/arm/thumb32.d: Add writeback addressing mode tests. * gas/arm/thumb32.s: Update expected output. opcodes/ * arm-dis.c (thumb32_opcodes): Display writeback ldrd/strd addresses.
2007-04-24Fix compile time warning (at -O3 with gcc 4.1.2)Nick Clifton1-1/+1
2007-04-21 * arm-dis.c (arm_opcodes): Disassemble to unified syntax.Richard Earnshaw1-90/+113
(thumb_opcodes): Add missing white space in adr. (arm_decode_shift): New parameter, print_shift. Only decode the shift parameter if set. Adjust callers. (print_insn_arm): Support for operand type q with no shift decode.
2007-04-20 * arm-dis.c (print_insn): Only look for a mapping symbol in the sectionRichard Earnshaw1-2/+4
being disassembled.
2007-03-272006-03-27 Paul Brook <paul@codesourcery.com>Paul Brook1-0/+1
opcodes/ * arm-dis.c (thumb_opcodes): Add entry for undefined insns (0xbe??).
2007-03-242007-03-24 Paul Brook <paul@codesourcery.com>Paul Brook1-2/+7
opcodes/ * arm-dis.c (coprocessor_opcodes): Remove superfluous 0x. (print_insn_coprocessor): Handle %<bitfield>x.
2007-03-242007-03-24 Paul Brook <paul@codesourcery.com>Paul Brook1-3/+3
Mark Shinwell <shinwell@codesourcery.com> gas/ * config/tc-arm.c (operand_parse_code): Add OP_oRRw. (parse_operands): Don't expect comma if first operand missing. Handle OP_oRRw. (do_srs): Encode register number, checking it is r13. Update comment. (insns): Update SRS entries to take a register. gas/testsuite/ * gas/arm/archv6.s: Add new SRS tests. * gas/arm/archv6.d: Update expected output. * gas/arm/thumb32.s: Add new SRS tests. * gas/arm/thumb32.d: Update expected output. * gas/arm/srs-t2.d: New. * gas/arm/srs-t2.l: New. * gas/arm/srs-t2.s: New. * gas/arm/srs-arm.d: New. * gas/arm/srs-arm.l: New. * gas/arm/srs-arm.s: New. opcodes/ * arm-dis.c (arm_opcodes): Print SRS base register.
2007-01-042007-01-04 Paul Brook <paul@codesourcery.com>Paul Brook1-4/+4
gas/ * config/tc-arm.c (do_cpsi): Set mmod bit for 2 argument form. gas/testsuite/ * gas/arm/archv6.s: Add more cpsie tests. * gas/arm/archv6.d: Ditto. opcodes/ * arm-dis.c (arm_opcodes): Fix cpsie and cpsid entries.
2007-01-04 * arm-dis.c (neon_opcode): Fix disassembly for vshl, vqshl, vrshl,Julian Brown1-4/+4
vqrshl instructions.
2006-11-292006-11-29 Paul Brook <paul@codesourcery.com>Paul Brook1-2/+2
gas/ * config/tc-arm.c (do_vfp_sp_const, do_vfp_dp_const): Fix operans encoding. gas/testsuite/ * gas/arm/vfpv3-const-conv.s: Improve test coverage. * gas/arm/vfpv3-const-conv.d: Adjust expected output. * gas/arm/vfp-neon-syntax_t2.d: Ditto. * gas/arm/vfp-neon-syntax.d: Ditto. opcodes/ * arm-dis.c (coprocessor_opcodes): Fix bitfields for fconstd/fconstd.
2006-11-22opcodes/Daniel Jacobowitz1-76/+154
* arm-dis.c (last_is_thumb): Delete. (enum map_type, last_type): New. (print_insn_data): New. (get_sym_code_type): Take MAP_TYPE argument. Check the type of the right symbol. Handle $d. (print_insn): Check for mapping symbols even without a normal symbol. Adjust searching. If $d is found see how much data to print. Handle data. gas/ * config/tc-arm.h (md_cons_align): Define. (mapping_state): New prototype. * config/tc-arm.c (mapping_state): Make global. gas/testsuite/ * gas/arm/arm7t.d, gas/arm/neon-ldst-rm.d, gas/arm/thumb2_pool.d, gas/arm/tls.d: Update for $d support. * gas/arm/mapshort.d, gas/arm/mapshort.s: New test. * gas/elf/section2.e-armeabi: Update. * gas/elf/section2.e-armelf: New file. * gas/elf/elf.exp: Use it. ld/testsuite/ * ld-arm/mixed-app.d, ld-arm/tls-app.d, ld-arm/tls-lib.d: Update for $d support.
2006-10-312006-10-30 Paul Brook <paul@codesourcery.com>Paul Brook1-5/+100
binutils/ * objdump.c (disassemble_section): Set info->symtab_pos. (disassemble_data): Set info->symtab and info->symtab_size. include/ * dis-asm.h (disassemble_info): Add symtab, symtab_pos and symtab_size. opcodes/ * arm-dis.c (last_is_thumb, last_mapping_sym, last_mapping_addr): New. (get_sym_code_type): New function. (print_insn): Search for mapping symbols.
2006-09-26bfd/Joseph Myers1-12/+90
2006-09-26 Mark Shinwell <shinwell@codesourcery.com> Joseph Myers <joseph@codesourcery.com> Ian Lance Taylor <ian@wasabisystems.com> Ben Elliston <bje@wasabisystems.com> * archures.c: Add definition for bfd_mach_arm_iWMMXt2. * cpu-arm.c (processors): Add bfd_mach_arm_iWMMXt2. (arch_info_struct, bfd_arm_update_notes): Likewise. (architectures): Likewise. (bfd_arm_merge_machines): Check for iWMMXt2. * bfd-in2.h: Rebuild. gas/ 2006-09-26 Mark Shinwell <shinwell@codesourcery.com> Joseph Myers <joseph@codesourcery.com> Ian Lance Taylor <ian@wasabisystems.com> Ben Elliston <bje@wasabisystems.com> * config/tc-arm.c (arm_cext_iwmmxt2): New. (enum operand_parse_code): New code OP_RIWR_I32z. (parse_operands): Handle OP_RIWR_I32z. (do_iwmmxt_wmerge): New function. (do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is a register. (do_iwmmxt_wrwrwr_or_imm5): New function. (insns): Mark instructions as RIWR_I32z as appropriate. Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>, waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n}, wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r}, wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx. (md_begin): Handle IWMMXT2. (arm_cpus): Add iwmmxt2. (arm_extensions): Likewise. (arm_archs): Likewise. gas/testsuite/ 2006-09-26 Mark Shinwell <shinwell@codesourcery.com> Joseph Myers <joseph@codesourcery.com> Ian Lance Taylor <ian@wasabisystems.com> Ben Elliston <bje@wasabisystems.com> * gas/arm/iwmmxt2.s: New file. * gas/arm/iwmmxt2.d: New file. include/opcode/ 2006-09-26 Mark Shinwell <shinwell@codesourcery.com> Joseph Myers <joseph@codesourcery.com> Ian Lance Taylor <ian@wasabisystems.com> Ben Elliston <bje@wasabisystems.com> * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define. opcodes/ 2006-09-26 Mark Shinwell <shinwell@codesourcery.com> Joseph Myers <joseph@codesourcery.com> Ian Lance Taylor <ian@wasabisystems.com> Ben Elliston <bje@wasabisystems.com> * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may only be used with the default multiply-add operation, so if N is set, don't bother printing X. Add new iwmmxt instructions. (IWMMXT_INSN_COUNT): Update. (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14 with a 'c' suffix. (print_insn_coprocessor): Check for iWMMXt2. Handle format specifiers 'r', 'i'.
2006-09-16* bfd-in.h (STRING_AND_COMMA): New macro. Takes one constant string as itsNick Clifton1-3/+3
argument and emits the string followed by a comma and then the length of the string. (CONST_STRNEQ): New macro. Checks to see if a variable string has a constant string as its initial characters. (CONST_STRNCPY): New macro. Copies a constant string to the start of a variable string. * bfd-in2.h: Regenerate. * <remainign files>: Make use of the new macros.
2006-09-052006-09-04 Paul Brook <paul@codesourcery.com>Paul Brook1-1/+1
gas/ * config/tc-arm.c (do_neon_dyadic_if_i): Remove. (do_neon_dyadic_if_i_d): Avoid setting U bit. (do_neon_mac_maybe_scalar): Ditto. (do_neon_dyadic_narrow): Force operand type to NT_integer. (insns): Remove out of date comments. gas/testsuite/ * gas/arm/neon-cov.s: Test .u and .s aliases for .i suffixes. * gas/arm/neon-cov.d: Adjust expected output. opcodes/ * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
2006-07-192006-07-19 Paul Brook <paul@codesourcery.com>Paul Brook1-1/+1
gas/ * config/tc-arm.c (insns): Fix rbit Arm opcode. gas/testsuite/ * gas/arm/archv6t2.d: Adjust expected output for rbit. opcodes/ * armd-dis.c (arm_opcodes): Fix rbit opcode.
2006-07-05 * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.Julian Brown1-1/+1
2006-06-12 * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signedJulian Brown1-1/+3
on 64-bit hosts.
2006-06-072006-06-06 Paul Brook <paul@codesourcery.com>Paul Brook1-522/+690
opcodes/ * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm instructions. (neon_opcodes): Add conditional execution specifiers. (thumb_opcodes): Ditto. (thumb32_opcodes): Ditto. (arm_conditional): Change 0xe to "al" and add "" to end. (ifthen_state, ifthen_next_state, ifthen_address): New. (IFTHEN_COND): Define. (print_insn_coprocessor, print_insn_neon): Print thumb conditions. (print_insn_arm): Change %c to use new values of arm_conditional. (print_insn_thumb16): Print thumb conditions. Add %I. (print_insn_thumb32): Print thumb conditions. (find_ifthen_state): New function. (print_insn): Track IT block state. gas/testsuite/ * gas/arm/thumb2_bcond.d: Update expected output. * gas/arm/thumb32.d: Ditto. * gas/arm/vfp1_t2.d: Ditto. * gas/arm/vfp1xD_t2.d: Ditto. binutils/testsuite/ * binutils-all/arm/objdump.exp: New file. * binutils-all/arm/thumb2-cond.s: New test.
2006-05-05 * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx asJulian Brown1-4/+4
vldm/vstm.
2006-04-26 * arm-dis.c (print_insn_neon): Disassemble floating-point constantJulian Brown1-2/+25
VMOV.
2006-04-26 * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convertJulian Brown1-368/+1080
%<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?]. Add unified load/store instruction names. (neon_opcode_table): New. (arm_opcodes): Expand meaning of %<bitfield>['`?]. (arm_decode_bitfield): New. (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers. Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y. (print_insn_neon): New. (print_insn_arm): Adjust print_insn_coprocessor call. Call print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers. (print_insn_thumb32): Likewise.
2006-03-162006-03-16 Paul Brook <paul@codesourcery.com>Paul Brook1-2/+2
gas/ * config/tc-arm.c (insns): Add "svc". gas/testsuite/ * gas/arm/svc.d: New test. * gas/arm/svc.s: New test. * gas/arm/inst.d: Accept svc mnemonic. * gas/arm/thumb.d: Ditto. * gas/arm/wince_inst.d: Ditto. opcodes/ * arm-dis.c (arm_opcodes): Rename swi to svc. (thumb_opcodes): Ditto.
2006-02-242006-02-24 Paul Brook <paul@codesourcery.com>Paul Brook1-83/+194
gas/ * config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7, arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables. (struct asm_barrier_opt): Define. (arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables. (parse_psr): Accept V7M psr names. (parse_barrier): New function. (enum operand_parse_code): Add OP_oBARRIER. (parse_operands): Implement OP_oBARRIER. (do_barrier): New function. (do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions. (do_t_cpsi): Add V7M restrictions. (do_t_mrs, do_t_msr): Validate V7M variants. (md_assemble): Check for NULL variants. (v7m_psrs, barrier_opt_names): New tables. (insns): Add V7 instructions. Mark V6 instructions absent from V7M. (md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh. (arm_cpu_option_table): Add Cortex-M3, R4 and A8. (arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m. (struct cpu_arch_ver_table): Define. (cpu_arch_ver): New. (aeabi_set_public_attributes): Use cpu_arch_ver. Set Tag_CPU_arch_profile. * doc/c-arm.texi: Document new cpu and arch options. gas/testsuite/ * gas/arm/thumb32.d: Fix expected msr and mrs output. * gas/arm/arch7.d: New test. * gas/arm/arch7.s: New test. * gas/arm/arch7m-bad.l: New test. * gas/arm/arch7m-bad.d: New test. * gas/arm/arch7m-bad.s: New test. include/opcode/ * arm.h: Add V7 feature bits. opcodes/ * arm-dis.c (arm_opcodes): Add V7 instructions. (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants. (print_arm_address): New function. (print_insn_arm): Use it. Add 'P' and 'U' cases. (psr_name): New function. (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2005-11-022005-11-02 Paul Brook <paul@codesourcery.com>Paul Brook1-1/+6
* arm-dis.c (print_insn_thumb32): Word align blx target address.
2005-10-31 * arm-dis.c (print_insn): Warning fix.Alan Modra1-5/+5
2005-10-262005-10-26 Paul Brook <paul@codesourcery.com>Paul Brook1-1/+1
gas/ * config/tc-arm.c (insns): Correct "sel" entry. gas/testsuite/ * gas/arm/archv6.d: Adjust expected output. opcodes/ * arm-dis.c (arm_opcodes): Correct "sel" entry.
2005-10-082005-10-08 James Lemke <jim@wasabisystems.com>Richard Earnshaw1-6/+6
* arm-dis.c (coprocessor_opcodes): Fix mask for various Maverick CDP operations.
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