| Age | Commit message (Collapse) | Author | Files | Lines |
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The memory disassemble_info::disassembler_options points to is always
owned by the client. I.e., that field is an non-owning, observing
pointer. Thus const makes sense.
Are the include/ and opcodes/ bits OK?
Tested on x86_64 Fedora 23, built with --enable-targets=all.
include/ChangeLog:
2017-04-05 Pedro Alves <palves@redhat.com>
* dis-asm.h (disassemble_info) <disassembler_options>: Now a
"const char *".
(next_disassembler_option): Constify.
opcodes/ChangeLog:
2017-04-05 Pedro Alves <palves@redhat.com>
* arc-dis.c (parse_option, parse_disassembler_options): Constify.
* arm-dis.c (parse_arm_disassembler_options): Constify.
* ppc-dis.c (powerpc_init_dialect): Constify local.
* vax-dis.c (parse_disassembler_options): Constify.
gdb/ChangeLog:
2017-04-05 Pedro Alves <palves@redhat.com>
* arm-tdep.c (show_disassembly_style_sfunc): Constify local.
* disasm.c (set_disassembler_options): Constify local.
* i386-tdep.c (i386_print_insn): Remove cast and FIXME comment.
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gas/
2017-02-06 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (parse_opcode_flags): Ignore implicit flags.
include/
2017-02-06 Claudiu Zissulescu <claziss@synopsys.com>
Anton Kolesov <anton.kolesov@synopsys.com>
* opcode/arc.h (insn_class_t): Add ENTER, LEAVE, POP, PUSH, BBIT0,
BBIT1, BI, BIH, BRCC, EI, JLI, and SUB instruction classes.
(flag_class_t): Add F_CLASS_WB, F_CLASS_ZZ, and F_CLASS_IMPLICIT
flag classes.
opcode/
2017-02-06 Claudiu Zissulescu <claziss@synopsys.com>
Anton Kolesov <anton.kolesov@synopsys.com>
* arc-dis.c (arc_disassemble_info): New structure.
(init_arc_disasm_info): New function.
(find_format_from_table): Ignore implicit flags.
(find_format): Update dissassembler private data.
(print_flags): Likewise.
(print_insn_arc): Likewise.
(arc_opcode_to_insn_type): Consider the new added instruction
classes.
(arcAnalyzeInstr): Remove.
(arc_insn_decode): New function.
* arc-dis.h (arc_ldst_writeback_mode): New enum.
(arc_ldst_data_size): Likewise.
(arc_condition_code): Likewise.
(arc_operand_kind): Likewise.
(arc_insn_kind): New struct.
(arc_instruction): Likewise.
(arc_insn_decode): Declare function.
(ARC_Debugger_OperandType): Deleted.
(Flow): Likewise.
(NullifyMode): Likewise.
(allOperandsSize): Likewise.
(arcDisState): Likewise.
(arcAnalyzeInstr): Likewise.
* arc-dis.c (arc_opcode_to_insn_type): Handle newly introduced
insn_class_t enums.
* arc-opc.c (F_SIZED): New define.
(C_CC_EQ, C_CC_GE, C_CC_GT, C_CC_HI, C_CC_HS): Likewise.
(C_CC_LE, C_CC_LO, C_CC_LS, C_CC_LT, C_CC_NE): Likewise.
(C_CC_NE, C_AA_AB, C_AA_AW, C_ZZ_D, C_ZZ_H, C_ZZ_B): Likewise.
(arc_flag_classes): Add F_CLASS_COND/F_CLASS_IMPLICIT flags.
* opcodes/arc-tbl.h: Update instructions to include new
F_CLASS_IMPLICIT flags.
(bbit0, lp): Change class.
(bbit1, bi, bih, br*, ei_s, jli_s): Likewsie
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gas/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (find_opcode_match): New function argument
errmsg.
(assemble_tokens): Collect and report the eventual error message
found during opcode matching process.
* testsuite/gas/arc/lpcount-err.s: New file.
* testsuite/gas/arc/add_s-err.s: Update error message.
opcode/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (insert_ra_chk): New function.
(insert_rb_chk): Likewise.
(insert_rad): Update text error message.
(insert_rcd): Likewise.
(insert_rhv2): Likewise.
(insert_r0): Likewise.
(insert_r1): Likewise.
(insert_r2): Likewise.
(insert_r3): Likewise.
(insert_sp): Likewise.
(insert_gp): Likewise.
(insert_pcl): Likewise.
(insert_blink): Likewise.
(insert_ilink1): Likewise.
(insert_ilink2): Likewise.
(insert_ras): Likewise.
(insert_rbs): Likewise.
(insert_rcs): Likewise.
(insert_simm3s): Likewise.
(insert_rrange): Likewise.
(insert_fpel): Likewise.
(insert_blinkel): Likewise.
(insert_pcel): Likewise.
(insert_nps_3bit_dst): Likewise.
(insert_nps_3bit_dst_short): Likewise.
(insert_nps_3bit_src2_short): Likewise.
(insert_nps_bitop_size_2b): Likewise.
(MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
(RA_CHK): Define.
(RB): Adjust.
(RB_CHK): Define.
(RC): Adjust.
* arc-dis.c (print_insn_arc): Add LOAD and STORE class.
* arc-tbl.h (div, divu): All instructions are DIVREM class.
Change first insn argument to check for LP_COUNT usage.
(rem): Likewise.
(ld, ldd): All instructions are LOAD class. Change first insn
argument to check for LP_COUNT usage.
(st, std): All instructions are STORE class.
(mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
Change first insn argument to check for LP_COUNT usage.
(mov): All instructions are MOVE class. Change first insn
argument to check for LP_COUNT usage.
include/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE
instruction classes.
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This patch fixes:
- fpus and fpud are swaped.
- quarkse_em doesn't include FPX extensions.
- auto guessed opcode mechanism may ignore the option passed via -M<feature> option.
opcodes/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (is_compatible_p): Remove function.
(skip_this_opcode): Don't add any decoding class to decode list.
Remove warning.
(find_format_from_table): Go through all opcodes, and warn if we
use a guessed mnemonic.
binutils/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/binutils-all/arc/objdump.exp (Warning test): Update
test.
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gas/ChangeLog:
* testsuite/gas/arc/nps-400-9.d: Added.
* testsuite/gas/arc/nps-400-9.s: Added.
include/ChangeLog:
* opcode/arc.h: Add PROTOCOL_DECODE to insn_class_t.
opcodes/ChangeLog:
* arc-dis.c (arc_insn_length): Return length 8 for instructions with
major opcode 0xa.
* arc-nps-400-tbl.h: Add dcmac instruction.
* arc-opc.c (arc_operands): Added operands for dcmac instruction.
(insert_nps_rbdouble_64): Added.
(extract_nps_rbdouble_64): Added.
(insert_nps_proto_size): Added.
(extract_nps_proto_size): Added.
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The current handling for arc instructions longer than 32-bits is all
handled as a special case in both the assembler and disassembler.
The problem with this approach is that it leads to code duplication,
selecting a long instruction is exactly the same process as selecting a
short instruction, except over more bits, in both cases we select based
on bit comparison, and initial operand insertion and extraction.
This commit unifies both the long and short instruction worlds,
converting the core opcodes library from being largely 32-bit focused,
to being largely 64-bit focused.
The changes are, on the whole, not too much. There's obviously a lot of
type changes but otherwise the bulk of the code just works. Most of the
actual functional changes are to code that previously handled the longer
48 or 64 bit instructions. The insert/extract handlers for these have
now been brought into line with the short instruction insert/extract
handlers.
All of the special case handling code that was previously added has now
been removed again. Overall, this commit reduces the amount of code in
the arc assembler and disassembler.
gas/ChangeLog:
* config/tc-arc.c (struct arc_insn): Change type of insn field.
(md_number_to_chars_midend): Support 6- and 8-byte values.
(emit_insn0): Update debug output.
(find_opcode_match): Likewise.
(build_fake_opcode_hash_entry): Delete.
(find_special_case_long_opcode): Delete.
(find_special_case): Remove long format special case handling.
(insert_operand): Change instruction type and update debug print
format.
(assemble_insn): Change instruction type, update debug print
formats, and remove unneeded assert.
include/ChangeLog:
* opcode/arc.h (struct arc_opcode): Change type of opcode and mask
fields.
(struct arc_long_opcode): Delete.
(struct arc_operand): Change types for insert and extract
handlers.
opcodes/ChangeLog:
* arc-dis.c (struct arc_operand_iterator): Remove all fields
relating to long instruction processing, add new limm field.
(OPCODE): Rename to...
(OPCODE_32BIT_INSN): ...this.
(OPCODE_AC): Delete.
(skip_this_opcode): Handle different instruction lengths, update
macro name.
(special_flag_p): Update parameter type.
(find_format_from_table): Update for more instruction lengths.
(find_format_long_instructions): Delete.
(find_format): Update for more instruction lengths.
(arc_insn_length): Likewise.
(extract_operand_value): Update for more instruction lengths.
(operand_iterator_next): Remove code relating to long
instructions.
(arc_opcode_to_insn_type): New function.
(print_insn_arc):Update for more instructions lengths.
* arc-ext.c (extInstruction_t): Change argument type.
* arc-ext.h (extInstruction_t): Change argument type.
* arc-fxi.h: Change type unsigned to unsigned long long
extensively throughout.
* arc-nps400-tbl.h: Add long instructions taken from
arc_long_opcodes table in arc-opc.c.
* arc-opc.c: Update parameter types on insert/extract handlers.
(arc_long_opcodes): Delete.
(arc_num_long_opcodes): Delete.
(arc_opcode_len): Update for more instruction lengths.
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highbyte and lowbyte actually refer to the low byte and the high
byte respectively, but are used consistently in this swapped
order. This commit swaps them round so that highbyte refers to the
high byte and lowbyte refers to the low byte.
There should be no functional change after this commit.
opcodes/ChangeLog:
* arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
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In preparation for moving to a world where arc instructions can be 2, 4,
6, or 8 bytes in length, replace the ARC_SHORT macro (which is either
true of false) with an arc_opcode_len function that returns a length in
bytes.
There should be no functional change after this commit.
gas/ChangeLog:
* config/tc-arc.c (assemble_insn): Replace use of ARC_SHORT with
arc_opcode_len.
include/ChangeLog:
* opcode/arc.h (arc_opcode_len): Declare.
(ARC_SHORT): Delete.
opcodes/ChangeLog:
* arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
with arc_opcode_len.
(find_format_long_instructions): Likewise.
* arc-opc.c (arc_opcode_len): New function.
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The ARC (short) instructions are using a special register number to
indicate is the instruction uses a long immediate (LIMM). In the case
of short instruction, this LIMM indicator depends on the ISA version
used. Thus, for ARCv1 processors, the LIMM indicator is 0x3E, the same
value used in "long" instructions. However, for the ARCv2 processors,
this LIMM indicator is 0x1E.
This patch fixes the LIMM detection for ARCv1 ISA and adds two tests.
gas/
2016-10-13 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/shortlimm_a7.d: New file.
* testsuite/gas/arc/shortlimm_a7.s: Likewise.
* testsuite/gas/arc/shortlimm_hs.d: Likewise.
* testsuite/gas/arc/shortlimm_hs.s: Likewise.
include/
2016-10-13 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (ARC_OPCODE_ARCV2): New define.
opcodes/
2016-10-13 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (find_format_from_table): Discriminate LIMM indicator
usage on ISA basis.
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Comment changes.
bfd/
* coff-h8300.c: Spell fall through comments consistently.
* coffgen.c: Likewise.
* elf32-hppa.c: Likewise.
* elf32-ppc.c: Likewise.
* elf32-score.c: Likewise.
* elf32-score7.c: Likewise.
* elf64-ppc.c: Likewise.
* elfxx-aarch64.c: Likewise.
* elfxx-mips.c: Likewise.
* cpu-ns32k.c: Add missing fall through comments.
* elf-m10300.c: Likewise.
* elf32-arm.c: Likewise.
* elf32-avr.c: Likewise.
* elf32-bfin.c: Likewise.
* elf32-frv.c: Likewise.
* elf32-i386.c: Likewise.
* elf32-microblaze.c: Likewise.
* elf32-nds32.c: Likewise.
* elf32-ppc.c: Likewise.
* elf32-rl78.c: Likewise.
* elf32-rx.c: Likewise.
* elf32-s390.c: Likewise.
* elf32-sh.c: Likewise.
* elf32-tic6x.c: Likewise.
* elf64-ia64-vms.c: Likewise.
* elf64-ppc.c: Likewise.
* elf64-s390.c: Likewise.
* elf64-x86-64.c: Likewise.
* elflink.c: Likewise.
* elfnn-aarch64.c: Likewise.
* elfnn-ia64.c: Likewise.
* ieee.c: Likewise.
* oasys.c: Likewise.
* pdp11.c: Likewise.
* srec.c: Likewise.
* versados.c: Likewise.
opcodes/
* aarch64-opc.c: Spell fall through comments consistently.
* i386-dis.c: Likewise.
* aarch64-dis.c: Add missing fall through comments.
* aarch64-opc.c: Likewise.
* arc-dis.c: Likewise.
* arm-dis.c: Likewise.
* i386-dis.c: Likewise.
* m68k-dis.c: Likewise.
* mep-asm.c: Likewise.
* ns32k-dis.c: Likewise.
* sh-dis.c: Likewise.
* tic4x-dis.c: Likewise.
* tic6x-dis.c: Likewise.
* vax-dis.c: Likewise.
binutils/
* dlltool.c: Spell fall through comments consistently.
* objcopy.c: Likewise.
* readelf.c: Likewise.
* dwarf.c: Add missing fall through comments.
* elfcomm.c: Likewise.
* sysinfo.y: Likewise.
* readelf.c: Likewise. Also remove extraneous comments.
gas/
* app.c: Add missing fall through comments.
* dw2gencfi.c: Likewise.
* expr.c: Likewise.
* config/tc-alpha.c: Likewise.
* config/tc-arc.c: Likewise.
* config/tc-arm.c: Likewise.
* config/tc-cr16.c: Likewise.
* config/tc-crx.c: Likewise.
* config/tc-dlx.c: Likewise.
* config/tc-h8300.c: Likewise.
* config/tc-hppa.c: Likewise.
* config/tc-i370.c: Likewise.
* config/tc-i386.c: Likewise.
* config/tc-i960.c: Likewise.
* config/tc-ia64.c: Likewise.
* config/tc-m68hc11.c: Likewise.
* config/tc-m68k.c: Likewise.
* config/tc-mep.c: Likewise.
* config/tc-metag.c: Likewise.
* config/tc-microblaze.c: Likewise.
* config/tc-mips.c: Likewise.
* config/tc-ns32k.c: Likewise.
* config/tc-rx.c: Likewise.
* config/tc-score.c: Likewise.
* config/tc-score7.c: Likewise.
* config/tc-sh.c: Likewise.
* config/tc-tic4x.c: Likewise.
* config/tc-vax.c: Likewise.
* config/tc-xstormy16.c: Likewise.
* config/tc-z80.c: Likewise.
* config/tc-z8k.c: Likewise.
* config/obj-elf.c: Likewise.
* config/tc-i386.c: Likewise.
* depend.c: Spell fall through comments consistently.
* config/tc-arm.c: Likewise.
* config/tc-d10v.c: Likewise.
* config/tc-i960.c: Likewise.
* config/tc-ia64.c: Likewise.
* config/tc-m68k.c: Likewise.
* config/tc-mcore.c: Likewise.
* config/tc-mep.c: Likewise.
* config/tc-ns32k.c: Likewise.
* config/tc-visium.c: Likewise.
* config/tc-xstormy16.c: Likewise.
* config/tc-z8k.c: Likewise.
gprof/
* gprof.c: Add missing fall through comments.
ld/
* lexsup.c: Spell fall through comments consistently and add
missing fall through comments.
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For each MAJOR-MINOR opcode tuple, we can have either a 3-operand, or
2-operand, or a single operand instruction format, depending on the
values present in i-field, and a-field.
The disassembler is reading the section containing the extension
instruction format and stores them in a table. Each table element
represents a linked list with encodings for a particular MAJOR-MINOR
tuple.
The current implementation checks only against the first element of
the list, hence, the issue.
This patch is walking the linked list until empty or finds an opcode
match. It also adds a test outlining the found problem.
opcodes/
2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (find_format): Walk the linked list pointed by einsn.
gas/
2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsnxop.d: New file.
* testsuite/gas/arc/textinsnxop.s: Likewise.
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present.
* arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
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Variable "header" in function is set conditionally, but was accessed without
verifying if pointer was NULL.
opcodes/ChangeLog:
Cupertino Miranda <cmiranda@synopsys.com>
* opcodes/arc-dis.c (print_insn_arc): Changed.
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opcodes * arc-nps400-tbl.h: Change block comments to GNU format.
* arc-dis.c: Add new globals addrtypenames,
addrtypenames_max, and addtypeunknown.
(get_addrtype): New function.
(print_insn_arc): Print colons and address types when
required.
* arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
define insert and extract functions for all address types.
(arc_operands): Add operands for colon and all address
types.
* arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
* arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
* arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
* arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
include * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,
ARC_OPERAND_COLON. Add the arc_nps_address_type enum and
ARC_NUM_ADDRTYPES.
* opcode/arc.h: Add BMU to insn_class_t enum.
* opcode/arc.h: Add PMU to insn_class_t enum.
gas * config/tc-arc.c: Add new global arc_addrtype_hash.
Define O_colon and O_addrtype.
(debug_exp): Add O_colon and O_addrtype.
(tokenize_arguments): Handle colon and address type
tokens.
(declare_addrtype): New function.
(md_begin): Initialise arc_addrtype_hash.
(arc_parse_name): Add lookup of address types.
(assemble_insn): Handle colons and address types by
ignoring them.
* testsuite/gas/arc/nps400-8.s: New file.
* testsuite/gas/arc/nps400-8.d: New file.
* testsuite/gas/arc/nps400-8.s: Add PMU instruction tests.
* testsuite/gas/arc/nps400-8.d: Add expected PMU
instruction output.
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gas * testsuite/gas/arc/dsp.d: New file.
* testsuite/gas/arc/dsp.s: Likewise.
* testsuite/gas/arc/fpu.d: Likewise.
* testsuite/gas/arc/fpu.s: Likewise.
* testsuite/gas/arc/ext2op.d: Add specific disassembler option.
* testsuite/gas/arc/ext3op.d: Likewise.
* testsuite/gas/arc/tdpfp.d: Likewise.
* testsuite/gas/arc/tfpuda.d: Likewise.
opcodes * arc-dis.c (skipclass): New structure.
(decodelist): New variable.
(is_compatible_p): New function.
(new_element): Likewise.
(skip_class_p): Likewise.
(find_format_from_table): Use skip_class_p function.
(find_format): Decode first the extension instructions.
(print_insn_arc): Select either ARCEM or ARCHS based on elf
e_flags.
(parse_option): New function.
(parse_disassembler_options): Likewise.
(print_arc_disassembler_options): Likewise.
(print_insn_arc): Use parse_disassembler_options function. Proper
select ARCv2 cpu variant.
* disassemble.c (disassembler_usage): Add ARC disassembler
options.
binutils* doc/binutils.texi (objdump): Add ARC disassembler options.
* testsuite/binutils-all/arc/dsp.s: New file.
* testsuite/binutils-all/arc/objdump.exp: Likewise.
include * dis-asm.h: Declare print_arc_disassembler_options.
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gas * config/tc-arc.c (check_cpu_feature, md_parse_option):
Add nps400 option and feature. Add check for nps400
feature. Refactor existing checks to check subclass before
feature enablement.
(md_show_usage): Document flags for NPS-400 and add some other
undocumented flags.
(cpu_type): Remove nps400 CPU type entry
(check_zol): Remove bfd_mach_arc_nps400 case.
(md_show_usage): Add help on -mcpu=nps400.
(cpu_types): Add entry for nps400 as arc700 plus nps400 extension
set.
* doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and
-fpuda flags. Document -mcpu=nps400.
* testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change
expected flags to match ARC700 instead of NPS400.
* testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400.
* testsuite/gas/arc/nps-400-2.d: Likewise.
* testsuite/gas/arc/nps-400-3.d: Likewise.
* testsuite/gas/arc/nps-400-4.d: Likewise.
* testsuite/gas/arc/nps-400-5.d: Likewise.
* testsuite/gas/arc/nps-400-6.d: Likewise.
* testsuite/gas/arc/nps-400-7.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to
avoid clash with cbba instruction.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using
-mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags.
binutils* readelf.c (decode_ARC_machine_flags): Remove E_ARC_MACH_NPS400
case.
ld * testsuite/ld-arc/nps-1a.d: Use -mcpu=arc700 -mnps400.
* testsuite/ld-arc/nps-1b.d: Likewise.
include * opcode/arc.h: Add nps400 extension and instruction
subclass.
Remove ARC_OPCODE_NPS400
* elf/arc.h: Remove E_ARC_MACH_NPS400
opcodes * arc-dis.c (arc_insn_length): Add comment on instruction length.
Use same method for determining instruction length on ARC700 and
NPS-400.
(arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
* arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
with the NPS400 subclass.
* arc-opc.c: Likewise.
bfd * archures.c: Remove bfd_mach_arc_nps400.
* bfd-in2.h: Likewise.
* cpu-arc.c (arch_info_struct): Likewise.
* elf32-arc.c (arc_elf_object_p, arc_elf_final_write_processing):
Likewise.
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gas * config/tc-arc.c (parse_opcode_flags): New function.
(find_opcode_match): Move flag parsing code out to new function.
Ignore operands marked IGNORE.
(build_fake_opcode_hash_entry): New function.
(find_special_case_long_opcode): New function.
(find_special_case): Lookup long opcodes.
* testsuite/gas/arc/nps400-7.d: New file.
* testsuite/gas/arc/nps400-7.s: New file.
include * opcode/arc.h (MAX_INSN_ARGS): Increase to 16.
(struct arc_long_opcode): New structure.
(arc_long_opcodes): Declare.
(arc_num_long_opcodes): Declare.
opcodes * arc-dis.c (struct arc_operand_iterator): New structure.
(find_format_from_table): All the old content from find_format,
with some minor adjustments, and parameter renaming.
(find_format_long_instructions): New function.
(find_format): Rewritten.
(arc_insn_length): Add LSB parameter.
(extract_operand_value): New function.
(operand_iterator_next): New function.
(print_insn_arc): Use new functions to find opcode, and iterator
over operands.
* arc-opc.c (insert_nps_3bit_dst_short): New function.
(extract_nps_3bit_dst_short): New function.
(insert_nps_3bit_src2_short): New function.
(extract_nps_3bit_src2_short): New function.
(insert_nps_bitop1_size): New function.
(extract_nps_bitop1_size): New function.
(insert_nps_bitop2_size): New function.
(extract_nps_bitop2_size): New function.
(insert_nps_bitop_mod4_msb): New function.
(extract_nps_bitop_mod4_msb): New function.
(insert_nps_bitop_mod4_lsb): New function.
(extract_nps_bitop_mod4_lsb): New function.
(insert_nps_bitop_dst_pos3_pos4): New function.
(extract_nps_bitop_dst_pos3_pos4): New function.
(insert_nps_bitop_ins_ext): New function.
(extract_nps_bitop_ins_ext): New function.
(arc_operands): Add new operands.
(arc_long_opcodes): New global array.
(arc_num_long_opcodes): New global.
* arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
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This patch corrects the instructioninformation passed into the
disassebler_info structure.
include/
2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (insn_subclass_t): Add COND.
(flag_class_t): Add F_CLASS_EXTEND.
opcodes/
2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
information.
(print_insn_arc): Set insn_type information.
* arc-opc.c (C_CC): Add F_CLASS_COND.
* arc-tbl.h (bbit0, bbit1): Update subclass to COND.
(beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
(ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
(breq, breq_s, brge, brhs, brlo, brlt): Likewise.
(brne, brne_s, jeq_s, jne_s): Likewise.
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gas/
2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
* config/tc-arc.c (attributes_t): Renamed attribute class to
attr_class.
(find_opcode_match, assemble_insn, tokenize_extinsn): Changed.
opcode/
2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
* arc-dis.c (find_format, find_format, get_auxreg)
(print_insn_arc): Changed.
* arc-ext.h (INSERT_XOP): Likewise.
include/
2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
* opcode/arc.h (struct arc_opcode): Renamed attribute class to
insn_class.
(struct arc_flag_class): Renamed attribute class to flag_class.
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Move the logic that calculates the instruction length out to a new
function. Restructure the code to make it simpler.
opcodes/ChangeLog:
* arc-dis.c (arc_insn_length): New function.
(print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
(find_format): Change insnLen parameter to unsigned.
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gas/
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textauxregister.d: New file.
* testsuite/gas/arc/textauxregister.s: Likewise.
* testsuite/gas/arc/textcondcode.d: Likewise.
* testsuite/gas/arc/textcondcode.s: Likewise.
* testsuite/gas/arc/textcoreregister.d: Likewise.
* testsuite/gas/arc/textcoreregister.s: Likewise.
* testsuite/gas/arc/textpseudoop.d: Likewise.
* testsuite/gas/arc/textpseudoop.s: Likewise.
* testsuite/gas/arc/ld2.d: Update test.
* testsuite/gas/arc/st.d: Likewise.
* testsuite/gas/arc/taux.d: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extCondCode,
.extCoreRegister and .extAuxRegister documentation.
* config/tc-arc.c (arc_extcorereg): New function.
(md_pseudo_table): Add .extCondCode, .extCoreRegister and
.extAuxRegister pseudo-ops.
(extRegister_t): New type.
(ext_condcode, arc_aux_hash): New global variable.
(find_opcode_match): Check for extensions.
(preprocess_operands): Likewise.
(md_begin): Add aux registers in a hash.
(assemble_insn): Update use arc_flags member.
(tokenize_extregister): New function.
(create_extcore_section): Likewise.
* config/tc-arc.h (MAX_FLAG_NAME_LENGHT): Increase to 10.
(arc_flags): Delete code, add flgp.
include/
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (flag_class_t): Update.
(ARC_OPCODE_NONE): Define.
(ARC_OPCODE_ARCALL): Likewise.
(ARC_OPCODE_ARCFPX): Likewise.
(ARC_REGISTER_READONLY): Likewise.
(ARC_REGISTER_WRITEONLY): Likewise.
(ARC_REGISTER_NOSHORT_CUT): Likewise.
(arc_aux_reg): Add cpu.
opcodes/
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (find_format): Check for extension flags.
(print_flags): New function.
(print_insn_arc): Update for .extCondCode, .extCoreRegister and
.extAuxRegister.
* arc-ext.c (arcExtMap_coreRegName): Use
LAST_EXTENSION_CORE_REGISTER.
(arcExtMap_coreReadWrite): Likewise.
(dump_ARC_extmap): Update printing.
* arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
(arc_aux_regs): Add cpu field.
* arc-regs.h: Add cpu field, lower case name aux registers.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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gas/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsn-errors.d: New File.
* testsuite/gas/arc/textinsn-errors.err: Likewise.
* testsuite/gas/arc/textinsn-errors.s: Likewise.
* testsuite/gas/arc/textinsn2op.d: Likewise.
* testsuite/gas/arc/textinsn2op.s: Likewise.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extInstruction
documentation.
* config/tc-arc.c (arcext_section): New variable.
(arc_extinsn): New function.
(md_pseudo_table): Add .extInstruction pseudo op.
(attributes_t): New type.
(suffixclass, syntaxclass, syntaxclassmod): New constant
structures.
(find_opcode_match): Remove arc_num_opcodes.
(md_begin): Likewise.
(tokenize_extinsn): New function.
(arc_set_ext_seg): Likewise.
(create_extinst_section): Likewise.
include/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (arc_num_opcodes): Remove.
(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
(ARC_SUFFIX_FLAG): Define.
(flags_none, flags_f, flags_cc, flags_ccf): Declare.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
opcodes/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
Initialize.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
(arc_opcode arc_opcodes): Null terminate the array.
(arc_num_opcodes): Remove.
* arc-ext.h (INSERT_XOP): Define.
(extInstruction_t): Likewise.
(arcExtMap_instName): Delete.
(arcExtMap_insn): New function.
(arcExtMap_genOpcode): Likewise.
* arc-ext.c (ExtInstruction): Remove.
(create_map): Zero initialize instruction fields.
(arcExtMap_instName): Remove.
(arcExtMap_insn): New function.
(dump_ARC_extmap): More info while debuging.
(arcExtMap_genOpcode): New function.
* arc-dis.c (find_format): New function.
(print_insn_arc): Use find_format.
(arc_get_disassembler): Enable dump_ARC_extmap only when
debugging.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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gas/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/ext2op.d: New file.
* testsuite/gas/arc/ext2op.s: Likewise.
* testsuite/gas/arc/ext3op.d: Likewise.
* testsuite/gas/arc/ext3op.s: Likewise.
opcodes/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* arc-tbl.h (invld07): Remove.
* arc-ext-tbl.h: New file.
* arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
* arc-opc.c (arc_opcodes): Add ext-tbl include.
include/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
(FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
(INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
(INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
(INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
(INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
(INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
(MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
(MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
(MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
(MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
(MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
(INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
(MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
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This commit introduces the nps400 machine type as a variant of arc.
There's a new flag in the assembler to select this machine type. All
other changes are just adding handling of the new machine type into the
relevant places.
The nps400 is an arc700 variant with some vendor specific instructions
added into the instruction set. This commit does not add any of the new
instructions, this is just laying the groundwork for future commits.
However, in preparation for these new instructions a new opcode define for
nps400 has been added to include/opcode/arc.h, this new opcode define is
used in the assembler and disassembler along with the existing define
for arc700 such that when assembling and disassembling for nps400 the
user will have access to all arc700 instructions and all the nps400
vendor extension instructions.
bfd/ChangeLog:
* archures.c (bfd_mach_arc_nps400): Define.
* bfd-in2.h: Regenerate.
* cpu-arc.c (arch_info_struct): New entry for nps400, renumber
some existing entries to make space.
* elf32-arc.c (arc_elf_object_p): Add nps400 case.
(arc_elf_final_write_processing): Likewise.
binutils/ChangeLog:
* readelf.c (decode_ARC_machine_flags): Handle nps400.
gas/ChangeLog:
* config/tc-arc.c (cpu_types): Add nps400 entry.
(check_zol): Handle nps400.
include/ChangeLog:
* elf/arc.h (E_ARC_MACH_NPS400): Define.
* opcode/arc.h (ARC_OPCODE_NPS400): Define.
opcodes/ChangeLog:
* arc-dis.c (print_insn_arc): Handle nps400.
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gas * config/tc-arc.c (arc_option): Sets all internal gas options when
parsing .cpu directive.
(declare_register_set): Declare all 64 registers.
(md_section_align): Refactor.
(md_pcrel_from_section): Remove assert.
(pseudo_operand_match): Fix pseudo operand match.
(find_reloc): Use flags filed, extend matching.
* config/tc-arc.h (TC_VALIDATE_FIX): Don't fixup any PLT
relocation.
testsuite * gas/arc/bic.d: Update test.
* gas/arc/add_s-err.s: New file.
* gas/arc/cpu-warn1.s: Likewise.
* gas/arc/pcl-relocs.d: Likewise.
* gas/arc/pcl-relocs.s: Likewise.
* gas/arc/pcrel-relocs.d: Likewise.
* gas/arc/pcrel-relocs.s: Likewise.
* gas/arc/pic-relocs.d: Likewise.
* gas/arc/pic-relocs.s: Likewise.
* gas/arc/plt-relocs.d: Likewise.
* gas/arc/plt-relocs.s: Likewise.
* gas/arc/pseudos.d: Likewise.
* gas/arc/pseudos.s: Likewise.
* gas/arc/sda-relocs.d: Likewise.
* gas/arc/sda-relocs.s: Likewise.
* gas/arc/sda-relocs2.d: Likewise.
* gas/arc/sda-relocs2.s: Likewise.
* gas/arc/tls-relocs.d: Likewise.
* gas/arc/tls-relocs.s: Likewise.
opcode * arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32].
opcodes * arc-dis.c (special_flag_p): Match full mnemonic.
* arc-opc.c (print_insn_arc): Check section size to read
appropriate number of bytes. Fix printing.
* arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
arguments.
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bfd * archures.c: Remove support for older ARC. Added support for new
ARC cpus (ARC600, ARC601, ARC700, ARCV2).
* bfd-in2.h: Likewise.
* config.bfd: Likewise.
* cpu-arc.c: Likewise.
* elf32-arc.c: Totally changed file with a refactored
inplementation of the ARC port.
* libbfd.h: Added ARC specific relocation types.
* reloc.c: Likewise.
gas * config/tc-arc.c: Revamped file for ARC support.
* config/tc-arc.h: Likewise.
* doc/as.texinfo: Add new ARC options.
* doc/c-arc.texi: Likewise.
ld * configure.tgt: Added target arc-*-elf* and arc*-*-linux-uclibc*.
* emulparams/arcebelf_prof.sh: New file
* emulparams/arcebelf.sh: Likewise.
* emulparams/arceblinux_prof.sh: Likewise.
* emulparams/arceblinux.sh: Likewise.
* emulparams/arcelf_prof.sh: Likewise.
* emulparams/arcelf.sh: Likewise.
* emulparams/arclinux_prof.sh: Likewise.
* emulparams/arclinux.sh: Likewise.
* emulparams/arcv2elfx.sh: Likewise.
* emulparams/arcv2elf.sh: Likewise.
* emultempl/arclinux.em: Likewise.
* scripttempl/arclinux.sc: Likewise.
* scripttempl/elfarc.sc: Likewise.
* scripttempl/elfarcv2.sc: Likewise
* Makefile.am: Add new ARC emulations.
* Makefile.in: Regenerate.
* NEWS: Mention the new feature.
opcodes * arc-dis.c: Revamped file for ARC support
* arc-dis.h: Likewise.
* arc-ext.c: Likewise.
* arc-ext.h: Likewise.
* arc-opc.c: Likewise.
* arc-fxi.h: New file.
* arc-regs.h: Likewise.
* arc-tbl.h: Likewise.
binutils * readelf.c (get_machine_name): Remove A5 reference. Add ARCompact
and ARCv2.
(get_machine_flags): Handle EM_ARCV2 and EM_ARCOMPACT.
(guess_is_rela): Likewise.
(dump_relocations): Likewise.
(is_32bit_abs_reloc): Likewise.
(is_16bit_abs_reloc): Likewise.
(is_none_reloc): Likewise.
* NEWS: Mention the new feature.
include * dis-asm.h (arc_get_disassembler): Correct declaration.
* arc-reloc.def: Macro file with definition of all relocation
types.
* arc.h: Changed macros for the newly supported ARC cpus. Altered
enum defining the supported relocations.
* common.h: Changed EM_ARC_A5 definition to EM_ARC_COMPACT. Added
macro for EM_ARC_COMPACT2.
* arc-func.h: New file.
* arc.h: Likewise.
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value with a default.
(do_special_encoding): Likewise.
(aarch64_ins_ldst_elemlist): Pre-initialize QSsize, and opcodeh2
variables with default.
* arc-dis.c (write_comments_): Don't use strncat due
size of state->commentBuffer pointer isn't predictable.
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* bfin-dis.c: Likewise.
* i860-dis.c: Likewise.
* ia64-dis.c: Likewise.
* ia64-gen.c: Likewise.
* m68hc11-dis.c: Likewise.
* mmix-dis.c: Likewise.
* msp430-dis.c: Likewise.
* or32-dis.c: Likewise.
* rl78-dis.c: Likewise.
* rx-dis.c: Likewise.
* tic4x-dis.c: Likewise.
* tilegx-opc.c: Likewise.
* tilepro-opc.c: Likewise.
* rx-decode.c: Regenerate.
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(FIELDD): Sign extend with xor,sub.
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with -Wc++-compat:
* config/tc-alpha.c: Add casts.
(extended_bfd_reloc_code_real_type): New type. Used to avoid
enumeration conversion warnings.
(struct alpha_fixup, void assemble_insn, assemble_insn)
(assemble_tokens): Use new type.
* ecoff.c: Add casts. (mark_stabs): Use enumeration names.
* config/obj-elf.c: Add cast
* config/tc-arc.c: Add casts.
* config/obj-aout.h (text_section,data_section,bss_section):
Make extern.
* config/obj-elf.c: Add cast.
* config/tc-arm.c: Add casts.
(X, TxCE, TxCE, TxC3, TxC3w, TxCM_, TxCM, TUE, TUF, CE, CL, cCE)
(cCL, C3E, xCM_, nUF, nCE_tag): Change input format to avoid the
need for keywords as arguments.
* ecoff.c: Add casts.
* ecofflink.c: Add casts.
* elf64-alpha.c: Add casts.
(struct alpha_elf_got_entry, struct alpha_elf_reloc_entry): Move
to top level.
(SKIP_HOWTO): Use enum name.
* elf32-arm.c: Add casts.
(elf32_arm_vxworks_bed): Update code to avoid multiple
declarations.
(struct map_stub): Move to top level.
* arc-dis.c Fix casts.
* arc-ext.c: Add casts.
* arm-dis.c (enum opcode_sentinel_enum): Gave name to anonymous
enum.
* emultempl/armelf.em: Add casts.
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bfd:
* elf32-xtensa.c (vsprint_msg): Add format attribute. Fix
format bugs.
* vms.h (_bfd_vms_debug): Add format attribute.
(_bfd_vms_debug, _bfd_hexdump): Fix typos.
binutils:
* bucomm.h (report): Add format attribute.
* dlltool.c (inform): Likewise.
* dllwrap.c (display, inform, warn): Likewise.
* objdump.c (objdump_sprintf): Likewise.
* readelf.c (error, warn): Likewise. Fix format bugs.
gas:
* config/tc-tic30.c (debug): Add format attribute. Fix format
bugs.
include:
* dis-asm.h (fprintf_ftype): Add format attribute.
opcodes:
* arc-dis.c, arm-dis.c, cris-dis.c, crx-dis.c, d10v-dis.c,
d30v-dis.c, fr30-dis.c, h8300-dis.c, h8500-dis.c, i860-dis.c,
ia64-dis.c, ip2k-dis.c, m10200-dis.c, m10300-dis.c,
m88k-dis.c, mcore-dis.c, mips-dis.c, ms1-dis.c, or32-dis.c,
ppc-dis.c, sh64-dis.c, sparc-dis.c, tic4x-dis.c, tic80-dis.c,
v850-dis.c: Fix format bugs.
* ia64-gen.c (fail, warn): Add format attribute.
* or32-opc.c (debug): Likewise.
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* opcodes/arc-dis.c:Add enum a4_decoding_class.
(dsmOneArcInst): Use the enum values for the decoding class
Remove redundant case in the switch for decodingClass value 11
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* Makefile.in: Regenerate.
* arc-dis.c: Use #include "" instead of <> for local header files.
* m68k-dis.c: Likewise.
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(my_sprintf): Define using VPARAMS, VA_OPEN, VA_FIXEDARG, VA_CLOSE.
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* openrisc-desc.c: Likewise.
* openrisc-ibld.c: Likewise.
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* a29k-dis.c: Likewise.
* arc-dis.c: Likewise.
* ia64-opc.c: Likewise.
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