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path: root/opcodes/arc-dis.c
AgeCommit message (Expand)AuthorFilesLines
2017-11-21[ARC] Improve printing of pc-relative instructions.claziss1-16/+46
2017-11-03[ARC] Force the disassam to use the hexadecimal number for printingclaziss1-1/+13
2017-11-03[ARC] Sync opcode data base.claziss1-0/+1
2017-06-29[ARC] Use FOR_EACH_DISASSEMBLER_OPTION to iterate over optionsAnton Kolesov1-14/+6
2017-06-29[ARC] Fix handling of cpu=... disassembler option valueAnton Kolesov1-8/+8
2017-05-30[ARC] Allow CPU to be enforced via disassemble_info optionsAnton Kolesov1-26/+105
2017-05-10[ARC] Object attributes.Claudiu Zissulescu1-1/+2
2017-04-25[ARC] Enhance enter/leave mnemonics.Claudiu Zissulescu1-3/+16
2017-04-05-Wwrite-strings: Constify struct disassemble_info's disassembler_options fieldPedro Alves1-2/+2
2017-02-06[ARC] Provide an interface to decode ARC instructions.Claudiu Zissulescu1-37/+174
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-11-29[ARC] Add checking for LP_COUNT reg usage, improve error reporting.Claudiu Zissulescu1-1/+3
2016-11-29[ARC] Fix disassembler option.Claudiu Zissulescu1-55/+40
2016-11-03arc: Implement NPS-400 dcmac instructionGraham Markall1-0/+4
2016-11-03arc: Change max instruction length to 64-bitsAndrew Burgess1-282/+189
2016-11-03arc: Swap highbyte and lowbyte in print_insn_arcGraham Markall1-4/+4
2016-11-03arc: Replace ARC_SHORT macro with arc_opcode_len functionGraham Markall1-4/+4
2016-10-14[ARC] Disassembler: fix LIMM detection for short instructions.Claudiu Zissulescu1-2/+3
2016-10-06-Wimplicit-fallthrough warning fixesAlan Modra1-0/+1
2016-09-16[ARC] Disassemble correctly extension instructions.Claudiu Zissulescu1-3/+3
2016-09-14Stop the ARC disassembler from seg-faulting if initialised without a BFD pres...Anton Kolesov1-3/+8
2016-08-30Fixed issue with NULL pointer access on header var.Cupertino Miranda1-1/+4
2016-07-27Begin implementing ARC NPS-400 Accelerator instructionsGraham Markall1-5/+40
2016-07-20Add support to the ARC disassembler for selecting instruction classes.Claudiu Zissulescu1-127/+342
2016-06-21Arc assembler: Convert nps400 from a machine type to an extension.Graham Markall1-6/+6
2016-06-02Add support for 48 and 64 bit ARC instructions.Andrew Burgess1-92/+377
2016-05-23[ARC] Update instruction type and delay slot info.Claudiu Zissulescu1-6/+25
2016-05-23[ARC] Rename "class" named attributes.Claudiu Zissulescu1-4/+4
2016-04-14opcodes/arc: Move instruction length logic to new functionAndrew Burgess1-13/+44
2016-04-12Add support for .extCondCode, .extCoreRegister and .extAuxRegister.Claudiu Zissulescu1-62/+153
2016-04-12Add support for .extInstruction pseudo-op.Claudiu Zissulescu1-99/+129
2016-03-29[ARC] Add support for Quarkse opcodes.Claudiu Zissulescu1-3/+0
2016-03-21arc: Add nps400 machine type, and assembler flag.Andrew Burgess1-0/+4
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-12-04Fix failures in the GAS testsuite for the ARC architecture.Claudiu Zissulescu1-29/+60
2015-10-08Fix compile time warning compiling ARC port.Nick Clifton1-1/+2
2015-10-07New ARC implementation.Nick Clifton1-1083/+416
2015-08-12Remove trailing spaces in opcodesH.J. Lu1-3/+3
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-03-05Update copyright yearsAlan Modra1-2/+1
2012-10-18 * aarch64-asm.c (aarch64_ins_ldst_reglist): InitializeKai Tietz1-2/+1
2012-05-18 * arc-dis.c: Include sysdep.h first, remove some redundant includes.Alan Modra1-2/+1
2012-02-27 * arc-dis.c (BITS): Don't use shifts to mask off bits.Alan Modra1-6/+5
2010-06-27fix set but unused variable warningsAlan Modra1-5/+2
2009-09-25 Update soruces to make alpha, arc and arm targets compile cleanlyNick Clifton1-3/+3
2007-07-05Change source files over to GPLv3.Nick Clifton1-8/+10
2005-07-07Kaveh Ghazi's printf format attribute checking patch.Jim Wilson1-1/+1
2005-07-01Update function declarations to ISO C90 formattingNick Clifton1-150/+116
2005-05-07Update the address and phone number of the FSFNick Clifton1-1/+1
2005-03-032005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>Ramana Radhakrishnan1-29/+48
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